Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ Tcr (Upper 8 Bits)]; Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ Tmdr (Lower 8 Bits)]; Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ Tcr And Tmdr (16 Bits)] - Renesas H8S Series Hardware Manual

Section 12 16-Bit Timer Pulse Unit (TPU)
Internal data bus
H
Bus
L
master
Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
Internal data bus
H
Bus
L
master
Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
Internal data bus
H
Bus
L
master
Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
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Bus interface
Bus interface
Bus interface
TCR
TMDR
TCR TMDR
Module
data bus
Module
data bus
Module
data bus