Conflict Between Compare-Matches A And B; Switching Of Internal Clocks And Tcnt Operation; Table 13.6 Timer Output Priorities - Renesas H8S Series Hardware Manual

Section 13 8-Bit Timer (TMR)
13.9.4

Conflict between Compare-Matches A and B

If compare-matches A and B occur at the same time, the operation follows the output status that is
defined for compare-match A or B, according to the priority of the timer output shown in table
13.6.

Table 13.6 Timer Output Priorities

Output Setting
Toggle output
1 output
0 output
No change
13.9.5

Switching of Internal Clocks and TCNT Operation

TCNT may increment erroneously when the internal clock is switched over. Table 13.7 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 13.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge, and TCNT is incremented.
Erroneous incrementation can also happen when switching between internal and external clocks.
Rev. 3.00 Jul. 14, 2005 Page 410 of 986
REJ09B0098-0300
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