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Renesas H8S/2111B Manuals
Manuals and User Guides for Renesas H8S/2111B. We have
1
Renesas H8S/2111B manual available for free PDF download: Hardware Manual
Renesas H8S/2111B Hardware Manual (582 pages)
Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4 MB
Table of Contents
Table of Contents
9
Section 1 Overview
35
Features
35
Internal Block Diagram
36
Figure 1.1 Internal Block Diagram
36
Pin Description
37
Pin Arrangement
37
Figure 1.2 Pin Arrangement
37
Pin Functions in each Operating Mode
38
Table 1.1 Pin Functions in each Operating Mode
38
Pin Functions
43
Table 1.2 Pin Functions
43
Section 2 CPU
47
Features
47
Differences between H8S/2600 CPU and H8S/2000 CPU
48
Differences from H8/300 CPU
49
Differences from H8/300H CPU
49
CPU Operating Modes
50
Normal Mode
50
Figure 2.1 Exception Vector Table (Normal Mode)
51
Figure 2.2 Stack Structure in Normal Mode
51
Advanced Mode
52
Figure 2.3 Exception Vector Table (Advanced Mode)
52
Figure 2.4 Stack Structure in Advanced Mode
53
Address Space
54
Figure 2.5 Memory Map
54
Register Configuration
55
Figure 2.6 CPU Internal Registers
55
Figure 2.7 Usage of General Registers
56
General Registers
56
Extended Control Register (EXR)
57
Figure 2.8 Stack
57
Program Counter (PC)
57
Condition-Code Register (CCR)
58
Initial Register Values
59
Data Formats
60
General Register Data Formats
60
Figure 2.9 General Register Data Formats (1)
60
Figure 2.9 General Register Data Formats (2)
61
Memory Data Formats
62
Figure 2.10 Memory Data Formats
62
Instruction Set
63
Table 2.1 Instruction Classification
63
Table 2.2 Operation Notation
64
Table of Instructions Classified by Function
64
Table 2.3 Data Transfer Instructions
65
Table 2.4 Arithmetic Operations Instructions (1)
66
Table 2.4 Arithmetic Operations Instructions (2)
67
Table 2.5 Logic Operations Instructions
68
Table 2.6 Shift Instructions
68
Table 2.7 Bit Manipulation Instructions (1)
69
Table 2.7 Bit Manipulation Instructions (2)
70
Table 2.8 Branch Instructions
71
Table 2.10 Block Data Transfer Instructions
72
Table 2.9 System Control Instructions
72
Basic Instruction Formats
73
Figure 2.11 Instruction Formats (Examples)
73
Addressing Modes and Effective Address Calculation
74
Register Direct-Rn
74
Register Indirect-@Ern
74
Table 2.11 Addressing Modes
74
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
75
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
75
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
75
Table 2.12 Absolute Address Access Ranges
75
Immediate-#XX:8, #XX:16, or #XX:32
76
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
76
Memory Indirect-@@Aa:8
77
Figure 2.12 Branch Address Specification in Memory Indirect Addressing Mode
77
Effective Address Calculation
78
Table 2.13 Effective Address Calculation (1)
78
Table 2.13 Effective Address Calculation (2)
79
Processing States
80
Figure 2.13 State Transitions
81
Usage Notes
82
Note on TAS Instruction Usage
82
Note on STM/LDM Instruction Usage
82
Note on Bit Manipulation Instructions
82
EEPMOV Instruction
83
Section 3 MCU Operating Modes
85
MCU Operating Mode Selection
85
Table 3.1 MCU Operating Mode Selection
85
Register Descriptions
86
Mode Control Register (MDCR)
86
System Control Register (SYSCR)
87
Serial Timer Control Register (STCR)
89
Operating Mode Descriptions
90
Mode 2
90
Mode 3
90
Address Map
91
Figure 3.1 Address Map for H8S/2111B-B
91
Figure 3.2 Address Map for H8S/2111B-C
92
Section 4 Exception Handling
93
Exception Handling Types and Priority
93
Exception Sources and Exception Vector Table
94
Table 4.2 Exception Handling Vector Table
94
Reset
95
Reset Exception Handling
95
Figure 4.1 Reset Sequence (Mode 3)
95
Interrupts after Reset
96
On-Chip Peripheral Modules after Reset Is Cancelled
96
Interrupt Exception Handling
97
Trap Instruction Exception Handling
97
Table 4.3 Status of CCR after Trap Instruction Exception Handling
97
Stack Status after Exception Handling
98
Figure 4.2 Stack Status after Exception Handling
98
Usage Note
99
Figure 4.3 Operation When SP Value Is Odd
99
Section 5 Interrupt Controller
101
Features
101
Input/Output Pins
102
Figure 5.1 Block Diagram of Interrupt Controller
102
Table 5.1 Pin Configuration
102
Register Descriptions
103
Interrupt Control Registers a to C (ICRA to ICRC)
103
Address Break Control Register (ABRKCR)
104
Table 5.2 Correspondence between Interrupt Source and ICR
104
Break Address Registers a to C (BARA to BARC)
105
IRQ Sense Control Registers (ISCRH, ISCRL)
106
IRQ Enable Register (IER)
107
IRQ Status Register (ISR)
107
Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) Wake-Up Event Interrupt Mask Register (WUEMRB)
107
Figure 5.2 Relationship between Interrupts IRQ7 and IRQ6, Interrupts KIN15 to KIN0, Interrupts WUE7 to WUE0, and Registers KMIMR, KMIMRA, and WUEMRB
109
Interrupt Sources
110
External Interrupts
110
Figure 5.3 Block Diagram of Interrupts IRQ7 to IRQ0
110
Internal Interrupts
111
Interrupt Exception Handling Vector Table
112
Table 5.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities
112
Interrupt Control Modes and Interrupt Operation
114
Interrupt Control Mode 0
114
Table 5.4 Interrupt Control Modes
114
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
115
Interrupt Control Mode 1
116
Section 4 Exception Handling
116
Figure 5.5 State Transition in Interrupt Control Mode 1
116
Figure 5.6 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 1
118
Interrupt Exception Handling Sequence
119
Figure 5.7 Interrupt Exception Handling
119
Interrupt Response Times
120
Table 5.5 Interrupt Response Times
120
Table 5.6 Number of States in Interrupt Handling Routine Execution Status
120
Address Break
121
Features
121
Block Diagram
121
Figure 5.8 Address Break Block Diagram
121
Operation
122
Usage Notes
122
Figure 5.9 Address Break Timing Example
123
Usage Notes
124
Conflict between Interrupt Generation and Disabling
124
Figure 5.10 Conflict between Interrupt Generation and Disabling
124
Instructions that Disable Interrupts
125
Interrupts During Execution of EEPMOV Instruction
125
IRQ Status Register (ISR)
125
Section 6 Bus Controller (BSC)
127
Register Descriptions
127
Bus Control Register (BCR)
127
Wait State Control Register (WSCR)
128
Section 7 I/O Ports
129
Table 7.1 Port Functions
130
Port 1
134
Port 1 Data Direction Register (P1DDR)
134
Port 1 Data Register (P1DR)
134
Port 1 Pull-Up MOS Control Register (P1PCR)
135
Pin Functions
135
Port 1 Input Pull-Up MOS
136
Port 2
136
Port 2 Data Direction Register (P2DDR)
136
Table 7.2 Input Pull-Up MOS States (Port 1)
136
Port 2 Data Register (P2DR))
137
Port 2 Pull-Up MOS Control Register (P2PCR)
137
Pin Functions
137
Port 2 Input Pull-Up MOS
138
Port 3
138
Port 3 Data Direction Register (P3DDR)
138
Table 7.3 Input Pull-Up MOS States (Port 2)
138
Port 3 Data Register (P3DR)
139
Port 3 Pull-Up MOS Control Register (P3PCR)
139
Pin Functions
140
Port 3 Input Pull-Up MOS
140
Table 7.4 Input Pull-Up MOS States (Port 3)
140
Port 4
141
Port 4 Data Direction Register (P4DDR)
141
Port 4 Data Register (P4DR)
141
Pin Functions
142
Port 5
144
Port 5 Data Direction Register (P5DDR)
144
Port 5 Data Register (P5DR)
144
Pin Functions
145
Port 6
146
Port 6 Data Direction Register (P6DDR)
146
Port 6 Data Register (P6DR)
147
Port 6 Pull-Up MOS Control Register (KMPCR)
147
System Control Register 2 (SYSCR2)
148
Pin Functions
148
Port 6 Input Pull-Up MOS
150
Table 7.5 Input Pull-Up MOS States (Port 6)
150
Port 7
151
Port 7 Input Data Register (P7PIN)
151
Pin Functions
151
Port 8
152
Port 8 Data Direction Register (P8DDR)
152
Port 8 Data Register (P8DR)
152
Pin Functions
153
Port 9
156
Port 9 Data Direction Register (P9DDR)
156
Port 9 Data Register (P9DR)
156
Pin Functions
157
Port a
159
Port a Data Direction Register (PADDR)
159
Port a Output Data Register (PAODR)
159
Port a Input Data Register (PAPIN)
160
Pin Functions
160
Port a Input Pull-Up MOS
162
Table 7.6 Input Pull-Up MOS States (Port A)
162
Port B
163
Port B Data Direction Register (PBDDR)
163
Port B Output Data Register (PBODR)
163
Port B Input Data Register (PBPIN)
164
Pin Functions
164
Port B Input Pull-Up MOS
165
Table 7.7 Input Pull-Up MOS States (Port B)
165
Ports C, D
166
Port C and Port D Data Direction Registers (PCDDR, PDDDR)
166
Port C and Port D Output Data Registers (PCODR, PDODR)
167
Port C and Port D Input Data Registers (PCPIN, PDPIN)
167
Port C and Port D Nch-OD Control Register (PCNOCR, PDNOCR)
168
Pin Functions
169
Input Pull-Up MOS in Ports C and D
169
Table 7.8 Input Pull-Up MOS States (Port C and Port D)
169
Ports E, F
170
Port E and Port F Data Direction Registers (PEDDR, PFDDR)
170
Port E and Port F Output Data Registers (PEODR, PFODR)
171
Port E and Port F Input Data Registers (PEPIN, PFPIN)
172
Pin Functions
172
Port E and Port F Nch-OD Control Register (PENOCR, PFNOCR)
174
Pin Functions
175
Input Pull-Up MOS in Ports E and F
175
Table 7.9 Input Pull-Up MOS States (Port E and Port F)
175
Port G
176
Port G Data Direction Register
176
Port G Output Data Register
177
Port G Input Data Register
177
Pin Functions
178
Port G Nch-OD Control Register
179
Pin Functions
179
Section 8 8-Bit PWM Timer (PWM)
181
Features
181
Figure 8.1 Block Diagram of PWM Timer
181
Input/Output Pins
182
Register Descriptions
182
PWM Register Select (PWSL)
183
Table 8.2 Internal Clock Selection
184
Table 8.3 Resolution, PWM Conversion Period, and Carrier Frequency When Φ = 10 Mhz
184
PWM Data Registers 7 to 0 (PWDR7 to PWD0)
185
PWM Data Polarity Register a (PWDPRA)
185
PWM Output Enable Register a (PWOERA)
186
Peripheral Clock Select Register (PCSR)
186
Operation
187
Table 8.4 Duty Cycle of Basic Pulse
187
Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000)
188
Table 8.5 Position of Pulses Added to Basic Pulses
188
Diagram of PWM Used as D/A Converter
189
Figure 8.3 Example of PWM Setting
189
Figure 8.4 Example When PWM Is Used as D/A Converter
189
PWM Setting Example
189
Usage Notes
190
Module Stop Mode Setting
190
Section 9 16-Bit Free-Running Timer (FRT)
191
Features
191
Figure 9.1 Block Diagram of 16-Bit Free-Running Timer
192
Input/Output Pins
193
Register Descriptions
193
Table 9.1 Pin Configuration
193
Free-Running Counter (FRC)
194
Input Capture Registers a to D (ICRA to ICRD)
194
Output Compare Registers a and B (OCRA, OCRB)
194
Output Compare Register DM (OCRDM)
195
Output Compare Registers AR and AF (OCRAR, OCRAF)
195
Timer Interrupt Enable Register (TIER)
196
Timer Control/Status Register (TCSR)
197
Timer Control Register (TCR)
200
Timer Output Compare Control Register (TOCR)
201
Operation
203
Pulse Output
203
Figure 9.2 Example of Pulse Output
203
Operation Timing
204
FRC Increment Timing
204
Figure 9.3 Increment Timing with Internal Clock Source
204
Figure 9.4 Increment Timing with External Clock Source
204
Output Compare Output Timing
205
FRC Clear Timing
205
Figure 9.5 Timing of Output Compare a Output
205
Figure 9.6 Clearing of FRC by Compare-Match a Signal
205
Input Capture Input Timing
206
Figure 9.7 Input Capture Input Signal Timing (Usual Case)
206
Figure 9.8 Input Capture Input Signal Timing (When ICRA to ICRD Are Read)
206
Buffered Input Capture Input Timing
207
Figure 9.9 Buffered Input Capture Timing
207
Figure 9.10 Buffered Input Capture Timing (BUFEA = 1)
207
Timing of Input Capture Flag (ICF) Setting
208
Timing of Output Compare Flag (OCF) Setting
208
Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting
208
Figure 9.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
208
Timing of FRC Overflow Flag Setting
209
Automatic Addition Timing
209
Figure 9.13 Timing of Overflow Flag (OVF) Setting
209
Figure 9.14 OCRA Automatic Addition Timing
209
Mask Signal Generation Timing
210
Figure 9.15 Timing of Input Capture Mask Signal Setting
210
Figure 9.16 Timing of Input Capture Mask Signal Clearing
210
Interrupt Sources
211
Usage Notes
211
Conflict between FRC Write and Clear
211
Figure 9.17 FRC Write-Clear Conflict
211
Table 9.2 FRT Interrupt Sources
211
Conflict between FRC Write and Increment
212
Conflict between OCR Write and Compare-Match
212
Figure 9.18 FRC Write-Increment Conflict
212
Figure 9.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used)
213
Figure 9.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used)
213
Switching of Internal Clock and FRC Operation
214
Table 9.3 Switching of Internal Clock and FRC Operation
214
Module Stop Mode Setting
215
Section 10 8-Bit Timer (TMR)
217
Features
217
Table 10.1 TMR Function
218
Figure 10.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X)
220
Figure 10.3 Block Diagram of 8-Bit Timer (TMR_B and TMR_A)
221
Input/Output Pins
222
Table 10.2 Pin Configuration
222
Register Descriptions
223
Timer Counter (TCNT)
225
Time Constant Register a (TCORA)
225
Time Constant Register B (TCORB)
225
Timer Control Register (TCR)
226
Table 10.3 Clock Input to TCNT and Count Condition (1)
227
Table 10.3 Clock Input to TCNT and Count Condition (2)
228
Table 10.3 Clock Input to TCNT and Count Condition (3)
229
Timer Control/Status Register (TCSR)
230
Time Constant Register (TCORC)
236
Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A)
236
Timer Input Select Register (TISR and TISR_B)
236
Timer Connection Register I (TCONRI)
237
Timer Connection Register S (TCONRS)
237
Timer XY Control Register (TCRXY)
238
Table 10.4 Registers Accessible by TMR_X/TMR_Y
238
Timer AB Control Register (TCRAB)
239
Operation
240
Pulse Output
240
Figure 10.4 Pulse Output Example
240
Operation Timing
241
TCNT Count Timing
241
Timing of CMFA and CMFB Setting at Compare-Match
241
Figure 10.5 Count Timing for Internal Clock Input
241
Figure 10.6 Count Timing for External Clock Input (both Edges)
241
Timing of Timer Output at Compare-Match
242
Timing of Counter Clear at Compare-Match
242
Figure 10.7 Timing of CMF Setting at Compare-Match
242
Figure 10.8 Timing of Toggled Timer Output by Compare-Match a Signal
242
Figure 10.9 Timing of Counter Clear by Compare-Match
242
TCNT External Reset Timing
243
Timing of Overflow Flag (OVF) Setting
243
Figure 10.10 Timing of Counter Clear by External Reset Input
243
Figure 10.11 Timing of OVF Flag Setting
243
TMR_0 and TMR_1 Cascaded Connection
244
16-Bit Count Mode
244
Compare-Match Count Mode
244
TMR_Y and TMR_X Cascaded Connection
245
16-Bit Count Mode
245
Compare-Match Count Mode
245
Input Capture Operation
246
TMR_B and TMR_A Cascaded Connection
246
16-Bit Count Mode
246
Compare-Match Count Mode
246
Input Capture Operation
247
Figure 10.12 Timing of Input Capture Operation
247
Figure 10.13 Timing of Input Capture Signal (Input Capture Signal Is Input During TICRR and TICRF Read)
247
Table 10.5 Input Capture Signal Selection
248
Table 10.6 Input Capture Signal Selection
248
Interrupt Sources
249
Usage Notes
250
10.10.1 Conflict between TCNT Write and Counter Clear
250
10.10.2 Conflict between TCNT Write and Count-Up
250
Figure 10.14 Conflict between TCNT Write and Clear
250
Figure 10.15 Conflict between TCNT Write and Count-Up
250
10.10.3 Conflict between TCOR Write and Compare-Match
251
10.10.4 Conflict between Compare-Matches a and B
251
Figure 10.16 Conflict between TCOR Write and Compare-Match
251
Table 10.8 Timer Output Priorities
251
10.10.5 Switching of Internal Clocks and TCNT Operation
252
Table 10.9 Switching of Internal Clocks and TCNT Operation
252
10.10.6 Mode Setting with Cascaded Connection
253
10.10.7 Module Stop Mode Setting
253
Section 11 Watchdog Timer (WDT)
255
Features
255
Figure 11.1 Block Diagram of WDT
256
Input/Output Pins
257
Register Descriptions
257
Timer Counter (TCNT)
257
Table 11.1 Pin Configuration
257
Timer Control/Status Register (TCSR)
258
Operation
261
Watchdog Timer Mode
261
Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation
262
Interval Timer Mode
263
Figure 11.3 Interval Timer Mode Operation
263
Figure 11.4 OVF Flag Set Timing
263
RESO Signal Output Timing
264
Interrupt Sources
264
Figure 11.5 Output Timing of RESO Signal
264
Table 11.2 WDT Interrupt Source
264
Usage Notes
265
Notes on Register Access
265
Figure 11.6 Writing to TCNT and TCSR (WDT_0)
265
Conflict between Timer Counter (TCNT) Write and Increment
266
Changing Values of CKS2 to CKS0 Bits
266
Switching between Watchdog Timer Mode and Interval Timer Mode
266
Figure 11.7 Conflict between TCNT Write and Increment
266
System Reset by RESO Signal
267
Counter Values During Transitions between High-Speed, Sub-Active, and Watch Modes
267
Figure 11.8 Sample Circuit for Resetting System by RESO Signal
267
Section 12 Serial Communication Interface (SCI)
269
Features
269
Input/Output Pins
270
Figure 12.1 Block Diagram of SCI
270
Table 12.1 Pin Configuration
270
Register Descriptions
271
Receive Shift Register (RSR)
271
Receive Data Register (RDR)
271
Transmit Data Register (TDR)
271
Transmit Shift Register (TSR)
272
Serial Mode Register (SMR)
272
Serial Control Register (SCR)
273
Serial Status Register (SSR)
275
Serial Interface Mode Register (SCMR)
277
Bit Rate Register (BRR)
278
Table 12.2 Relationships between N Setting in BRR and Bit Rate B
278
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
279
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
280
Table 12.4 Maximum Bit Rate for each Frequency (Asynchronous Mode)
281
Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
281
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
282
Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
282
Serial Pin Select Register (SPSR)
283
Operation in Asynchronous Mode
283
Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
283
Data Transfer Format
284
Table 12.8 Serial Transfer Formats (Asynchronous Mode)
284
Clock
285
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode
285
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
285
Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode)
286
Figure 12.5 Sample SCI Initialization Flowchart
287
SCI Initialization (Asynchronous Mode)
287
Data Transmission (Asynchronous Mode)
288
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
288
Figure 12.7 Sample Serial Transmission Flowchart
289
Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
290
Serial Data Reception (Asynchronous Mode)
290
Figure 12.9 Sample Serial Reception Flowchart (1)
291
Table 12.9 SSR Status Flags and Receive Data Handling
291
Figure 12.9 Sample Serial Reception Flowchart (2)
292
Multiprocessor Communication Function
293
Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
293
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart
294
Multiprocessor Serial Data Transmission
294
Figure 12.12 Example of SCI Receive Operation (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
295
Multiprocessor Serial Data Reception
295
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)
296
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)
297
Operation in Clocked Synchronous Mode
298
Clock
298
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)
298
SCI Initialization (Clocked Synchronous Mode)
299
Figure 12.15 Sample SCI Initialization Flowchart
299
Serial Data Transmission (Clocked Synchronous Mode)
300
Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode
300
Figure 12.17 Sample Serial Transmission Flowchart
301
Serial Data Reception (Clocked Synchronous Mode)
302
Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode
302
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
303
Figure 12.19 Sample Serial Reception Flowchart
303
Figure 12.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
304
Interrupt Sources
305
Table 12.10 SCI Interrupt Sources
305
Usage Notes
306
Module Stop Mode Setting
306
Break Detection and Processing
306
Mark State and Break Detection
306
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
306
Relation between Writing to TDR and TDRE Flag
306
SCI Operations During Mode Transitions
307
Figure 12.21 Sample Flowchart for Mode Transition During Transmission
308
Figure 12.22 Pin States During Transmission in Asynchronous Mode (Internal Clock)
308
Internal Clock
309
Figure 12.23 Pin States During Transmission in Clocked Synchronous Mode
309
Figure 12.24 Sample Flowchart for Mode Transition During Reception
309
Switching from SCK Pins to Port Pins
310
Figure 12.25 Switching from SCK Pins to Port Pins
310
Figure 12.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
310
Section 13 I C Bus Interface (IIC)
311
Features
311
Figure 13.1 Block Diagram of I
312
Figure 13.2 I C Bus Interface Connections (Example: this LSI as Master)
313
Input/Output Pins
314
Table 13.1 Pin Configuration
314
Register Descriptions
315
I 2 C Bus Data Register (ICDR)
315
C Bus Data Register (ICDR)
316
Slave Address Register (SAR)
317
Second Slave Address Register (SARX)
318
Table 13.2 Communication Format
319
C Bus Mode Register (ICMR)
320
Table 13.3 I 2 C Transfer Rate
322
C Bus Control Register (ICCR)
323
Table 13.4 Flags and Transfer States (Master Mode)
328
Table 13.5 Flags and Transfer States (Slave Mode)
329
Table 13.5 Flags and Transfer States (Slave Mode) (Cont)
330
C Bus Status Register (ICSR)
331
DDC Switch Register (DDCSWR)
335
C Bus Extended Control Register (ICXR)
336
Port G Control Register
340
Operation
341
C Bus Data Format
341
Figure 13.3 I 2 C Bus Data Format (I 2 C Bus Format)
341
Figure 13.4 I 2 C Bus Data Format (Serial Format)
341
Figure 13.5 I C Bus Timing
342
Table 13.6 I 2 C Bus Data Format Symbols
342
Initialization
343
Master Transmit Operation
343
Figure 13.6 Sample Flowchart for IIC Initialization
343
Figure 13.7 Sample Flowchart for Operations in Master Transmit Mode
344
Figure 13.8 Example of Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
346
Figure 13.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0)
347
Master Receive Operation
348
Figure 13.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1)
348
Figure 13.11 Example of Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
350
Figure 13.12 Example of Stop Condition Issuance Operation Timing in Master Receive Mode (MLS = WAIT = 0, HNDS = 1)
350
Figure 13.13 Sample Flowchart for Operations in Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
351
Figure 13.14 Sample Flowchart for Operations in Master Receive Mode (Receiving a Single Byte) (WAIT = 1)
352
Figure 13.15 Example of Master Receive Mode Operation Timing (MLS = ACKB = 0, WAIT = 1)
354
Slave Receive Operation
355
Figure 13.16 Example of Stop Condition Issuance Timing in Master Receive Mode (MLS = ACKB = 0, WAIT = 1)
355
Figure 13.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)
356
Figure 13.18 Example of Slave Receive Mode Operation Timing (1) (MLS = 0, HNDS= 1)
358
Figure 13.19 Example of Slave Receive Mode Operation Timing (2) (MLS = 0, HNDS= 1)
358
Figure 13.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0)
359
Figure 13.21 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0, HNDS = 0)
361
Figure 13.22 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0, HNDS = 0)
361
Slave Transmit Operation
362
Figure 13.23 Sample Flowchart for Slave Transmit Mode
362
Figure 13.24 Example of Slave Transmit Mode Operation Timing (MLS = 0)
364
IRIC Setting Timing and SCL Control
365
Figure 13.25 IRIC Setting Timing and SCL Control (1)
365
Figure 13.26 IRIC Setting Timing and SCL Control (2)
366
Figure 13.27 IRIC Setting Timing and SCL Control (3)
367
Noise Canceller
368
Figure 13.28 Block Diagram of Noise Canceler
368
Initialization of Internal State
369
Interrupt Sources
370
Table 13.7 IIC Interrupt Sources
370
Usage Notes
371
Table 13.8 I 2 C Bus Timing (SCL and SDA Outputs)
371
Table 13.9 Permissible SCL Rise Time
372
Figure 13.29 Notes on Reading Master Receive Data
374
Figure 13.30 Flowchart for Start Condition Issuance Instruction for Retransmission
375
Figure 13.31 Stop Condition Issuance Timing
376
Figure 13.32 IRIC Flag Clearing Timing When WAIT = 1
377
Figure 13.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode
378
Figure 13.34 TRS Bit Set Timing in Slave Mode
379
Figure 13.35 Diagram of Erroneous Operation When Arbitration Is Lost
381
Module Stop Mode Setting
381
Section 14 Keyboard Buffer Controller
383
Features
383
Figure 14.1 Block Diagram of Keyboard Buffer Controller
383
Input/Output Pins
384
Figure 14.2 Keyboard Buffer Controller Connection
384
Table 14.1 Pin Configuration
384
Register Descriptions
385
Keyboard Control Register H (KBCRH)
385
Keyboard Control Register L (KBCRL)
387
Keyboard Data Buffer Register (KBBR)
388
Operation
389
Receive Operation
389
Figure 14.3 Sample Receive Processing Flowchart
389
Transmit Operation
390
Figure 14.4 Receive Timing
390
Figure 14.5 Sample Transmit Processing Flowchart (1)
391
Figure 14.5 Sample Transmit Processing Flowchart (2)
392
Figure 14.6 Transmit Timing
392
Receive Abort
393
Figure 14.7 Sample Receive Abort Processing Flowchart (1)
393
Figure 14.7 Sample Receive Abort Processing Flowchart (2)
394
Figure 14.8 Receive Abort and Transmit Start (Transmission/Reception Switchover) Timing
394
KCLKI and KDI Read Timing
395
KCLKO and KDO Write Timing
395
Figure 14.9 KCLKI and KDI Read Timing
395
Figure 14.10 KCLKO and KDO Write Timing
395
KBF Setting Timing and KCLK Control
396
Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing
396
Receive Timing
397
Figure 14.12 Receive Counter and KBBR Data Load Timing
397
KCLK Fall Interrupt Operation
398
Figure 14.13 Example of KCLK Input Fall Interrupt Operation
398
Usage Notes
399
KBIOE Setting and KCLK Falling Edge Detection
399
Figure 14.14 KBIOE Setting and KCLK Falling Edge Detection Timing
399
Module Stop Mode Setting
400
Section 15 Host Interface (Lpc)
401
Figure 15.1 Block Diagram of LPC
402
Section 15 Host Interface (LPC)
403
Features
403
Table 15.1 Pin Configuration
403
Input/Output Pins
405
Register Descriptions
406
Host Interface Control Registers 0 and 1 (HICR0, HICR1)
407
Host Interface Control Registers 2 and 3 (HICR2, HICR3)
413
Table 15.2 Register Selection
414
LPC Channel 3 Address Register (LADR3)
415
Input Data Registers 1 to 3 (IDR1 to IDR3)
416
Output Data Registers 1 to 3 (ODR1 to ODR3)
417
Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)
417
Status Registers 1 to 3 (STR1 to STR3)
417
SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)
423
Host Interface Select Register (HISEL)
431
Operation
432
Host Interface Activation
432
Figure 15.2 Typical LFRAME Timing
432
Figure 15.3 Abort Mechanism
432
LPC I/O Cycles
433
Figure 15.4 GA20 Output
433
Table 15.3 GA20 (P81) Set/Clear Timing
433
A20 Gate
434
Table 15.4 Fast A20 Gate Output Signals
434
Table 15.5 Scope of Host Interface Pin Shutdown
436
Host Interface Shutdown Function (LPCPD)
437
Table 15.6 Scope of Initialization in each Host Interface Mode
437
Figure 15.5 Power-Down State Termination Timing
438
Figure 15.6 SERIRQ Timing
439
Host Interface Serialized Interrupt Operation (SERIRQ)
441
Figure 15.7 Clock Start Request Timing
441
Table 15.7 Receive Complete Interrupts and Error Interrupt
442
Host Interface Clock Start Request (CLKRUN)
443
Table 15.8 HIRQ Setting and Clearing Conditions
443
Interrupt Sources
444
IBFI1, IBFI2, IBFI3, and ERRI
444
SMI, HIRQ1, HIRQ6, HIRQ9, HIRQ10, HIRQ11, and HIRQ12
444
Figure 15.8 HIRQ Flowchart (Example of Channel 1)
444
Usage Notes
447
Module Stop Mode Setting
447
Notes on Using Host Interface
447
Section 16 A/D Converter
447
Features
447
Figure 16.1 Block Diagram of A/D Converter
448
Input/Output Pins
449
Table 16.1 Pin Configuration
449
Register Descriptions
450
A/D Data Registers a to D (ADDRA to ADDRD)
450
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
450
A/D Control/Status Register (ADCSR)
451
A/D Control Register (ADCR)
452
Operation
453
Single Mode
453
Scan Mode
453
Figure 16.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)
454
Input Sampling and A/D Conversion Time
455
Figure 16.3 A/D Conversion Timing
455
External Trigger Input Timing
456
Figure 16.4 External Trigger Input Timing
456
Table 16.3 A/D Conversion Time (Single Mode)
456
Interrupt Sources
457
A/D Conversion Accuracy Definitions
457
Figure 16.5 A/D Conversion Accuracy Definitions
458
Figure 16.6 A/D Conversion Accuracy Definitions
458
Usage Notes
459
Permissible Signal Source Impedance
459
Influences on Absolute Accuracy
459
Figure 16.7 Example of Analog Input Circuit
459
Setting Range of Analog Power Supply and Other Pins
460
Notes on Board Design
460
Notes on Noise Countermeasures
460
Module Stop Mode Setting
461
Figure 16.8 Example of Analog Input Protection Circuit
461
Figure 16.9 Equivalent Circuit of Analog Input Pin
461
Section 17 RAM
463
Section 18 ROM
465
Features
465
Figure 18.1 Block Diagram of Flash Memory
466
Mode Transitions
467
Figure 18.2 Flash Memory State Transitions
467
Table 18.1 Differences between Boot Mode and User Program Mode
467
Figure 18.3 Boot Mode
468
Figure 18.4 User Program Mode (Example)
469
Block Configuration
470
Figure 18.5 Flash Memory Block Configuration
470
Input/Output Pins
471
Register Descriptions
471
Table 18.2 Pin Configuration
471
Flash Memory Control Register 1 (FLMCR1)
472
Flash Memory Control Register 2 (FLMCR2)
473
Erase Block Registers 1 and 2 (EBR1, EBR2)
474
Operating Modes
475
On-Board Programming Modes
475
Table 18.3 Operating Modes and ROM
475
Table 18.4 On-Board Programming Mode Settings
475
Boot Mode
476
Table 18.5 Boot Mode Operation
477
Figure 18.6 On-Chip RAM Area in Boot Mode
478
Figure 18.7 ID Code Area
478
Table 18.6 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is Possible
478
Figure 18.8 Programming/Erasing Flowchart Example in User Program Mode
479
User Program Mode
479
Flash Memory Programming/Erasing
480
Program/Program-Verify
480
Figure 18.9 Program/Program-Verify Flowchart
481
Erase/Erase-Verify
482
Figure 18.10 Erase/Erase-Verify Flowchart
483
Program/Erase Protection
484
Hardware Protection
484
Software Protection
484
Error Protection
484
Interrupts During Flash Memory Programming/Erasing
485
Programmer Mode
486
Figure 18.11 Memory Map in Programmer Mode
486
Usage Notes
487
Section 19 Clock Pulse Generator
489
Figure 19.1 Block Diagram of Clock Pulse Generator
489
Oscillator
490
Connecting Crystal Resonator
490
Figure 19.2 Typical Connection to Crystal Resonator
490
Figure 19.3 Equivalent Circuit of Crystal Resonator
490
Table 19.1 Damping Resistance Values
490
Table 19.2 Crystal Resonator Parameters
490
External Clock Input Method
491
Figure 19.4 Example of External Clock Input
491
Figure 19.5 External Clock Input Timing
492
Table 19.3 External Clock Input Conditions
492
Table 19.4 External Clock Output Stabilization Delay Time
492
Duty Correction Circuit
493
Medium-Speed Clock Divider
493
Bus Master Clock Select Circuit
493
Figure 19.6 Timing of External Clock Output Stabilization Delay Time
493
Subclock Input Circuit
494
Waveform Forming Circuit
494
Figure 19.7 Subclock Input Timing
494
Table 19.5 Subclock Input Conditions
494
Clock Select Circuit
495
Usage Notes
495
Note on Resonator
495
Notes on Board Design
495
Figure 19.8 Note on Board Design of Oscillator Circuit Section
495
Section 20 Power-Down Modes
497
Register Descriptions
497
Standby Control Register (SBYCR)
498
Low-Power Control Register (LPWRCR)
499
Table 20.1 Operating Frequency and Wait Time
499
Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
501
Mode Transitions and LSI States
502
Figure 20.1 Mode Transition Diagram
502
Table 20.2 LSI Internal States in each Operating Mode
503
Medium-Speed Mode
504
Figure 20.2 Medium-Speed Mode Timing
504
Sleep Mode
505
Software Standby Mode
505
Figure 20.3 Application Example in Software Standby Mode
506
Hardware Standby Mode
507
Figure 20.4 Hardware Standby Mode Timing
507
Watch Mode
508
Subsleep Mode
509
Subactive Mode
510
Module Stop Mode
511
Direct Transitions
511
Usage Notes
512
20.12.1 I/O Port Status
512
20.12.2 Current Consumption When Waiting for Oscillation Stabilization
512
Section 21 List of Registers
513
Register Addresses (Address Order)
514
Register Bits
523
Register States in each Operating Mode
531
Register Select Conditions
539
Section 22 Electrical Characteristics
547
Absolute Maximum Ratings
547
Table 22.1 Absolute Maximum Ratings
547
DC Characteristics
548
Table 22.2 DC Characteristics (1)
548
Table 22.2 DC Characteristics (2)
550
Table 22.2 DC Characteristics (3) When LPC Function Is Used
551
Figure 22.1 Darlington Pair Drive Circuit (Example)
552
Table 22.3 Permissible Output Currents
552
Figure 22.2 LED Drive Circuit (Example)
553
Table 22.4 Bus Drive Characteristics
553
AC Characteristics
554
Figure 22.3 Output Load Circuit
554
Clock Timing
555
Table 22.5 Clock Timing
555
Control Signal Timing
556
Table 22.6 Control Signal Timing
556
Table 22.7 Timing of On-Chip Peripheral Modules (1)
557
Timing of On-Chip Peripheral Modules
557
Table 22.8 Keyboard Buffer Controller Timing
558
Table 22.9 I 2 C Bus Timing
559
A/D Conversion Characteristics
560
Table 22.10 LPC Module Timing
560
Table 22.11 A/D Conversion Characteristics (AN5 to AN0 Input: 134/266-State Conversion)
560
Flash Memory Characteristics
561
Table 22.12 Flash Memory Characteristics
561
Usage Note
563
Timing Chart
563
Clock Timing
563
Figure 22.4 Connection of VCL Capacitor
563
Figure 22.5 System Clock Timing
563
Figure 22.6 Oscillation Settling Timing
564
Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)
564
Control Signal Timing
565
Figure 22.8 Reset Input Timing
565
Figure 22.9 Interrupt Input Timing
565
On-Chip Peripheral Module Timing
566
Figure 22.10 I/O Port Input/Output Timing
566
Figure 22.11 FRT Input/Output Timing
566
Figure 22.12 FRT Clock Input Timing
566
Figure 22.13 8-Bit Timer Output Timing
567
Figure 22.14 8-Bit Timer Clock Input Timing
567
Figure 22.15 8-Bit Timer Reset Input Timing
567
Figure 22.16 PWM, PWMX Output Timing
567
Figure 22.17 SCK Clock Input Timing
568
Figure 22.18 SCI Input/Output Timing (Synchronous Mode)
568
Figure 22.19 A/D Converter External Trigger Input Timing
568
Figure 22.20 WDT Output Timing (RESO)
568
Figure 22.21 Keyboard Buffer Controller Timing
569
Figure 22.22 I C Bus Interface Input/Output Timing
569
Figure 22.23 Host Interface (LPC) Timing
570
Figure 22.24 Tester Measurement Condition
570
Appendix
571
I/O Port States in each Processing State
571
Table A.1 I/O Port States in each Processing State
571
Product Codes
572
Package Dimensions
573
Figure C.1 Package Dimensions (TFP-144)
573
Index
575
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