Section 18 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave Host Description
5
IRQ11E4 0
4
IRQ10E4 0
Rev. 3.00 Jul. 14, 2005 Page 650 of 986
REJ09B0098-0300
R/W
R/W
Host IRQ11 Interrupt Enable 4
Enables or disables an HIRQ11 interrupt request
when OBF4 is set by an ODR4 write.
0: HIRQ11 interrupt request by OBF4 and
IRQE11E4 is disabled
[Clearing conditions]
•
Writing 0 to IRQ11E4
•
LPC hardware reset, LPC software reset
•
Clearing OBF4 to 0 (when IEDIR4 = 0)
1: [When IEDIR4 = 0]
HIRQ11 interrupt request by setting OBF4 to 1 is
enabled
[When IEDIR4 = 1]
HIRQ11 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ11E4 = 0
R/W
Host IRQ10 Interrupt Enable 4
Enables or disables an HIRQ10 interrupt request
when OBF4 is set by an ODR4 write.
0: HIRQ10 interrupt request by OBF4 and
IRQE10E4 is disabled
[Clearing conditions]
•
Writing 0 to IRQ10E4
•
LPC hardware reset, LPC software reset
•
Clearing OBF4 to 0 (when IEDIR4 = 0)
1: [When IEDIR4 = 0]
HIRQ10 interrupt request by setting OBF4 to 1 is
enabled
[When IEDIR4 = 1]
HIRQ10 interrupt is requested
[Setting condition]
•
Writing 1 after reading IRQ10E4 = 0