Renesas H8S Series Hardware Manual page 687

Bit Bit Name Initial Value Slave Host Description
0 OBF3 0
Note: * Only 0 can be written to clear the flag.
• STR4
Bit Bit Name Initial Value Slave Host Description
7 DBU47 0
6 DBU46 0
5 DBU45 0
4 DBU44 0
3 C/D4 0
2 DBU42 0
1 IBF4 0
R/W
R/(W)* R Output Buffer Full
0: [Clearing conditions]
•
When the host reads ODR3 in I/O read cycle
•
When the slave writes 0 to the OBF3 bit
1: [Setting condition]
•
When the slave writes to ODR3
R/W
R/W R Defined by User
R/W R The user can use these bits as necessary.
R/W R
R/W R
R R Command/Data Flag
When the host writes to IDR4, bit 2 of the I/O address
is written into this bit to indicate whether IDR4
contains data or a command.
0: Content of input data register (IDR4) is a data
1: Content of input data register (IDR4) is a
command
R/W R Defined by User
The user can use this bit as necessary.
R R Input Buffer Full
This bit is an internal interrupt source to the slave
(this LSI).
0: [Clearing condition]
When the slave reads IDR4
1: [Setting condition]
When the host writes to IDR4 in I/O write cycle
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 639 of 986
REJ09B0098-0300