C Bus Control Register (Iccr) - Renesas H8S Series Hardware Manual

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16.3.5 I

C Bus Control Register (ICCR)

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ICCR controls the I C bus interface and performs interrupt flag confirmation.
Bit Bit Name Initial Value R/W
7 ICE 0
6 IEIC 0
5 MST 0
4 TRS 0
Description
2
R/W I C Bus Interface Enable
2
0: I C bus interface modules are stopped and I
interface module internal state is initialized. SAR and
SARX can be accessed.
2
1: I C bus interface modules can perform transfer
operation, and the ports function as the SCL and SDA
input/output pins. ICMR and ICDR can be accessed.
2
R/W I C Bus Interface Interrupt Enable
0: Disables interrupts from the I
1: Enables interrupts from the I
R/W Master/Slave Select
R/W Transmit/Receive Select
MST TRS
0 0: Slave receive mode
0 1: Slave transmit mode
1 0: Master receive mode
1 1: Master transmit mode
Both these bits will be cleared by hardware when they lose
in a bus contention in master mode with the I
In slave receive mode with I
the first frame immediately after the start condition sets
these bits in receive mode or transmit mode automatically
by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.
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Section 16 I C Bus Interface (IIC)
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C bus interface to the CPU
2
C bus interface to the CPU.
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C bus format, the R/W bit in
Rev. 3.00 Jul. 14, 2005 Page 517 of 986
REJ09B0098-0300
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C bus
2
C bus format.