Medium-Speed Mode - Renesas H8S Series Hardware Manual

Section 24 Power-Down Modes
24.3

Medium-Speed Mode

The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends
according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the
operating clock can be selected from φ/2, φ/4, φ/8, φ/16, or φ/32. On-chip peripheral modules
other than the bus masters and KBU operate on the system clock (φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in four states, and internal I/O registers in eight states.
By clearing all of bits SCK2 to SCK0 to 0 in medium-speed mode, a transition is made to high-
speed mode at the end of the current bus cycle.
When the SLEEP instruction is executed with the SSBY bit in SBYCR cleared to 0 and the LSON
bit in LPWRCR cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by
an interrupt, medium-speed mode is restored. When the SLEEP instruction is executed with the
SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in TCSR
(WDT_1) cleared to 0, a transition is made to software standby mode. When software standby
mode is cleared by an external interrupt, medium-speed mode is restored.
When the RES pin is driven low, medium-speed mode is cancelled and a transition is made to the
reset state. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev. 3.00 Jul. 14, 2005 Page 870 of 986
REJ09B0098-0300