Noise Canceller; Figure 16.28 Block Diagram Of Noise Canceller - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

Hide thumbs Also See for H8S Series:

Table of Contents

Noise Canceller

The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched

internally. Figure 16.28 shows a block diagram of the noise canceller.

The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin

input signal is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

Sampling clock

System clock

Rev. 3.00 Jul. 14, 2005 Page 567 of 986

Section 16 I

C Bus Interface (IIC)

REJ09B0098-0300

H8s/2100 series H8s/2114r R4f2114r