Buffer Operation; Figure 12.16 Compare Match Buffer Operation; Figure 12.17 Input Capture Buffer Operation; Table 12.17 Register Combinations In Buffer Operation - Renesas H8S Series Hardware Manual

12.5.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers. Buffer operation differs depending on whether TGR has been designated as an input
capture register or as a compare match register. Table 12.17 shows the register combinations used
in buffer operation.

Table 12.17 Register Combinations in Buffer Operation

Channel
0
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. This operation is illustrated in figure 12.16.
Buffer register
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register. This operation is
illustrated in figure 12.17.
Input capture
signal
Buffer register
Timer General Register
TGRA_0
TGRB_0
Compare match signal
Timer general
register

Figure 12.16 Compare Match Buffer Operation

Timer general

Figure 12.17 Input Capture Buffer Operation

Section 12 16-Bit Timer Pulse Unit (TPU)
Buffer Register
TGRC_0
TGRD_0
Comparator
register
Rev. 3.00 Jul. 14, 2005 Page 343 of 986
TCNT
TCNT
REJ09B0098-0300