Renesas H8S Series Hardware Manual page 433

Bit Bit Name Initial Value R/W Description
4 CCLR1 0
3 CCLR0 0
2 CKS2 0
1 CKS1 0
0 CKS0 0
R/W Counter Clear 1, 0
R/W These bits select the method by which the timer counter is
cleared.
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
R/W Clock Select 2 to 0
R/W These bits select the clock input to TCNT and count
condition, together with the ICKS1 and ICKS0 bits in
R/W
STCR. For details, see table 13.2.
Section 13 8-Bit Timer (TMR)
Rev. 3.00 Jul. 14, 2005 Page 385 of 986
REJ09B0098-0300