Section 7 Data Transfer Controller (Dtc) - Renesas H8S Series Hardware Manual

Section 7 Data Transfer Controller (DTC)

Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-
chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus
connects the DTC to addresses H'(FF)EC00 to H'(FF)EFFF in on-chip RAM (1 kbyte), enabling
32-bit/1-state reading and writing of the DTC register information.
Rev. 3.00 Jul. 14, 2005 Page 135 of 986
DTCH80CA_000020020300
REJ09B0098-0300