Section 18 Lpc Interface (Lpc); Features - Renesas H8S Series Hardware Manual

This LSI has an on-chip LPC interface.
The LPC includes four register sets, each of which comprises data and status registers, control
register, the fast Gate A20 logic circuit, and the host interrupt request circuit.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC
module supports I/O read, I/O write, LPC memory read, LPC memory write, firmware (FW)
memory read, and firmware (FW) memory write cycle transfers. It is also provided with
power-down functions that can control the PCI clock and shut down the LPC interface.
18.1

Features

• Supports LPC interface I/O read and I/O write cycles
 Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
 Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
• Four register sets comprising data and status registers
 The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
 Fixed I/O addresses of H'60/H'64 are set for channel 1. A fast Gate A20 function is also
provided.
 Fixed I/O addresses of H'62/H'66 are set for channel 2.
 I/O addresses from H'0000 to H'FFFF is selected for channel 3. Sixteen bidirectional data
register bytes can be manipulated in addition to the basic register set.
 I/O addresses from H'0000 to H'FFFF is selected for channel 4.
• Supports SERIRQ
 Host interrupt requests are transferred serially on a single signal line (SERIRQ).
 On channel 1, HIRQ1 and HIRQ12 can be generated.
 On channels 2, 3 and 4, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
 Operation can be switched between quiet mode and continuous mode.
 The CLKRUN signal can be manipulated to restart the PCI clock (LCLK).
• Power-down modes and interrupts
 The LPC module can be shut down by inputting the LPCPD signal.
 Three pins, PME, LSMI, and LSCI, are provided for general input/output.
IFHSTL0A_000020020700

Section 18 LPC Interface (LPC)

Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 613 of 986
REJ09B0098-0300