Renesas H8S Series Hardware Manual page 675

Bit Bit Name Initial Value Slave Host Description
3 IBFIE3 0
2 IBFIE2 0
1 IBFIE1 0
0 ERRIE 0
Note: Only 0 can be written to bits 6 to 4, to clear the flag.
*
R/W

R/W IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register IDR3 and TWR receive
complete interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
[When TWRIE = 1 in LADR3]

R/W IDR2 Receive Complete interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled

R/W IDR1 Receive Complete interrupt Enable
Enables or disables IBFI1 interrupt to the slave (this
LSI).
0: Input data register (IDR1) receive complete
interrupt requests disabled
1: Input data register (IDR1) receive complete
interrupt requests enabled

R/W Error Interrupt Enable
Enables or disables ERRI interrupt to the slave (this
LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Section 18 LPC Interface (LPC)
Input data register (IDR3) receive complete
interrupt requests enabled
Input data register (IDR3) and TWR receive
complete interrupt requests enabled
Rev. 3.00 Jul. 14, 2005 Page 627 of 986
REJ09B0098-0300