Figure 10.2 (1) Dacnt Access Operation (1) [Cpu → Dacnt(H'aa57) Writing]; Table 10.3 Reading/Writing To 16-Bit Registers - Renesas H8S Series Hardware Manual

Table 10.3 Reading/Writing to 16-bit Registers

Register
DADRA, DADRB
DACNT
[Legend]
O: Enabled access.
Word-unit access includes accessing byte sequentially, first upper byte, and then lower
byte.
×:
The result of the access in the unit cannot be guaranteed.
(a) Write to upper byte
CPU
[H'AA]
Upper byte
(b) Write to lower byte
CPU
[H'57]
Lower byte
Figure 10.2 (1) DACNT Access Operation (1) [CPU → DACNT(H'AA57) Writing]
Read
Word Byte
O O
×
O
Bus interface
Bus interface
Section 10 14-Bit PWM Timer (PWMX)
Write
Word
O
O
Module data bus
TEMP
[H'AA]
DACNTH DACNTL
[ ] [ ]
Module data bus
TEMP
[H'AA]
DACNTH DACNTL
[H'AA] [H'57]
Rev. 3.00 Jul. 14, 2005 Page 267 of 986
Byte
×
×
REJ09B0098-0300