Duty Correction Circuit; Medium-Speed Clock Divider; Bus Master Clock Select Circuit - Renesas H8S Series Hardware Manual

Section 23 Clock Pulse Generator
23.2

Duty Correction Circuit

The duty correction circuit generates the system clock (φ) by correcting the duty of the clock
output from the oscillator.
23.3

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock (φ), and generates φ/2, φ/4, φ/8, φ/16,
and φ/32 clocks.
23.4

Bus Master Clock Select Circuit

The bus master clock select circuit selects a clock to supply to the bus master from either the
system clock (φ) or medium-speed clock (φ/2, φ/4, φ/8, φ/16, or φ/32) by the SCK2 to SCK0 bits
in SBYCR.
Rev. 3.00 Jul. 14, 2005 Page 854 of 986
REJ09B0098-0300