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Manuals and User Guides for Renesas H8S/2437. We have
1
Renesas H8S/2437 manual available for free PDF download: Hardware Manual
Renesas H8S/2437 Hardware Manual (746 pages)
Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S / 2600 Series
Brand:
Renesas
| Category:
Computer Hardware
| Size: 4.02 MB
Table of Contents
General Precautions on Handling of Product
4
Preface
6
List of Registers
7
Table of Contents
9
Section 1 Overview
39
Features
39
Section 1 Overview
40
Figure 1.1 Internal Block Diagram of H8S/2437 Group
40
Internal Block Diagram
40
Section 5 Interrupt Controller
40
Pin Description
41
Pin Assignment
41
Figure 1.2 Pin Assignment of H8S/2437 Group (FP-128B)
41
Pin Assignment in each Operating Mode
42
Table 1.1 Pin Assignment in each Operating Mode
42
Pin Functions
47
Table 1.2 Pin Functions
47
Manual
48
Figure 1.3 Sample Design of Reset Signals Without Affection each Other
52
Section 1 Overview
42
Section 2 CPU
53
Features
53
Differences between H8S/2600 CPU and H8S/2000 CPU
54
Section 2 CPU
54
Differences from H8/300 CPU
55
Differences from H8/300H CPU
55
CPU Operating Modes
56
Normal Mode
56
Figure 2.1 Exception-Handling Vector Table (Normal Mode)
57
Figure 2.2 Stack Structure in Normal Mode
57
Advanced Mode
58
Figure 2.3 Exception-Handling Vector Table (Advanced Mode)
58
Figure 2.4 Stack Structure in Advanced Mode
59
Address Space
60
Figure 2.5 Memory Map
60
Registers
61
Figure 2.6 CPU Registers
61
Figure 2.7 Usage of General Registers
62
General Registers
62
Extended Register (EXR)
63
Figure 2.8 Stack
63
Program Counter (PC)
63
Condition-Code Register (CCR)
64
Initial Values of CPU Internal Registers
65
Multiply-Accumulate Register (MAC)
65
Data Formats
66
General Register Data Formats
66
Figure 2.9 General Register Data Formats (1)
66
Figure 2.9 General Register Data Formats (2)
67
Memory Data Formats
68
Figure 2.10 Memory Data Formats
68
Instruction Set
69
Table 2.1 Instruction Classification
69
Table 2.2 Operation Notation
70
Table of Instructions Classified by Function
70
Table 2.3 Data Transfer Instructions
71
Table 2.4 Arithmetic Operations Instructions (1)
72
Table 2.4 Arithmetic Operations Instructions (2)
73
Table 2.5 Logic Operations Instructions
74
Table 2.6 Shift Instructions
74
Table 2.7 Bit Manipulation Instructions (1)
75
Table 2.7 Bit Manipulation Instructions (2)
76
Table 2.8 Branch Instructions
77
Table 2.9 System Control Instructions
78
Basic Instruction Formats
79
Table 2.10 Block Data Transfer Instructions
79
Figure 2.11 Instruction Formats (Examples)
80
Addressing Modes and Effective Address Calculation
81
Register Direct-Rn
81
Register Indirect-@Ern
81
Register Indirect with Displacement-@(D:16, Ern) or @(D:32, Ern)
81
Table 2.11 Addressing Modes
81
Register Indirect with Post-Increment or Pre-Decrement-@Ern+ or @-Ern
82
Absolute Address-@Aa:8, @Aa:16, @Aa:24, or @Aa:32
82
Table 2.12 Absolute Address Access Ranges
82
Immediate-#XX:8, #XX:16, or #XX:32
83
Program-Counter Relative-@(D:8, PC) or @(D:16, PC)
83
Memory Indirect-@@Aa:8
83
Effective Address Calculation
84
Figure 2.12 Branch Address Specification in Memory Indirect Mode
84
Table 2.13 Effective Address Calculation (1)
85
Table 2.13 Effective Address Calculation (2)
86
Processing States
87
Usage Note
88
Usage Notes on Bit-Wise Operation Instructions
88
Figure 2.13 State Transitions
88
Section 3 MCU Operating Modes
89
Operating Mode Selection
89
Section 2 CPU
89
Register Descriptions
90
Mode Control Register (MDCR)
90
System Control Register (SYSCR)
91
Operating Mode Descriptions
92
Mode 7
92
Section 3 MCU Operating Modes
93
Pin Functions
93
Table 3.2 Pin Functions in each Operating Mode
93
Section 3 MCU Operating Modes
94
Memory Map
94
Figure 3.1 Memory Map
94
Section 4 Exception Handling
95
Exception Handling Types and Priority
95
Section 4 Exception Handling
96
Exception Sources and Exception Vector Table
96
Table 4.2 Exception Handlingvector Table
96
Reset
97
Reset Exception Handling
97
Interrupts after Reset
98
On-Chip Peripheral Functions after Reset Release
98
Figure 4.1 Reset Sequence
98
Traces
99
Interrupts
99
Table 4.3 Status of CCR and EXR after Trace Exception Handling
99
Trap Instruction
100
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
100
Stack Status after Exception Handling
101
Section 4 Exception Handling
101
Figure 4.2 Stack Status after Exception Handling
101
Usage Note
102
Figure 4.3 Operation When SP Value Is Odd
102
Section 5 Interrupt Controller
103
Features
103
Figure 5.1 Block Diagram of Interrupt Controller
104
Section 5 Interrupt Controller
105
Input/Output Pins
105
Register Descriptions
105
Table 5.1 Pin Configuration
105
Interrupt Control Register (INTCR)
106
Interrupt Priority Registers a to K (IPRA to IPRK)
107
IRQ Enable Register (IER)
109
IRQ Sense Control Registers (ISCR)
110
IRQ Status Register (ISR)
112
Software Standby Release IRQ Enable Register (SSIER)
113
Interrupt Sources
113
External Interrupt Sources
113
Internal Interrupts
114
Interrupt Exception Handling Vector Table
114
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
114
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities
115
Interrupt Control Modes and Interrupt Operation
119
Interrupt Control Mode 0
119
Table 5.3 Interrupt Control Modes
119
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0
120
Interrupt Control Mode 2
121
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 2
122
Interrupt Exception Handling Sequence
123
Figure 5.5 Interrupt Exception Handling
124
Interrupt Response Times
125
Table 5.4 Interrupt Response Times
125
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses
125
Usage Notes
126
Contention between Interrupt Generation and Disabling
126
Figure 5.6 Contention between Interrupt Generation and Disabling
126
Instructions that Disable Interrupts
127
Times When Interrupts Are Disabled
127
Interrupts During Execution of EEPMOV Instruction
127
IRQ Pin Select
127
Note on IRQ Status Register (ISR)
128
Section 6 Bus Controller (BSC)
129
Features
129
Section 6 Bus Controller (BSC)
130
Figure 6.1 Block Diagram of Bus Controller
130
Section 6 Bus Controller (BSC)
131
Input/Output Pins
131
Table 6.1 Pin Configuration
131
Register Descriptions
132
Bus Control Register (BCR)
132
Area Control Register (BCRA)
133
Bus Control
135
Bus Specifications
135
Table 6.2 Address Range and External Address Area (Normal Extended Mode)
135
Table 6.3 Bus Specifications for Normal Extended Bus Interface
136
Table 6.4 Address Range and External Address Area (Multiplex Extended Mode)
137
Table 6.5 Bus Specifications for Multiplex Extended Bus Interface (Address Cycle)
137
Table 6.6 Bus Specifications for Multiplex Extended Bus Interface (Data Cycle)
137
External Address Area
138
Chip Select Signals
138
Figure 6.2 Csn Signal Output Polarity and Output Timing
138
Address Strobe/Hold Signal
139
Address Output
139
Bus Interface
140
Data Size and Data Alignment
140
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
140
Figure 6.4 Access Sizes and Data Alignment Control (16-Bit Access Space)
141
Valid Strobes
142
Table 6.7 Data Buses Used and Valid Strobes
142
Basic Operation Timing in Normal Extended Mode
143
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space
143
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space
144
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
145
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)
146
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)
147
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)
148
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access)
149
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
150
Basic Operation Timing in Multiplex Extended Mode
151
Figure 6.13 Bus Timing for 8-Bit, 2-State Data Access Space (with Address Wait)
151
Figure 6.14 Bus Timing for 8-Bit, 2-State Data Access Space (Without Address Wait)
152
Figure 6.15 Bus Timing for 8-Bit, 3-State Data Access Space (with Address Wait)
153
Figure 6.16 Bus Timing for 16-Bit, 2-State Data Access Space (1) (Even Byte Access, with Address Wait)
154
Figure 6.17 Bus Timing for 16-Bit, 2-State Data Access Space (2) (Even Byte Access, Without Address Wait)
155
Figure 6.18 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access, with Address Wait)
156
Figure 6.19 Bus Timing for 16-Bit, 2-State Data Access Space (4) (Odd Byte Access, Without Address Wait)
157
Figure 6.20 Bus Timing for 16-Bit, 2-State Data Access Space (5) (Word Access, with Address Wait)
158
Figure 6.21 Bus Timing for 16-Bit, 2-State Data Access Space (6) (Word Access, Without Address Wait)
159
Figure 6.22 Bus Timing for 16-Bit, 3-State Data Access Space (1) (Even Byte Access, with Address Wait)
160
Figure 6.23 Bus Timing for 16-Bit, 3-State Data Access Space
161
Figure 6.24 Bus Timing for 16-Bit, 3-State Data Access Space
162
Wait Control
163
Figure 6.25 Example of Wait State Insertion Timing (Normal Extended Pin Wait Mode)
164
Figure 6.26 Example of Wait State Insertion Timing (Multiplex Extended Mode)
165
Idle Cycle
166
Figure 6.27 Examples of Idle Cycle Operation
166
Table 6.8 Pin States in Idle Cycle
167
Section 7 I/O Ports
169
Table 7.1 Port Functions (1)
170
Table 7.1 Port Functions (2)
171
Table 7.1 Port Functions (3)
172
Table 7.1 Port Functions (4)
173
Table 7.1 Port Functions (5)
174
Port 0
175
Port 0 Register (PORT0)
175
Pin Functions
175
Port 1
177
Port 1 Data Direction Register (P1DDR)
177
Port 1 Data Register (P1DR)
178
Port 1 Register (PORT1)
178
Port 1 Pull-Up MOS Control Register (P1PCR)
179
Pin Functions
179
Port 1 Input Pull-Up MOS States
180
Table 7.2 Port 1 Input Pull-Up MOS States
180
Port 2
181
Port 2 Data Direction Register (P2DDR)
181
Port 2 Data Register (P2DR)
182
Port 2 Register (PORT2)
182
Port 2 Pull-Up MOS Control Register (P2PCR)
183
Pin Functions
183
Port 2 Input Pull-Up MOS States
192
Table 7.3 Port 2 Input Pull-Up MOS States
192
Port 3
193
Port 3 Data Direction Register (P3DDR)
193
Port 3 Data Register (P3DR)
194
Port 3 Register (PORT3)
194
Port 3 Pull-Up MOS Control Register (P3PCR)
195
Pin Functions
195
Port 3 Input Pull-Up MOS States
199
Table 7.4 Port 3 Input Pull-Up MOS States
199
Port 4
200
Port 4 Data Direction Register (P4DDR)
200
Port 4 Data Register (P4DR)
201
Port 4 Register (PORT4)
201
Pin Functions
202
Port 5
206
Port 5 Data Direction Register (P5DDR)
206
Port 5 Data Register (P5DR)
207
Port 5 Register (PORT5)
207
Pin Functions
208
Port 6
211
Port 6 Data Direction Register (P6DDR)
211
Port 6 Data Register (P6DR)
212
Port 6 Register (PORT6)
212
Port 6 Pull-Up MOS Control Register (P6PCR)
213
Port 6 Open-Drain Control Register (P6ODR)
213
Pin Functions
213
Port 6 Input Pull-Up MOS States
219
Port 7
219
Port 7 Register (PORT7)
219
Table 7.5 Port 6 Input Pull-Up MOS States
219
Pin Functions
220
Port 8
221
Port 8 Data Direction Register (P8DDR)
221
Port 8 Data Register (P8DR)
222
Port 8 Register (PORT8)
222
Pin Functions
223
Port 9
227
Port 9 Data Direction Register (P9DDR)
227
Port 9 Data Register (P9DR)
228
Port 9 Register (PORT9)
228
Port Function Control Register (PFCR)
229
Pin Functions
230
Port a
236
Port a Data Direction Register (PADDR)
236
Port a Data Register (PADR)
237
Port a Register (PORTA)
237
Pin Functions
238
Port B
243
Port B Data Direction Register (PBDDR)
243
Port B Data Register (PBDR)
244
Port B Register (PORTB)
244
Pin Functions
245
Port C
248
Port C Data Direction Register (PCDDR)
248
Port C Data Register (PCDR)
248
Port C Register (PORTC)
249
Pin Functions
249
Change of Peripheral Function Pins
252
Port Control Register 0 (PTCNT0)
252
Port Control Register 1 (PTCNT1)
253
Port Control Register 2 (PTCNT2)
254
Section 8 8-Bit PWM Timer (PWM)
255
Features
255
Figure 8.1 Block Diagram of PWM Timer
255
Input/Output Pin
256
Register Descriptions
256
Table 8.1 Pin Configuration
256
PWM Register Select (PWSL)
257
PWM Data Registers 7 to 0 (PWDR7 to PWDR0)
258
Table 8.2 Internal Clock Selection
258
Table 8.3 Resolution, PWM Conversion Period, and Carrier Frequency When Φ = 20 Mhz
258
PWM Data Polarity Register (PWDPR)
259
PWM Output Enable Register (PWOER)
259
Peripheral Clock Select Register (PCSR)
260
Operation
261
Table 8.4 Duty Cycle of Basic Pulse
261
Figure 8.2 Example of Additional Pulse Timing (When Upper 4 Bits in PWDR = 1000)
262
Table 8.5 Position of Pulses Added to Basic Pulses
262
Section 9 14-Bit PWM Timer (PWMX)
263
Features
263
Figure 9.1 Block Diagram of PWMX (D/A)
263
Input/Output Pins
264
Register Descriptions
264
PWMX (D/A) Counters H and L (DACNTH and DACNTL)
265
PWMX (D/A) Data Registers a and B (DADRA and DADRB)
266
PWMX (D/A) Control Register (DACR)
268
Peripheral Clock Select Register (PCSR)
269
Bus Master Interface
269
Table 9.2 Clock Selection of PWMX
269
Table 9.3 Access Method for Reading/Writing 16-Bit Registers
270
Operation
271
Figure 9.2 PWMX (D/A) Operation
271
Table 9.4 Settings and Operation (Examples When Φ = 20 Mhz)
272
Figure 9.3 Output Waveform (os = 0, DADR Corresponds to T L )
273
Figure 9.4 Output Waveform (os = 1, DADR Corresponds to T H )
274
Figure 9.5 D/A Data Register Configuration When CFS = 1
274
Figure 9.6 Output Waveform When DADR = H'0207 (os = 1)
275
Table 9.5 Locations of Additional Pulses Added to Base Pulse (When CFS = 1)
276
Section 10 16-Bit Free-Running Timer (FRT)
277
Features
277
Section 10 16-Bit Free-Running Timer (FRT)
278
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer
278
Input/Output Pins
279
Register Descriptions
279
Table 10.1 Pin Configuration
279
Free-Running Counter (FRC)
280
Input Capture Registers a to D (ICRA to ICRD)
280
Output Compare Registers a and B (OCRA and OCRB)
280
Output Compare Register DM (OCRDM)
281
Output Compare Registers AR and AF (OCRAR and OCRAF)
281
Timer Interrupt Enable Register (TIER)
282
Timer Control/Status Register (TCSR)
283
Timer Control Register (TCR)
286
Timer Output Compare Control Register (TOCR)
287
Operation
289
Pulse Output
289
Figure 10.2 Example of Pulse Output
289
Operation Timing
290
FRC Increment Timing
290
Figure 10.3 Increment Timing with Internal Clock Source
290
Figure 10.4 Increment Timing with External Clock Source
290
Output Compare Output Timing
291
FRC Clear Timing
291
Figure 10.5 Timing of Output Compare a Output
291
Figure 10.6 Clearing of FRC by Compare-Match a Signal
291
Input Capture Input Timing
292
Figure 10.7 Timing of Input Capture Input Signal (Usual Case)
292
Figure 10.8 Timing of Input Capture Input Signal (When ICRA to ICRD Are Read)
292
Buffered Input Capture Input Timing
293
Figure 10.9 Buffered Input Capture Timing
293
Timing of Input Capture Flag Setting
294
Figure 10.10 Buffered Input Capture Timing (BUFEA = 1)
294
Figure 10.11 Timing of Input Capture Flags (ICFA to ICFD) Setting
294
Timing of Output Compare Flag Setting
295
Timing of Overflow Flag Setting
295
Figure 10.12 Timing of Output Compare Flag (OCFA or OCFB) Setting
295
Figure 10.13 Timing of OVF Flag Setting
295
Automatic Addition Timing
296
10.5.10 Mask Signal Generation Timing
296
Figure 10.14 OCRA Automatic Addition Timing
296
Figure 10.15 Timing of Input Capture Mask Signal Setting
296
Figure 10.16 Timing of Input Capture Mask Signal Clearing
297
Interrupt Sources
298
Table 10.2 FRT Interrupt Sources
298
Usage Notes
299
Conflict between FRC Write and Clear
299
Figure 10.17 FRC Write-Clear Conflict
299
Conflict between FRC Write and Increment
300
Figure 10.18 FRC Write-Increment Conflict
300
Conflict between OCR Write and Compare-Match
301
Figure 10.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function Is Not Used)
301
Switching of Internal Clock and FRC Operation
302
Figure 10.20 Conflict between OCRAR/OCRAF Write and Compare-Match (When Automatic Addition Function Is Used)
302
Table 10.3 Switching of Internal Clock and FRC Operation
303
Section 11 8-Bit Timer (TMR)
305
Features
305
Section 11 8-Bit Timer (TMR)
306
Figure 11.1 Block Diagram of 8-Bit Timer (TMR0 and TMR1)
306
Figure 11.2 Block Diagram of 8-Bit Timer (TMRY and TMRX)
307
Input/Output Pins
308
Table 11.1 Pin Configuration
308
Register Descriptions
309
Timer Counter (TCNT)
311
Time Constant Register a (TCORA)
311
Time Constant Register B (TCORB)
311
Timer Control Register (TCR)
312
Table 11.2 Clock Input to TCNT and Count Condition
313
Timer Control/Status Register (TCSR)
315
Input Capture Register (TICR)
320
Time Constant Register (TCORC)
320
Input Capture Registers R and F (TICRR and TICRF)
320
Timer Input Select Register (TISR)
321
Operation
321
Pulse Output
321
Figure 11.3 Pulse Output Example
321
Operation Timing
322
TCNT Count Timing
322
Figure 11.4 Count Timing for Internal Clock Input
322
Figure 11.5 Count Timing for External Clock Input
322
Timing of CMFA and CMFB Setting at Compare-Match
323
Timing of Timer Output at Compare-Match
323
Figure 11.6 Timing of CMF Setting at Compare-Match
323
Figure 11.7 Timing of Toggled Timer Output by Compare-Match a Signal
323
Timing of Counter Clear at Compare-Match
324
TCNT External Reset Timing
324
Timing of Overflow Flag (OVF) Setting
324
Figure 11.8 Timing of Counter Clear by Compare-Match
324
Figure 11.9 Timing of Counter Clear by External Reset Input
324
TMR0 and TMR1 Cascaded Connection
325
16-Bit Count Mode
325
Figure 11.10 Timing of OVF Flag Setting
325
Compare-Match Count Mode
326
TMRY and TMRX Cascaded Connection
326
16-Bit Count Mode
326
Compare-Match Count Mode
327
Input Capture Operation
327
Figure 11.11 Timing of Input Capture Operation
327
Figure 11.12 Timing of Input Capture Signal (When Input Capture Signal Is Input During TICRR and TICRF Read)
328
Interrupt Sources
329
Table 11.3 Interrupt Sources of 8-Bit Timers TMR0, TMR1, TMRY, and TMRX
329
Usage Notes
330
Conflict between TCNT Write and Clear
330
Figure 11.13 Conflict between TCNT Write and Clear
330
Conflict between TCNT Write and Increment
331
Figure 11.14 Conflict between TCNT Write and Increment
331
Conflict between TCOR Write and Compare-Match
332
Conflict between Compare-Matches a and B
332
Figure 11.15 Conflict between TCOR Write and Compare-Match
332
Switching of Internal Clocks and TCNT Operation
333
Table 11.4 Timer Output Priorities
333
Table 11.5 Switching of Internal Clocks and TCNT Operation
333
Table 11.5 Switching of Internal Clocks and TCNT Operation (Cont)
334
Mode Setting with Cascaded Connection
335
Section 12 16-Bit Timer Pulse Unit (TPU)
337
Features
337
Figure 12.1 Block Diagram of TPU
338
Section 12 16-Bit Timer Pulse Unit (TPU)
339
Table 12.1 TPU Functions
339
Input/Output Pins
341
Table 12.2 Pin Configuration
341
Register Descriptions
342
Timer Control Register (TCR)
343
Table 12.3 CCLR2 to CCLR0 (Channel 0)
344
Table 12.4 CCLR2 to CCLR0 (Channels 1 and 2)
344
Table 12.5 TPSC2 to TPSC0 (Channel 0)
345
Table 12.6 TPSC2 to TPSC0 (Channel 1)
345
Timer Mode Register (TMDR)
346
Table 12.7 TPSC2 to TPSC0 (Channel 2)
346
Table 12.8 MD3 to MD0
347
Timer I/O Control Register (TIOR)
348
Table 12.9 TIORH_0 (Channel 0)
349
Table 12.10 TIORH_0 (Channel 0)
350
Table 12.11 TIORL_0 (Channel 0)
351
Table 12.12 TIORL_0 (Channel 0)
352
Table 12.13 TIOR_1 (Channel 1)
353
Table 12.14 TIOR_1 (Channel 1)
354
Table 12.15 TIOR_2 (Channel 2)
355
Table 12.16 TIOR_2 (Channel 2)
356
Timer Interrupt Enable Register (TIER)
357
Timer Status Register (TSR)
358
Timer Counter (TCNT)
361
Timer General Register (TGR)
361
Timer Start Register (TSTR)
361
Timer Synchro Register (TSYR)
362
Interface to Bus Master
363
16-Bit Registers
363
Figure 12.2 16-Bit Register Access Operation [Bus Master ↔ TCNT (16 Bits)]
363
Figure 12.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)]
363
Figure 12.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)]
364
Figure 12.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)]
364
Operation
365
Basic Functions
365
Figure 12.6 Example of Counter Operation Setting Procedure
365
Figure 12.7 Free-Running Counter Operation
366
Figure 12.8 Periodic Counter Operation
367
Figure 12.9 Example of Setting Procedure for Waveform Output by Compare Match
367
Figure 12.10 Example of 0 Output/1 Output Operation
368
Figure 12.11 Example of Toggle Output Operation
368
Figure 12.12 Example of Setting Procedure for Input Capture Operation
369
Figure 12.13 Example of Input Capture Operation
369
Synchronous Operation
370
Figure 12.14 Example of Synchronous Operation Setting Procedure
370
Figure 12.15 Example of Synchronous Operation
371
Buffer Operation
372
Figure 12.16 Compare Match Buffer Operation
372
Figure 12.17 Input Capture Buffer Operation
372
Table 12.17 Register Combinations in Buffer Operation
372
Figure 12.18 Example of Buffer Operation Setting Procedure
373
Figure 12.19 Example of Buffer Operation (1)
373
Figure 12.20 Example of Buffer Operation (2)
374
Cascaded Operation
375
Figure 12.21 Cascaded Operation Setting Procedure
375
Table 12.18 Cascaded Combinations
375
PWM Modes
376
Figure 12.22 Example of Cascaded Operation (1)
376
Figure 12.23 Example of Cascaded Operation (2)
376
Table 12.19 PWM Output Registers and Output Pins
377
Figure 12.24 Example of PWM Mode Setting Procedure
378
Figure 12.25 Example of PWM Mode Operation (1)
378
Figure 12.26 Example of PWM Mode Operation (2)
379
Figure 12.27 Example of PWM Mode Operation (3)
380
Phase Counting Mode
381
Figure 12.28 Example of Setting Procedure for Phase Counting Mode
381
Table 12.20 Clock Input Pins for Phase Counting Mode
381
Figure 12.29 Example of Phase Counting Mode 1 Operation
382
Table 12.21 Up/Down-Count Conditions in Phase Counting Mode 1
382
Figure 12.30 Example of Phase Counting Mode 2 Operation
383
Table 12.22 Up/Down-Count Conditions in Phase Counting Mode 2
383
Figure 12.31 Example of Phase Counting Mode 3 Operation
384
Table 12.23 Up/Down-Count Conditions in Phase Counting Mode 3
384
Figure 12.32 Example of Phase Counting Mode 4 Operation
385
Table 12.24 Up/Down-Count Conditions in Phase Counting Mode 4
385
Interrupt Sources
386
Interrupt Source and Priority
386
Table 12.25 TPU Interrupts
386
A/D Converter Activation
387
Operation Timing
388
Input/Output Timing
388
Figure 12.33 Count Timing in Internal Clock Operation
388
Figure 12.34 Count Timing in External Clock Operation
388
Figure 12.35 Output Compare Output Timing
389
Figure 12.36 Input Capture Input Signal Timing
389
Figure 12.37 Counter Clear Timing (Compare Match)
390
Figure 12.38 Counter Clear Timing (Input Capture)
390
Figure 12.39 Buffer Operation Timing (Compare Match)
391
Figure 12.40 Buffer Operation Timing (Input Capture)
391
Interrupt Signal Timing
392
Figure 12.41 TGI Interrupt Timing (Compare Match)
392
Figure 12.42 TGI Interrupt Timing (Input Capture)
393
Figure 12.43 TCIV Interrupt Setting Timing
393
Figure 12.44 TCIU Interrupt Setting Timing
394
Figure 12.45 Timing for Status Flag Clearing by CPU
394
Usage Notes
395
Figure 12.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
395
Figure 12.47 Contention between TCNT Write and Clear Operations
396
Figure 12.48 Contention between TCNT Write and Increment Operations
396
Figure 12.49 Contention between TGR Write and Compare Match
397
Figure 12.50 Contention between Buffer Register Write and Compare Match
397
Figure 12.51 Contention between TGR Read and Input Capture
398
Figure 12.52 Contention between TGR Write and Input Capture
398
Figure 12.53 Contention between Buffer Register Write and Input Capture
399
Figure 12.54 Contention between Overflow and Counter Clearing
400
Figure 12.55 Contention between TCNT Write and Overflow
400
Section 13 Timer Connection
403
Features
403
Figure 13.1 Schematic Diagram of Timer Connection
404
Figure 13.2 Block Diagram of Timer Connection
405
Section 13 Timer Connection
406
Input/Output Pins
406
Table 13.1 Pin Configuration
406
Register Descriptions
407
Timer Connection Register I (TCONRI)
407
Table 13.2 Synchronization Signal Connection Enable
409
Timer Connection Register O (TCONRO)
410
Table 13.3 HSYNCO Output Selection
412
Table 13.4 VSYNCO Output Selection
412
Timer Connection Register S (TCONRS)
413
Edge Sense Register (SEDGR)
415
Timer Extended Control Register (TECR)
417
Operation
418
PWM Decoding (PDC Signal Generation)
418
Figure 13.3 Block Diagram for PWM Decoding
418
Figure 13.4 Timing Chart for PWM Decoding
419
Table 13.5 Examples of TCR Settings
419
Table 13.6 Examples of TCORB (Pulse Width Threshold) Settings
419
Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
420
Figure 13.5 Block Diagram for Clamp Waveform Generation
421
Figure 13.6 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)
421
Figure 13.7 Timing Chart for Clamp Waveform Generation (CL3 Signal)
422
Measurement of 8-Bit Timer Divided Waveform Period
423
Figure 13.8 Block Diagram for Measurement of 8-Bit Timer Divided Waveform Period
423
Table 13.7 Examples of TCR and TCSR Settings
424
2Fh Modification of IHI Signal
425
Figure 13.9 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods
425
Figure 13.10 Block Diagram for 2Fh Modification of IHI Signal
426
Table 13.8 Examples of TCR, TCSR, TCOR, and OCRDM Settings
426
IVI Signal Fall Modification and IHI Synchronization
427
Figure 13.11 2Fh Modification Timing Chart
427
Figure 13.12 Block Diagram for IVI Signal Fall Modification and IHI Signal Operation
428
Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
429
Figure 13.13 Fall Modification and IHI Synchronization Timing Chart
429
Table 13.9 Examples of TCR, TCSR, and TCORB Settings
429
Figure 13.14 Block Diagram for IVG Signal Generation
430
Figure 13.15 Block Diagram for IHG Signal Generation
431
Table 13.10 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR Settings
432
Figure 13.16 IVG Signal/Ihg Signal/Cl4 Signal Timing Chart
433
HSYNCO Output
434
Table 13.11 HSYNCO Output Modes
434
VSYNCO Output
435
Table 13.12 VSYNCO Output Modes
435
CBLANK Output
436
Figure 13.17 CBLANK Output Waveform Generation
436
Section 14 Duty Measurement Circuit
437
Features
437
Section 14 Duty Measurement Circuit
438
Figure 14.1 Block Diagram of Duty Measurement Circuit
438
Input/Output Pins
439
Table 14.1 Pin Configuration
439
Register Descriptions
440
Free-Running Counter (TWCNT)
440
Input Capture Register (TWICR)
440
Duty Measurement Control Register 1 (TWCR1)
441
Duty Measurement Control Register 2 (TWCR2)
442
Operation
444
Duty Measurement for External Event Signal
444
Figure 14.2 Example of Duty Measurement for External Event Signal
444
Operation Timing
445
TWCNT Count Timing
445
TWCNT Clear Timing by Setting START Bit
445
Figure 14.3 TWCNT Count Timing
445
Figure 14.4 TWCNT Clear Timing by Setting START Bit
445
Count Start Timing for Duty Measurement
446
Capture Timing During Duty Measurement
446
Figure 14.5 Count Start Timing for Duty Measurement
446
Figure 14.6 Input Capture Timing During Duty Measurement
446
Clear Timing for START Bit When Duty Measurement Ends
447
Set Timing for Duty Measurement End Flag (ENDF)
447
Figure 14.7 Clear Timing for START Bit When Duty Measurement Ends
447
Figure 14.8 Set Timing for Duty Measurement End Flag (ENDF)
447
Set Timing for Overflow Flag (OVF)
448
Interrupt Sources
448
Figure 14.9 Set Timing for OVF Flag
448
Table 14.2 Interrupt Sources for Duty Measurement Circuit
448
Usage Notes
449
Conflict between TWCNT Write and Increment
449
Write to START Bit During Free-Running Counter Operation
449
Figure 14.10 TWCNT Write-Increment Conflict
449
Figure 14.11 Write to START Bit During Free-Running Counter Operation
449
Switching of Internal Clock and TWCNT Operation
450
Table 14.3 Switching of Internal Clock and TWCNT Operation
450
Switching of External Event Signal and Operation of Edge Detection Circuit
452
Table 14.4 Switching of External Event Signal and Operation of Edge Detection Circuit
452
Section 15 Watchdog Timer (WDT)
455
Features
455
Figure 15.1 Block Diagram of WDT
455
Register Descriptions
456
Timer Counter (TCNT)
456
Timer Control/Status Register (TCSR)
456
Operation
458
Watchdog Timer Mode
458
Figure 15.2 Watchdog Timer Mode (RST/NMI = 1) Operation
458
Interval Timer Mode
459
Figure 15.3 Interval Timer Mode Operation
459
Figure 15.4 OVF Flag Set Timing
459
Internal Reset Signal Generation Timing
460
Interrupt Sources
460
Figure 15.5 Internal Reset Signal Generation Timing
460
Table 15.1 Interrupt Source
460
Usage Notes
461
Notes on Register Access
461
Figure 15.6 Writing to TCNT and TCSR
461
Conflict between Timer Counter (TCNT) Write and Increment
462
Changing Values of CKS2 to CKS0 Bits
462
Switching between Watchdog Timer Mode and Interval Timer Mode
462
Figure 15.7 Conflict between TCNT Write and Increment
462
Section 16 Serial Communication Interface (SCI)
463
Features
463
Figure 16.1 Block Diagram of SCI
464
Input/Output Pins
465
Table 16.1 Pin Configuration
465
Register Descriptions
466
Receive Shift Register (RSR)
466
Receive Data Register (RDR)
466
Transmit Data Register (TDR)
466
Transmit Shift Register (TSR)
467
Serial Mode Register (SMR)
467
Serial Control Register (SCR)
469
Serial Status Register (SSR)
471
Serial Interface Mode Register (SCMR)
473
Bit Rate Register (BRR)
474
Table 16.2 Relationships between N Setting in BRR and Bit Rate B
474
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
475
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
476
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
477
Table 16.4 Maximum Bit Rate for each Operating Frequency (Asynchronous Mode)
478
Table 16.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
478
Table 16.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
479
Table 16.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
479
Operation in Asynchronous Mode
480
Figure 16.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
480
Data Transfer Format
481
Table 16.8 Serial Transfer Formats (Asynchronous Mode)
481
Figure 16.3 Receive Data Sampling Timing in Asynchronous Mode
482
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
482
Clock
483
Figure 16.4 Relation between Output Clock and Transmit Data Phase
483
Figure 16.5 Sample SCI Initialization Flowchart
484
SCI Initialization (Asynchronous Mode)
484
Figure 16.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
485
Serial Data Transmission (Asynchronous Mode)
485
Figure 16.7 Sample Serial Transmission Flowchart
486
Figure 16.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit)
487
Serial Data Reception (Asynchronous Mode)
487
Table 16.9 SSR Status Flags and Receive Data Handling
488
Figure 16.9 Sample Serial Reception Flowchart (1)
489
Figure 16.9 Sample Serial Reception Flowchart (2)
490
Multiprocessor Communication Function
491
Figure 16.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
492
Figure 16.11 Sample Multiprocessor Serial Transmission Flowchart
493
Multiprocessor Serial Data Transmission
493
Figure 16.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
494
Multiprocessor Serial Data Reception
494
Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (1)
495
Figure 16.13 Sample Multiprocessor Serial Reception Flowchart (2)
496
Operation in Clocked Synchronous Mode
497
Clock
497
SCI Initialization (Clocked Synchronous Mode)
497
Figure 16.14 Data Format in Clocked Synchronous Communication (LSB-First)
497
Serial Data Transmission (Clocked Synchronous Mode)
498
Figure 16.15 Sample SCI Initialization Flowchart
498
Figure 16.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
499
Figure 16.17 Sample Serial Transmission Flowchart
500
Serial Data Reception (Clocked Synchronous Mode)
501
Figure 16.18 Example of SCI Receive Operation in Clocked Synchronous Mode
501
Figure 16.19 Sample Serial Reception Flowchart
502
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
503
Figure 16.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
504
Interrupt Sources
505
Table 16.10 SCI Interrupt Sources
506
Usage Notes
507
Module Stop Mode Setting
507
Break Detection and Processing
507
Mark State and Break Sending
507
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
507
Relation between Writing to TDR and TDRE Flag
507
SCI Operations During Mode Transitions
508
Figure 16.21 Sample Flowchart for Mode Transition During Transmission
508
Figure 16.22 Pin States During Transmission in Asynchronous Mode (Internal Clock)
509
Figure 16.23 Pin States During Transmission in Clocked Synchronous Mode
509
Figure 16.24 Sample Flowchart for Mode Transition During Reception
510
Switching from SCK Pins to Port Pins
511
Figure 16.25 Switching from SCK Pins to Port Pins
511
Figure 16.26 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins
511
Section 17 I C Bus Interface 3 (IIC3)
513
Features
513
Section 17 IC Bus Interface 3 (IIC3)
514
Figure 17.1 Block Diagram of I
514
Figure 17.2 External Circuit Connections of I/O Pins
515
Input/Output Pins
516
Register Descriptions
516
Table 17.1 Pin Configuration
516
C Bus Control Register a (ICCRA)
517
C Bus Control Register B (ICCRB)
518
Table 17.2 Transfer Rate
518
C Bus Mode Register (ICMR)
520
C Bus Interrupt Enable Register (ICIER)
521
C Bus Status Register (ICSR)
523
Slave Address Register (SAR)
525
Slave Address Register a (SARA)
525
Slave Address Mask Register (SAMR)
526
Slave Address Register B (SARB)
526
C Bus Receive Data Register (ICDRR)
527
C Bus Status Register a (ICSRA)
527
C Bus Transmit Data Register (ICDRT)
527
C Bus Shift Register (ICDRS)
528
Operation
529
C Bus Format
529
Figure 17.3 I 2 C Bus Formats
529
Figure 17.4 I 2 C Bus Timing
529
Master Transmit Operation
530
Figure 17.5 Operation Timing in Master Transmit Mode (1)
531
Figure 17.6 Operation Timing in Master Transmit Mode (2)
531
Master Receive Operation
532
Figure 17.7 Operation Timing in Master Receive Mode (1)
533
Figure 17.8 Operation Timing in Master Receive Mode (2)
533
Slave Transmit Operation
534
Figure 17.9 Operation Timing in Slave Transmit Mode (1)
535
Slave Receive Operation
536
Figure 17.10 Operation Timing in Slave Transmit Mode (2)
536
Figure 17.11 Operation Timing in Slave Receive Mode (1)
537
Figure 17.12 Operation Timing in Slave Receive Mode (2)
537
Noise Canceler
538
Example of Use
538
Figure 17.13 Block Diagram of Noise Canceler
538
Figure 17.14 Sample Flowchart for Master Transmit Mode
539
Figure 17.15 Sample Flowchart for Master Receive Mode
540
Figure 17.16 Sample Flowchart for Slave Transmit Mode
541
Figure 17.17 Sample Flowchart for Slave Receive Mode
542
Interrupt Requests
543
Table 17.3 Interrupt Requests
543
Bit Synchronous Circuit
544
Figure 17.18 Timing of Bit Synchronous Circuit
544
Table 17.4 Time for Monitoring SCL
544
Section 18 A/D Converter
545
Features
545
Section 18 A/D Converter
546
Figure 18.1 Block Diagram of A/D Converter
546
Input/Output Pins
547
Table 18.1 Pin Configuration
547
Register Descriptions
548
A/D Data Registers a to H (ADDRA to ADDRH)
548
Table 18.2 Analog Input Channels and Corresponding ADDR
548
A/D Control/Status Register (ADCSR)
549
A/D Control Register (ADCR)
551
Operation
552
Single Mode
552
Scan Mode
552
Input Sampling and A/D Conversion Time
553
Figure 18.2 A/D Conversion Timing
553
External Trigger Input Timing
554
Table 18.3 A/D Conversion Time (Single Mode)
554
Table 18.4 A/D Conversion Time (Scan Mode)
554
Interrupt Source
555
Figure 18.3 External Trigger Input Timing
555
Table 18.5 A/D Converter Interrupt Source
555
A/D Conversion Accuracy Definitions
556
Figure 18.4 A/D Conversion Accuracy Definitions
557
Figure 18.5 A/D Conversion Accuracy Definitions
557
Usage Notes
558
Module Stop Mode Setting
558
Permissible Signal Source Impedance
558
Figure 18.6 Example of Analog Input Circuit
558
Influences on Absolute Accuracy
559
Setting Range of Analog Power Supply and Other Pins
559
Notes on Board Design
559
Notes on Noise Countermeasures
559
Figure 18.7 Example of Analog Input Protection Circuit
560
Table 18.6 Analog Pin Specifications
560
Section 19 RAM
561
Section 20 Flash Memory (0.18-ΜM F-ZTAT Version)
563
Features
563
Section 20 Flash Memory (0.18- ΜµM F-ZTAT Version)
564
Figure 20.1 Block Diagram of Flash Memory
564
Mode Transition
565
Figure 20.2 Mode Transition of Flash Memory
565
Mode Comparison
566
Table 20.1 Comparison of Programming Modes
566
Flash Memory MAT Configuration
567
Figure 20.3 Flash Memory Configuration
567
Block Division
568
Figure 20.4 Block Division of User MAT
568
Programming/Erasing Interface
569
Figure 20.5 Overview of User Procedure Program
569
Input/Output Pins
571
Register Descriptions
571
Table 20.2 Pin Configuration
571
Programming/Erasing Interface Registers
572
Table 20.3 Registers/Parameters and Target Modes
572
Programming/Erasing Interface Parameters
579
Table 20.4 Parameters and Target Modes
580
On-Board Programming Mode
589
Boot Mode
589
Table 20.5 Setting On-Board Programming Mode
589
Figure 20.6 System Configuration in Boot Mode
590
Figure 20.7 Automatic-Bit-Rate Adjustment Operation of SCI
590
Table 20.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
591
Figure 20.8 Overview of State Transition Diagram in Boot Mode
592
User Program Mode
593
Figure 20.9 Overview of Programming/Erasing Flow
593
Figure 20.10 RAM Map When Programming/Erasing Is Executed
594
Figure 20.11 Programming Procedure
595
Figure 20.12 Erasing Procedure
600
Figure 20.13 Repeating Procedure of Erasing and Programming
602
User Boot Mode
603
Figure 20.14 Procedure for Programming User MAT in User Boot Mode
604
Figure 20.15 Procedure for Erasing User MAT in User Boot Mode
605
Storable Area for Procedure Program and Program Data
606
Table 20.7 Executable MAT
607
Table 20.8 (1) Usable Area for Programming in User Program Mode
608
Table 20.8 (2) Usable Area for Erasure in User Program Mode
610
Table 20.8 (3) Usable Area for Programming in User Boot Mode
612
Table 20.8 (4) Usable Area for Erasure in User Boot Mode
614
Protection
616
Hardware Protection
616
Table 20.9 Hardware Protection
616
Software Protection
617
Error Protection
617
Table 20.10 Software Protection
617
Switching between User MAT and User Boot MAT
618
Figure 20.16 Transitions to Error Protection State
618
Figure 20.17 Switching between User MAT and User Boot MAT
619
Programmer Mode
620
Figure 20.18 Memory Map in Programmer Mode
620
Serial Communication Interface Specification for Boot Mode
621
Figure 20.19 Boot Program States
622
Figure 20.20 Bit-Rate-Adjustment Sequence
623
Figure 20.21 Communication Protocol Format
624
Table 20.11 Inquiry/Selection Commands
625
Figure 20.22 New Bit-Rate Selection Sequence
634
Table 20.12 Programming/Erasing Commands
636
Figure 20.23 Programming Sequence
637
Figure 20.24 Erasure Sequence
640
Table 20.13 Status Codes
644
Table 20.14 Error Codes
645
Usage Notes
646
Section 21 Clock Pulse Generator
649
Figure 21.1 Block Diagram of Clock Pulse Generator
649
Register Description
650
System Clock Control Register (SCKCR)
650
Section 21 Clock Pulse Generator
652
Oscillator
652
Connecting Crystal Resonator
652
Figure 21.2 Typical Connection to Crystal Resonator
652
Figure 21.3 Equivalent Circuit of Crystal Resonator
652
Table 21.1 Damping Resistor Values
652
Table 21.2 Crystal Resonator Parameters
652
External Clock Input Method
653
Figure 21.4 Example of External Clock Input
653
Table 21.3 External Clock Input Conditions
653
Figure 21.5 External Clock Input Timing
654
Figure 21.6 Timing of Output Stabilization Delay Time for External Clock
654
Table 21.4 Output Stabilization Delay Time for External Clock
654
Duty Adjustment Circuit
655
Divider
655
Usage Notes
655
Note on Resonator
655
Notes on Board Design
655
Figure 21.7 Note on Board Design of Oscillation Circuit Section
655
Notes on Operation Confirmation
656
Section 22 Power-Down Modes
657
Section 22 Power-Down Modes
658
Table 22.1 Operating Modes and Internal States of LSI
658
Figure 22.1 Mode Transitions
659
Register Descriptions
660
Standby Control Register (SBYCR)
660
Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
662
Extension Module Stop Control Registers H and L
663
(Exmstpcrh, Exmstpcrl)
663
Operation
664
Clock Division Mode
664
Sleep Mode
664
Software Standby Mode
665
Table 22.2 Oscillation Stabilization Time Settings
666
Figure 22.2 Software Standby Mode Application Example
667
Hardware Standby Mode
668
Module Stop Mode
669
Clock Output Control
669
Figure 22.3 Hardware Standby Mode Timing
669
Table 22.3 Φ Pin State in each Processing State
670
Usage Notes
671
I/O Port State
671
Current Consumption During Oscillation Stabilization Standby Period
671
On-Chip Peripheral Module Interrupts
671
Writing to MSTPCR, EXMSTPCR
671
Notes on Clock Division Mode
671
Section 23 List of Registers
673
Register Addresses (Address Order)
674
Register Bits
685
Register States in each Operating Mode
697
Section 24 Electrical Characteristics
707
Section 24 Electrical Characteristics
707
Absolute Maximum Ratings
707
Table 24.1 Absolute Maximum Ratings
707
DC Characteristics
708
Table 24.2 DC Characteristics
708
Figure 24.1 Darlington Transistor Drive Circuit (Example)
710
Table 24.3 Permissible Output Currents
710
AC Characteristics
711
Clock Timing
711
Figure 24.2 Output Load Circuit
711
Figure 24.3 System Clock Timing
712
Figure 24.4 Oscillation Stabilization Timing
712
Table 24.4 Clock Timing
712
Control Signal Timing
713
Figure 24.5 Oscillation Stabilization Timing (Exiting Software Standby Mode)
713
Table 24.5 Control Signal Timing
713
Figure 24.6 Reset Input Timing
714
Figure 24.7 Interrupt Input Timing
714
Bus Timing
715
Table 24.6 Bus Timing (Normal Extension)
715
Figure 24.8 Basic Bus Timing/2-State Access
716
Figure 24.9 Basic Bus Timing/3-State Access
717
Figure 24.10 Basic Bus Timing/3-State Access with One Wait State
718
Table 24.7 Bus Timing (Multiplex Extension)
719
Figure 24.11 Muliplex Bus Timing/2-State Access
720
Figure 24.12 Multiplex Bus Timing/3-State Access
721
Figure 24.13 Multiplex Bus Timing/3-State Access with One Wait State
722
Timing of On-Chip Peripheral Modules
723
Table 24.8 Timing of On-Chip Peripheral Modules
723
Figure 24.14 I/O Port Input/Output Timing
724
Figure 24.15 FRT Input/Output Timing
724
Figure 24.16 FRT Clock Input Timing
724
Figure 24.17 TPU Input/Output Timing
725
Figure 24.18 TPU Clock Input Timing
725
Figure 24.19 8-Bit Timer Output Timing
725
Figure 24.20 8-Bit Timer Clock Input Timing
725
Figure 24.21 8-Bit Timer Reset Input Timing
726
Figure 24.22 PWM, PWMX Output Timing
726
Figure 24.23 SCK Clock Input Timing
726
Figure 24.24 SCI Input/Output Timing (Clock Synchronous Mode)
726
Figure 24.25 A/D Converter External Trigger Input Timing
727
Table 24.9 I 2 C Bus Interface Timing
727
Figure 24.26 Input/Output Timing of I
728
A/D Conversion Characteristics
729
Table 24.10 A/D Conversion Characteristics (AN15 to AN0 Input: 134/266-State Conversion)
729
Flash Memory Characteristics
730
Table 24.11 Flash Memory Characteristics
730
Usage Notes
731
Figure 24.27 Connection of VCL Capacitor
731
Appendix
733
Appendix
733
I/O Port States in each Pin State
733
Table A.1 I/O Port States in each Pin State
733
Product Lineup
735
Appendix
736
Package Dimensions
736
Figure C.1 Package Dimensions (FP-128B)
736
Index
737
Section 16 Serial Communication Interface (SCI)
740
Section 13 Timer Connection
740
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