Lpc Channel 3 Address Registers H And L (Ladr3H And Ladr3L) - Renesas H8S Series Hardware Manual

18.3.4

LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)

LADR3 stores the LPC channel 3 host address and controls the operation of the bidirectional data
registers. The contents of the address fields in LADR3 must not be changed while channel 3 is
operating (while LPC3E is set to 1).
• LADR3H
Bit Bit Name Initial Value Slave Host Description
7 Bit 15 0
6 Bit 14 0
5 Bit 13 0
4 Bit 12 0
3 Bit 11 0
2 Bit 10 0
1 Bit 9 0
0 Bit 8 0
• LADR3L
Bit Bit Name Initial Value Slave Host Description
7 Bit 7 0
6 Bit 6 0
5 Bit 5 0
4 Bit 4 0
3 Bit 3 0

2 0
1 Bit 1 0
R/W

R/W Channel 3 Address Bits 15 to 8

R/W Store the LPC channel 3 host address.

R/W

R/W

R/W

R/W

R/W

R/W
R/W

R/W Channel 3 Address Bits 7 to 3

R/W Set the LPC channel 3 host address.

R/W

R/W

R/W

R/W Reserved
The initial value should not be changed.

R/W Channel 3 Address Bit 1
Sets the LPC channel 3 host address.
Section 18 LPC Interface (LPC)
Rev. 3.00 Jul. 14, 2005 Page 629 of 986
REJ09B0098-0300