Renesas H8S Series Hardware Manual page 112

Section 3 MCU Operating Modes
Bit Bit Name Initial Value
4 IICE 0
Rev. 3.00 Jul. 14, 2005 Page 64 of 986
REJ09B0098-0300
R/W Description
2
R/W I C Master Enable
When the RELOCATE bit is cleared to 0, enables or
disables CPU access for IIC registers (ICCR, ICSR,
ICDR/SARX, ICMR/SAR, and DDCSWR), PWMX
registers (DADRAH/DACR, DADRAL,
DADRBH/DACNTH, and DADRBL/DACNTL), and SCI
registers (SMR, BRR, and SCMR).
0: SCI_1 registers are accessed in areas from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
SCI_2 registers are accessed in areas from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to
H'(FF)FFA7.
Access is prohibited in areas from H'(FF)FFD8 to
H'(FF)FFD9 and from H'(FF)FFDE to H'(FF)FFDF.
1: IIC_1 registers are accessed in areas from
H'(FF)FF88 to H'(FF)FF89 and from H'(FF)FF8E to
H'(FF)FF8F.
PWMX registers are accessed in areas from
H'(FF)FFA0 to H'(FF)FFA1 and from H'(FF)FFA6 to
H'(FF)FFA7.
IIC_0 registers are accessed in areas from
H'(FF)FFD8 to H'(FF)FFD9 and from H'(FF)FFDE to
H'(FF)FFDF.
DDCSWR is accessed in areas of H'(FF)FEE6
When the RELOCATE bit is set to 1, this bit is disabled.
For details, see section 3.2.4, System Control Register
3 (SYSCR3) and section 25, List of Registers.