Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2357 Group, H8S/2357F-ZTAT H8S/2398F-ZTAT Hardware Manual Renesas 16-Bit Single-chip Microcomputer H8S Family / H8S/2300 Series Rev. 6.00 Revision date: Oct. 28, 2004 www.renesas.com...
Page 2 (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
Page 3 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise.
Page 5 This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology, Corp. ZTAT is a registered trademark of Renesas Technology, Corp.
Page 6 User's manuals for development tools: Manual Title Document No. H8S, H8/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor REJ10B0058 User's Manual H8S, H8/300 Series Simulator/Debugger (for Windows) User's Manual ADE-702-037 H8S, H8/300 Series High-performance Embedded Workshop User's Manual ADE-702-201 Application Note: Manual Title Document No.
Page 7 Main Revisions for This Edition I t e m P a g e Revision (See Manual for Details) 1.1 Overview Product lineup Table 1-1 Overview HD64F2398F20T* and HD64F2398TE20T* added 5V version F-ZTAT HD64F2357F20 HD64F2398F20 Version* HD64F2357TE20 HD64F2398TE20 HD64F2398F20T * HD64F2398TE20T* Note 3 added as follows Note: 3.
Page 8 I t e m P a g e Revision (See Manual for Details) 9.8.2 Register Configuration Note added Port A MOS Pull-Up Control Register (PAPCR) (ON-Chip ROM Version Only) PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
Page 9 I t e m P a g e Revision (See Manual for Details) 9.12.2 Register Configuration Note added Port E MOS Pull-Up Control Register (PEPCR) (ON-Chip ROM Version Only) PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
Page 10 I t e m P a g e Revision (See Manual for Details) 19.18.2 Program-Verify Mode Figure 19-48 amended, note *6 added Figure 19-48 Program/Program- Write pulse application subroutine Start of programming Perform programming in the erased state. Sub-routine write pulse Start Verify Flowchart Do not perform additional programming...
Page 11 I t e m P a g e Revision (See Manual for Details) A.5 Bus States during Instruction Table A-6 amended Execution Table A-6 Instruction Execution Cycles Rev.6.00 Oct.28.2004 page vii of xxiv REJ09B0138-0600H...
Page 12 I t e m P a g e Revision (See Manual for Details) G. Product Code Lineup 1014 Table G-2 amended Table G-2 H8S/2398, H8S/2394, Product Type Product Code Mark Code Package (Package Code) H8S/2392, H8S/2390 Group Product H8S/2398 Masked ROM HD6432398 HD6432398TE* 120-pin TQFP (TFP-120)
Page 13: Table Of Contents
Contents Section 1 Overview..........................1 Overview..................................1 Block Diagram................................6 Pin Description ................................7 1.3.1 Pin Arrangement ............................. 7 1.3.2 Pin Functions in Each Operating Mode......................11 1.3.3 Pin Functions..............................15 Section 2 CPU.............................21 Overview..................................21 2.1.1 Features ................................. 21 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ................22 2.1.3 Differences from H8/300 CPU........................22 2.1.4...
Page 14 Section 3 MCU Operating Modes ......................55 Overview..................................55 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) ................. 55 3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) ....56 3.1.3 Register Configuration ..........................57 Register Descriptions..............................57 3.2.1 Mode Control Register (MDCR)........................57 3.2.2 System Control Register (SYSCR) .......................
Page 15 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ..................84 5.2.3 IRQ Enable Register (IER) ........................... 85 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)................86 5.2.5 IRQ Status Register (ISR) ..........................86 Interrupt Sources................................. 87 5.3.1 External Interrupts............................
Page 16 6.4.5 Wait Control ..............................136 DRAM Interface............................... 138 6.5.1 Overview ..............................138 6.5.2 Setting DRAM Space ..........................138 6.5.3 Address Multiplexing ..........................138 6.5.4 Data Bus ..............................138 6.5.5 Pins Used for DRAM Interface ........................139 6.5.6 Basic Timing ............................... 140 6.5.7 Precharge State Control..........................141 6.5.8 Wait Control ..............................141 6.5.9...
Page 17 7.3.1 Memory Address Register (MAR) ......................181 7.3.2 I/O Address Register (IOAR)........................181 7.3.3 Execute Transfer Count Register (ETCR)....................181 7.3.4 DMA Control Register (DMACR)......................183 7.3.5 DMA Band Control Register (DMABCR)....................186 Register Descriptions (3) ............................190 7.4.1 DMA Write Enable Register (DMAWER) ....................190 7.4.2 DMA Terminal Control Register (DMATCR)....................192 7.4.3...
Page 18 8.3.7 Block Transfer Mode........................... 258 8.3.8 Chain Transfer............................. 259 8.3.9 Operation Timing ............................260 8.3.10 Number of DTC Execution States....................... 261 8.3.11 Procedures for Using DTC ..........................262 8.3.12 Examples of Use of the D7TC........................262 Interrupts................................... 264 Usage Notes ................................264 Section 9 I/O Ports..........................265 Overview...................................
Page 19 9.11.2 Register Configuration (On-Chip ROM Version Only)................318 9.11.3 Pin Functions............................... 320 9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only)..............321 9.12 Port E ..................................322 9.12.1 Overview ..............................322 9.12.2 Register Configuration ..........................323 9.12.3 Pin Functions............................... 325 9.12.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) ..............326 9.13 Port F ..................................327 9.13.1 Overview ..............................
Page 20 10.7 Usage Notes ................................404 Section 11 Programmable Pulse Generator (PPG) ................411 11.1 Overview................................... 411 11.1.1 Features ............................... 411 11.1.2 Block Diagram............................. 412 11.1.3 Pin Configuration ............................413 11.1.4 Registers ..............................414 11.2 Register Descriptions..............................415 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................415 11.2.2 Output Data Registers H and L (PODRH, PODRL) ...................
Page 21 12.6.2 Contention between TCNT Write and Increment ..................449 12.6.3 Contention between TCOR Write and Compare Match ................450 12.6.4 Contention between Compare Matches A and B ..................450 12.6.5 Switching of Internal Clocks and TCNT Operation................... 451 12.6.6 Interrupts and Module Stop Mode....................... 452 Section 13 Watchdog Timer ......................453 13.1 Overview...................................
Page 22 14.4 SCI Interrupts ................................512 14.5 Usage Notes ................................514 Section 15 Smart Card Interface.......................517 15.1 Overview................................... 517 15.1.1 Features ............................... 517 15.1.2 Block Diagram............................. 518 15.1.3 Pin Configuration ............................518 15.1.4 Register Configuration ..........................519 15.2 Register Descriptions..............................520 15.2.1 Smart Card Mode Register (SCMR) ......................520 15.2.2 Serial Status Register (SSR)........................521 15.2.3 Serial Mode Register (SMR)........................
Page 23 17.2.2 D/A Control Register (DACR)........................557 17.2.3 Module Stop Control Register (MSTPCR) ....................558 17.3 Operation ..................................559 Section 18 RAM..........................561 18.1 Overview................................... 561 18.1.1 Block Diagram ............................561 18.1.2 Register Configuration ..........................561 18.2 Register Descriptions..............................562 18.2.1 System Control Register (SYSCR) ......................562 18.3 Operation ..................................562 18.4 Usage Note ................................
Page 24 19.10.3 Error Protection ............................599 19.11 Flash Memory Emulation in RAM........................... 601 19.11.1 Emulation in RAM ............................601 19.11.2 RAM Overlap ..............................602 19.12 Interrupt Handling when Programming/Erasing Flash Memory ................603 19.13 Flash Memory Programmer Mode ........................... 604 19.13.1 Programmer Mode Setting ..........................604 19.13.2 Socket Adapters and Memory Map......................
Page 25 19.22.2 Socket Adapters and Memory Map......................648 19.22.3 Programmer Mode Operation........................650 19.22.4 Memory Read Mode............................651 19.22.5 Auto-Program Mode ........................... 653 19.22.6 Auto-Erase Mode............................655 19.22.7 Status Read Mode............................656 19.22.8 Status Polling............................... 657 19.22.9 Programmer Mode Transition Time......................657 19.22.10 Notes on Memory Programming ....................... 658 19.23 Flash Memory Programming and Erasing Precautions ....................658 Section 20 Clock Pulse Generator ....................661 20.1 Overview...................................
Page 26 22.1.3 AC Characteristics............................684 22.1.4 A/D Conversion Characteristics ........................701 22.1.5 D/A Conversion Characteristics ........................702 22.2 Usage Note (Internal Voltage Step Down for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390) ....702 22.3 Electrical Characteristics of H8S/2398 F-ZTAT......................703 22.3.1 Absolute Maximum Ratings........................703 22.3.2 DC Characteristics............................
Page 27 C.12 Port F Block Diagram............................... 996 C.13 Port G Block Diagram ............................1004 Appendix D Pin States ........................1007 Port States in Each Mode ............................1007 Appendix E Pin States at Power-On ....................1011 When Pins Settle from an Indeterminate State at Power-On ................. 1011 When Pins Settle from the High-Impedance State at Power-On................1012 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode......1013 Timing of Transition to Hardware Standby Mode ....................
Page 28 Rev.6.00 Oct.28.2004 page xxiv of xxiv REJ09B0138-0600H...
Page 29: Section 1 Overview
The H8S/2357 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Page 30 Table 1-1 Overview Item Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 50 ns 16 ×...
Page 31 Item Specification • 6-channel 16-bit timer on-chip 16-bit timer-pulse • unit (TPU) Pulse I/O processing capability for up to 16 pins • Automatic 2-phase encoder count capability • Maximum 16-bit pulse output possible with TPU as time base Programmable • pulse generator Output trigger selectable in 4-bit groups (PPG)
Page 32 Item Specification • Nine external interrupt pins (NMI, IRQ0 to IRQ7) Interrupt controller • 52 internal interrupt sources • Eight priority levels settable • Medium-speed mode Power-down state • Sleep mode • Module stop mode • Software standby mode • Hardware standby mode •...
Page 33 Item Specification • Four MCU operating modes (H8S/2398 F-ZTAT, masked ROM, ROMless, and Operating modes ZTAT) External Data Bus Operating On-Chip Initial Maximum Mode Mode Description Value Value — — — — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode On-chip ROM disabled...
Page 34: Block Diagram
Block Diagram Figure 1-1 shows an internal block diagram of the H8S/2357 Group. Port D Port E / IRQ7 / IRQ6 / IRQ5 / IRQ4 Port EXTAL XTAL STBY H8S/2000 CPU WDTOVF (FWE, V Port Interrupt controller / ø / AS DMAC ROM * / RD...
Page 35: Pin Description
Pin Description 1.3.1 Pin Arrangement Figures 1-2 and 1-3 show the pin arrangement for the H8S/2357, H8S/2352 and figures 1-4 and 1-5 show the pin arrangements for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390. / DREQ0 / CS4 SCK2 / P5 ADTRG / P5 / SCK1 / SCK0...
Page 36 / SCK1 / SCK0 AN0 / P4 / RxD1 AN1 / P4 / RxD0 AN2 / P4 / TxD1 AN3 / P4 / TxD0 AN4 / P4 AN5 / P4 DA0 / AN6 / P4 DA1 / AN7 / P4 TCLKD / TIOCB2 / PO15 / P1 TIOCA2 / PO14 / P1 TCLKC / TIOCB1 / PO13 / P1...
Page 37 / DREQ0 / CS4 SCK2 / P5 ADTRG / P5 / SCK1 / SCK0 AN0 / P4 / RxD1 AN1 / P4 / RxD0 AN2 / P4 / TxD1 AN3 / P4 / TxD0 AN4 / P4 AN5 / P4 DA0 / AN6 / P4 DA1 / AN7 / P4 TCLKD / TIOCB2 / PO15 / P1...
Page 38 / SCK1 / SCK0 AN0 / P4 / RxD1 AN1 / P4 / RxD0 AN2 / P4 / TxD1 AN3 / P4 / TxD0 AN4 / P4 AN5 / P4 DA0 / AN6 / P4 DA1 / AN7 / P4 TCLKD / TIOCB2 / PO15 / P1 TIOCA2 / PO14 / P1 TCLKC / TIOCB1 / PO13 / P1...
Page 39: Pin Functions In Each Operating Mode
1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2357 Group in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. Pin Name Flash Memory PROM Programmer TFP-120 FP-128B Mode 4* Mode 5*...
Page 40 Pin No. Pin Name Flash PROM Memory TFP-120 FP-128B Mode 4* Mode 5* Mode 6 Mode 7 Mode Programmer Mode /IRQ1 /IRQ1 /IRQ1 /IRQ1 /IRQ0 /IRQ0 /IRQ0 /IRQ0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 /TxD0 /TxD0 /TxD0 /TxD0 /TxD1 /TxD1 /TxD1...
Page 41 Pin No. Pin Name Flash PROM Memory TFP-120 FP-128B Mode 4* Mode 5* Mode 6 Mode 7 Mode Programmer Mode /PO5/ /PO5/ /PO5/ /PO5/ TIOCB4/ TIOCB4/ TIOCB4/ TIOCB4/ TMCI TMCI TMCI TMCI /PO4/ /PO4/ /PO4/ /PO4/ TIOCA4/ TIOCA4/ TIOCA4/ TIOCA4/ TMRI TMRI TMRI...
Page 42 Pin No. Pin Name Flash PROM Memory TFP-120 FP-128B Mode 4* Mode 5* Mode 6 Mode 7 Mode Programmer Mode /AN2 /AN2 /AN2 /AN2 /AN3 /AN3 /AN3 /AN3 /AN4 /AN4 /AN4 /AN4 /AN5 /AN5 /AN5 /AN5 /AN6/ /AN6/ /AN6/ /AN6/ /AN7/ /AN7/ /AN7/...
Page 43: Pin Functions
1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2357 Group. Table 1-3 Pin Functions Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Power 81, 76, 89, 84, Input Power supply: For connection to the 52, 33, 58, 39, power supply.
Page 44 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Operating mode 115 to 125 to Input Mode pins: These pins set the control operating mode. The relation between the settings of pins MD to MD and the operating mode is shown below. These pins should not be changed while the H8S/2357 Group is operating.
Page 45 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Address bus 28 to 25, 32 to 29, Output Address bus: These pins output an 23 to 16, 27 to 20, address. 14 to 7, 18 to 11, 5 to 2 9 to 6 Data bus 51 to 48,...
Page 46 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function 16-bit timer- TCLKD to 110, 109, 120, 119, Input Clock input D to A: These pins input pulse unit TCLKA 107, 105 117, 115 an external clock. (TPU) TIOCA0, 112 to 122 to Input capture/ output compare TIOCB0,...
Page 47 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function A/D converter AN7 to 102 to 112 to Input Analog 7 to 0: Analog input pins. ADTRG Input A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. D/A converter DA1, DA0 102, 101...
Page 48 Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function I/O ports 19 to 16, 23 to 20, Port B* : An 8-bit I/O port. Input or 14 to 11 18 to 15 output can be designated for each bit by means of the port B data direction register (PBDDR).
Page 49: Section 2 Cpu
Section 2 CPU Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features.
Page 50: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU.
Page 51: Differences From H8/300H Cpu
2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. • Additional control register  One 8-bit control register has been added. • Enhanced instructions  Addressing modes of bit-manipulation instructions have been enhanced. ...
Page 52 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-1).
Page 53 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
Page 54: Address Space
Address Space Figure 2-3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16- Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2357 Group H'FFFFFFFF...
Page 55: Register Configuration
Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR) 7 6 5 4 3 2 1 0 T —...
Page 56: Control Registers
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-5 illustrates the usage of the general registers. The usage of each register can be selected independently. •...
Page 57: Initial Register Values
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC.
Page 58: Data Formats
Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal- adjust instructions treat byte data as two digits of 4-bit BCD data.
Page 59 Data Type Register Number Data Format Word data Word data Longword data Legend: ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (cont) Rev.6.00 Oct.28.2004 page 31 of 1016 REJ09B0138-0600H...
Page 60: Memory Data Formats
2.5.2 Memory Data Formats Figure 2-8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 61: Instruction Set
Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Size Types Data transfer POP* , PUSH* LDM, STM MOVFPE, MOVTPE* Arithmetic ADD, SUB, CMP, NEG operations ADDX, SUBX, DAA, DAS INC, DEC...
Page 62: Instructions And Addressing Modes
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes Addressing Modes Function Instruction Data — — — — — transfer POP, PUSH —...
Page 63: Table Of Instructions Classified By Function
2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) (EAd) Destination operand (EAs) Source operand...
Page 64 Table 2-3 Instructions Classified by Function Type Instruction Size* Function (EAs) → Rd, Rs → (Ead) Data transfer B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2357 Group.
Page 65 Type Instruction Size* Function Rd ÷ Rs → Rd Arithmetic DIVXU operations Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.
Page 66 Type Instruction Size* Function 1 → (<bit-No.> of <EAd>) Bit- BSET manipulation Sets a specified bit in a general register or memory instructions operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 67 Type Instruction Size* Function C → (<bit-No.> of <EAd>) Bit- manipulation Transfers the carry flag value to a specified bit in a instructions general register or memory operand. ¬ C → (<bit-No.> of <EAd>) BIST Transfers the inverse of the carry flag value to a specified bit in a general register or memory operand.
Page 68 Type Instruction Size* Function CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR System control ANDC instructions Logically ANDs the CCR or EXR contents with immediate data. CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR Logically ORs the CCR or EXR contents with immediate data.
Page 69: Basic Instruction Formats
2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2-9 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc.
Page 70 Table 2-4 Addressing Modes Addressing Mode Symbol Register direct Register indirect @ERn Register indirect with displacement @(d:16,ERn)/@(d:32,ERn) Register indirect with post-increment @ERn+ Register indirect with pre-decrement @–ERn Absolute address @aa:8/@aa:16/@aa:24/@aa:32 Immediate #xx:8/#xx:16/#xx:32 Program-counter relative @(d:8,PC)/@(d:16,PC) Memory indirect @@aa:8 (1) Register Direct—Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand.
Page 71 Table 2-5 Absolute Address Access Ranges Absolute Address Advanced Mode Data address 8 bits (@aa:8) H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction address 24 bits (@aa:24) (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand.
Page 72: Effective Address Calculation
2.7.2 Effective Address Calculation Table 2-6 indicates how effective addresses are calculated in each addressing mode. Table 2-6 Effective Address Calculation Rev.6.00 Oct.28.2004 page 44 of 1016 REJ09B0138-0600H...
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Page 75: Processing States
Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-11 shows a diagram of the processing states. Figure 2-12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
Page 76: Reset State
End of bus request Bus request Program execution state End of bus SLEEP request instruction with request SLEEP SSBY = 0 instruction with SSBY = 1 Bus-released state Request for End of exception exception handling Sleep mode handling Interrupt request Exception-handling state External interrupt Software standby mode...
Page 77 Table 2-7 Exception Handling Types and Priority Priority Type of Exception Detection Timing Start of Exception Handling High Reset Synchronized with clock Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. Trace End of instruction When the trace (T) bit is set to...
Page 78: Program Execution State
Figure 2-13 shows the stack after exception handling ends. Advanced mode Reserved* (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Note: *Ignored when returning. Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence.
Page 79: Basic Timing
(3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. Basic Timing 2.9.1 Overview...
Page 80: On-Chip Supporting Module Access Timing
Bus cycle ø Address bus Unchanged High High HWR, LWR High Data bus High-impedance state Figure 2-15 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed.
Page 81: External Address Space Access Timing
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
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Page 83: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection (H8S/2357 F-ZTAT Only) The H8S/2357 F-ZTAT has eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD to MD ) and flash write enable pin (FWE) settings.
Page 84: Operating Mode Selection (Ztat, Masked Rom, Romless Version, And H8S/2398 F-Ztat)
The H8S/2357 F-ZTAT can only be used in modes 4 to 7, 10, 11, 14, and 15. This means that the flash write enable pin and mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Operating Mode Selection (ZTAT, Masked ROM, ROMless Version, and H8S/2398 F-ZTAT) The H8S/2357 Group has four operating modes (modes 4 to 7).
Page 85: Register Configuration
3.1.3 Register Configuration The H8S/2357 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD to MD ), and a system control register (SYSCR) and a system control register 2 (SYSCR2)* that control the operation of the H8S/2357 Group.
Page 86: System Control Register 2 (Syscr2) (F-Ztat Version Only)
Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit cannot be modified and is always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller.
Page 87 Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details, see section 19, ROM. Bit 3 FLSHE Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
Page 88: Operating Mode Descriptions
Operating Mode Descriptions 3.3.1 Mode 1 Mode 1 is not supported in this LSI, and must not be set. 3.3.2 Mode 2 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. MCU operation is the same as in mode 6. 3.3.3 Mode 3 (H8S/2398 F-ZTAT Only) This is a flash memory boot mode.
Page 89: Mode 7 (Single-Chip Mode)
3.3.7 Mode 7 (Single-Chip Mode) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 3.3.8 Modes 8 and 9 Modes 8 and 9 are not supported in the H8S/2357 Group, and must not be set.
Page 90: Pin Functions In Each Operating Mode
Pin Functions in Each Operating Mode The pin functions of ports A to F vary depending on the operating mode. Table 3-4 shows their functions in each operating mode. Table 3-4 Pin Functions in Each Mode Mode Mode Mode Mode Mode Mode Mode...
Page 91 Modes 4 and 5* Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF External address H'010000 H'010000 space On-chip ROM/ On-chip ROM/ external address reserved area...
Page 92 Mode 10* Boot Mode Mode 11* Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved area space H'01FFFF H'020000 External address space H'FFDC00 H'FFDC00 On-chip RAM...
Page 93 Mode 14* User Program Mode Mode 15* User Program Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved area space H'01FFFF H'020000 External address space H'FFDC00 H'FFDC00...
Page 94 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 Reserved space H'FFEC00 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. This is a reserved space. Access to this space is inhibited. The space can be made available for use as an external address space by clearing the RAME bit of the SYSCR to 0.
Page 95 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-3 Memory Map in Each Operating Mode (H8S/2392) Rev.6.00 Oct.28.2004 page 67 of 1016 REJ09B0138-0600H...
Page 96 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FF7C00 On-chip RAM External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-4 Memory Map in Each Operating Mode (H8S/2394) Rev.6.00 Oct.28.2004 page 68 of 1016 REJ09B0138-0600H...
Page 97 Mode 2 Mode 3 (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address *2*4 reserved area space H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip RAM On-chip RAM H'FFFBFF External address...
Page 98 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF External address H'010000 H'010000 space On-chip ROM/ On-chip ROM/ external address *2*4...
Page 99: Section 4 Exception Handling
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 100: Exception Handling Operation
4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3.
Page 101 Table 4-2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Power-on reset H'0000 to H'0003 Manual reset* H'0004 to H'0007 Reserved for system use H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Reserved for system use H'0018 to H'001B External interrupt...
Page 102: Reset
Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2357 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set.
Page 103: Reset Sequence
4.2.3 Reset Sequence The H8S/2357 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2357 Group is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2357 Group during operation, hold the RES pin low for at least 20 states.
Page 104: Interrupts After Reset
4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Page 105: Interrupts
Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), and A/D converter.
Page 106: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
Page 107: Notes On Use Of The Stack
Notes on Use of the Stack When accessing word data or longword data, the H8S/2357 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even.
Page 108 Rev.6.00 Oct.28.2004 page 80 of 1016 REJ09B0138-0600H...
Page 109: Section 5 Interrupt Controller
Section 5 Interrupt Controller Overview 5.1.1 Features The H8S/2357 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
Page 110: Block Diagram
5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1, INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to TEI Interrupt controller Legend:...
Page 111: Register Configuration
5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Interrupt Controller Registers Name Abbreviation Initial Value Address* System control register SYSCR H'01 H'FF39 IRQ sense control register H ISCRH H'00 H'FF2C IRQ sense control register L ISCRL H'00 H'FF2D...
Page 112: Interrupt Priority Registers A To K (Ipra To Iprk)
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 Bit 4 Interrupt INTM1 INTM0 Control Mode Description Interrupts are controlled by I bit (Initial value) —...
Page 113: Irq Enable Register (Ier)
Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ4 IRQ3 IRQ5 IPRC IRQ6 IRQ7 IPRD Watchdog timer Refresh timer IPRE —* A/D converter IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2...
Page 114: Irq Sense Control Registers H And L (Iscrh, Iscrl)
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
Page 115: Interrupt Sources
Bit n IRQnF Description [Clearing conditions] (Initial value) • Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag • When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high •...
Page 116: Internal Interrupts
IRQnE IRQnSCA, IRQnSCB IRQnF IRQn interrupt Edge/level detection circuit request IRQn input Clear signal Note: n=7 to 0 Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Page 117 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority External H'001C — High IRQ0 H'0040 IPRA6 to 4 IRQ1 H'0044 IPRA2 to 0 IRQ2 H'0048 IPRB6 to 4 IRQ3 H'004C IRQ4...
Page 118 Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority TGI3A (TGR3A input capture/ H'00C0 IPRG2 to 0 High compare match) channel 3 TGI3B (TGR3B input capture/ H'00C4 compare match) TGI3C (TGR3C input capture/ H'00C8 compare match) TGI3D (TGR3D input capture/ H'00CC compare match)
Page 119: Interrupt Operation
Vector Address* Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority ERI0 (receive error 0) H'0140 IPRJ2 to 0 High channel 0 RXI0 (reception data full 0) H'0144 TXI0 (transmit data empty 0) H'0148 TEI0 (transmission end 0) H'014C ERI1 (receive error 1) H'0150...
Page 120 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Page 121: Interrupt Control Mode 0
(3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated.
Page 122 Program execution status Interrupt generated? Hold pending IRQ0 IRQ1 TEI2 Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.6.00 Oct.28.2004 page 94 of 1016 REJ09B0138-0600H...
Page 123: Interrupt Control Mode 2
5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Page 124 Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0 Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2...
Page 125: Interrupt Exception Handling Sequence
5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling Rev.6.00 Oct.28.2004 page 97 of 1016 REJ09B0138-0600H...
Page 126: Interrupt Response Times
5.4.5 Interrupt Response Times The H8S/2357 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.
Page 127: Usage Notes
Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 128: Times When Interrupts Are Disabled
5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
Page 129: Block Diagram
5.6.2 Block Diagram Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller. DMAC DTC activation Interrupt request vector request Selection number circuit interrupt Select signal Control logic Clear signal DTCER Interrupt source On-chip Clear signal clear signal supporting module DTVECR...
Page 130: Note On Use
If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCERA to DTCERF in the DTC and the DISEL bit of MRB in the DTC.
Page 131: Section 6 Bus Controller
Section 6 Bus Controller Overview The H8S/2357 Group has a on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 132 • Other features  Refresh counter (refresh timer) can be used as an interval timer  External bus release function Rev.6.00 Oct.28.2004 page 104 of 1016 REJ09B0138-0600H...
Page 133: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Bus controller Internal control BREQO signals Bus mode signal Wait controller WAIT WCRH...
Page 134: Pin Configuration
6.1.3 Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Symbol I/O Function Address strobe Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.
Page 135: Register Configuration
6.1.4 Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Initial Value Power-On Manual Name Abbreviation Reset Reset* Address* Bus width control register ABWCR H'FF/H'00* Retained H'FED0 Access state control register ASTCR H'FF Retained H'FED1 Wait control register H...
Page 136: Register Descriptions
Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space.
Page 137: Access State Control Register (Astcr)
6.2.2 Access State Control Register (ASTCR) AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
Page 138: Wait Control Registers H And L (Wcrh, Wcrl)
6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode.
Page 139 Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...
Page 140 Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 Bit 4 Description Program wait not inserted when external space area 2 is accessed...
Page 141: Bus Control Register H (Bcrh)
6.2.4 Bus Control Register H (BCRH) ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 Initial value : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode.
Page 142: Bus Control Register L (Bcrl)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description Max. 4 words in burst access (Initial value) Max. 8 words in burst access Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode.
Page 143 Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated.
Page 144: Memory Control Register (Mcr)
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. (Initial value) Wait input by WAIT pin enabled 6.2.6 Memory Control Register (MCR) RCDM...
Page 145 Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 Description 16-bit DRAM space selected (Initial value) 8-bit DRAM space selected Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface.
Page 146: Dram Control Register (Dramcr)
6.2.7 DRAM Control Register (DRAMCR) RFSHE RMODE CMIE CKS2 CKS1 CKS0 Initial value : DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in software standby mode.
Page 147: Refresh Timer/Counter (Rtcnt)
Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0. Bit 3 CMIE Description...
Page 148: Refresh Time Constant Register (Rtcor)
6.2.9 Refresh Time Constant Register (RTCOR) Initial value : RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00.
Page 149: Overview Of Bus Control
Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6-2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area.
Page 150: Bus Specifications
6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 151: Memory Interfaces
6.3.3 Memory Interfaces The H8S/2357 Group memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM.
Page 152: Chip Select Signals
6.3.5 Chip Select Signals The H8S/2357 Group can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6-3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin.
Page 153: Basic Bus Interface
Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D ) or lower data bus...
Page 154 16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D to D ) and lower data bus (D to D ) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.
Page 155: Valid Strobes
6.4.3 Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6-4 Data Buses Used and Valid Strobes Access...
Page 156: Basic Timing
6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D to D ) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...
Page 157 8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D to D ) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...
Page 158 16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D to D ) of the data bus is used for the even address, and the lower half (D ) for the odd address.
Page 159 Bus cycle ø Address bus to D Invalid Read to D Valid High Write High impedance to D to D Valid Note: n = 0 to 7 Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Oct.28.2004 page 131 of 1016 REJ09B0138-0600H...
Page 160 Bus cycle ø Address bus to D Valid Read to D Valid Write to D Valid to D Valid Note: n = 0 to 7 Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.6.00 Oct.28.2004 page 132 of 1016 REJ09B0138-0600H...
Page 161 16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D to D ) of the data bus is used for the even address, and the lower half (D ) for the odd address.
Page 162 Bus cycle ø Address bus to D Invalid Read to D Valid High Write High impedance to D to D Valid Note: n = 0 to 7 Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Oct.28.2004 page 134 of 1016 REJ09B0138-0600H...
Page 163 Bus cycle ø Address bus to D Valid Read to D Valid Write to D Valid to D Valid Note: n = 0 to 7 Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.6.00 Oct.28.2004 page 135 of 1016 REJ09B0138-0600H...
Page 164: Wait Control
6.4.5 Wait Control When accessing external space, the H8S/2357 Group can extend the bus cycle by inserting one or more wait states (T There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T state and T state on an...
Page 165 Figure 6-14 shows an example of wait state insertion timing. By program wait By WAIT pin ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled.
Page 166: Dram Interface
DRAM Interface 6.5.1 Overview When the H8S/2357 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2357 Group. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH.
Page 167: Pins Used For Dram Interface
6.5.5 Pins Used for DRAM Interface Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins With DRAM Setting Name Function Write enable Output When 2-CAS system is set, write enable for DRAM space access.
Page 168: Basic Timing
6.5.6 Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states.
Page 169: Precharge State Control
6.5.7 Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one T state is always inserted when DRAM space is accessed. This can be changed to two T states by setting the TPC bit in MCR to 1. Set the appropriate number of T cycles according to the DRAM connected and the operating frequency of the H8S/2357 Group.
Page 170 Figure 6-17 shows an example of wait state insertion timing. By program wait By WAIT pin ø WAIT Address bus C Sn, (RAS) Read Data bus Read data Write Data bus Write data indicates the timing of WAIT pin sampling. Notes: n = 2 to 5 Figure 6-17 Example of Wait State Insertion Timing (CW2 = 1, 8-Bit Area Setting for Entire Space)
Page 171: Byte Access Control
6.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2- CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection.
Page 172: Burst Operation
6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address.
Page 173 RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again.
Page 174 • RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous.
Page 175: Refresh Control
6.5.11 Refresh Control The H8S/2357 Group is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.
Page 176 ø CS, (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6-25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0.
Page 177: Dmac Single Address Mode And Dram Interface
Software standby ø CSn, (RAS) CAS, LCAS HWR, (WE) High Note: n = 2 to 5 Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0) DMAC Single Address Mode and DRAM Interface When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed is selected.
Page 178: When Dds = 0
6.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the T state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0.
Page 179: Basic Timing
6.7.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH.
Page 180: Wait Control
Full access Burst access ø Only lower address changed Address bus Data bus Read data Read data Read data Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.
Page 181: Idle Cycle
Idle Cycle 6.8.1 Operation When the H8S/2357 Group accesses external space, it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle.
Page 182 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 183: Usage Notes
(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6- In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
Page 184 External read DRAM space read ø Address bus Data bus Figure 6-34 Example of DRAM Access after External Read DRAM space read External read DRAM space read EXTAL Address CAS, LCAS Data bus Idle cycle Figure 6-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) DRAM space read External read DRAM space write...
Page 185: Pin States In Idle Cycle
6.8.3 Pin States in Idle Cycle Table 6-8 shows pin states in an idle cycle. Table 6-8 Pin States in Idle Cycle Pins Pin State to A Contents of next bus cycle to D High impedance CSn* High* High High High High High...
Page 186: Write Data Buffer Function
Write Data Buffer Function The H8S/2357 Group has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1.
Page 187: Bus Release
6.10 Bus Release 6.10.1 Overview The H8S/2357 Group can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is generated, it can issue a bus request off-chip.
Page 188: Pin States In External Bus Released State
6.10.3 Pin States in External Bus Released State Table 6-9 shows pin states in the external bus released state. Table 6-9 Pin States in Bus Released State Pins Pin State to A High impedance to D High impedance CSn* High impedance High impedance High impedance High impedance...
Page 189: Transition Timing
6.10.4 Transition Timing Figure 6-37 shows the timing for transition to the bus-released state. cycle CPU cycle External bus released state ø High impedance Address bus Address High impedance Data bus High impedance High impedance High impedance HWR, LWR BREQ BACK BREQO * Minimum...
Page 190: Bus Arbitration
6.11 Bus Arbitration 6.11.1 Overview The H8S/2357 Group has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
Page 191: Bus Transfer Timing
6.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus.
Page 192: Resets And The Bus Controller
6.12 Resets and the Bus Controller In a power-on reset, the H8S/2357 Group, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset*, the bus controller’s registers and internal state are maintained, and an executing external bus cycle is completed.
Page 193: Section 7 Dma Controller
Section 7 DMA Controller Overview The H8S/2357 Group has a on-chip DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1.1 Features The features of the DMAC are listed below. • Choice of short address mode or full address mode Short address mode ...
Page 194: Block Diagram
7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7-1. Internal address bus Internal interrupts TGI0A Address buffer TGI1A TGI2A Processor TGI3A TGI4A TGI5A MAR0A TXI0 IOAR0A RXI0 Control logic TXI1 ETCR0A RXI1 MAR0B External pins IOAR0B DREQ0 ETCR0B...
Page 195: Overview Of Functions
7.1.3 Overview of Functions Tables 7-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7-1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination •...
Page 196 Table 7-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination • • Normal mode Auto-request Auto-request  Transfer request retained internally  Transfers continue for the specified number of times (1 to 65,536) ...
Page 197: Pin Configuration
7.1.4 Pin Configuration Table 7-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output.
Page 198: Register Configuration
7.1.5 Register Configuration Table 7-3 summarizes the DMAC registers. Table 7-3 DMAC Registers Initial Channel Name Abbreviation R/W Value Address* Bus Width Memory address register 0A MAR0A Undefined H'FEE0 16 bits I/O address register 0A IOAR0A Undefined H'FEE4 16 bits Transfer count register 0A ETCR0A Undefined H'FEE6...
Page 199: Register Descriptions (1) (Short Address Mode)
Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0.
Page 200: Memory Address Registers (Mar)
7.2.1 Memory Address Registers (MAR) — — — — — — — — Initial value : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address.
Page 201: Execute Transfer Count Register (Etcr)
7.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode Transfer Counter ETCR...
Page 202: Dma Control Register (Dmacr)
7.2.4 DMA Control Register (DMACR) DMACR DTSZ DTID5 DTDIR DTF3 DTF2 DTF1 DTF0 Initial value : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in hardware standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Page 203 Bit 4—Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR Bit 4 DTDIR Description...
Page 204 Channel B Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt Activated by SCI channel 1 transmission data empty...
Page 205: Dma Band Control Register (Dmabcr)
7.2.5 DMA Band Control Register (DMABCR) DMABCRH : FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value : DMABCRL : DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Initial value : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in hardware standby mode.
Page 206 Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. Bit 12 SAE0 Description Transfer in dual address mode (Initial value) Transfer in single address mode This bit is invalid in full address mode.
Page 207 Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bits 7 to 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by...
Page 208 Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A Description Data transfer disabled (Initial value) Data transfer enabled Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
Page 209: Register Descriptions (2) (Full Address Mode)
Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7-4. 7.3.1 Memory Address Register (MAR) — — — — — — — —...
Page 210 (1) Normal Mode ETCRA Transfer Counter ETCR Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000.
Page 211: Dma Control Register (Dmacr)
7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in hardware standby mode. DMACRA DMACRA : DTSZ...
Page 212 Bit 11—Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 Bit 11 BLKDIR...
Page 213 • Block Transfer Mode Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission data empty interrupt Activated by SCI channel 0 reception data full interrupt...
Page 214: Dma Band Control Register (Dmabcr)
7.3.5 DMA Band Control Register (DMABCR) DMABCRH : FAE1 FAE0 — — DTA1 — DTA0 — Initial value : DMABCRL : DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode.
Page 215 Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Page 216 Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 Description...
Page 217 Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC.
Page 218: Register Descriptions (3)
Register Descriptions (3) 7.4.1 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned.
Page 219 Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0. Bit 3—Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC. Bit 3 WE1B Description...
Page 220: Dma Terminal Control Register (Dmatcr)
7.4.2 DMA Terminal Control Register (DMATCR) DMATCR : — — TEE1 TEE0 — — — — Initial value : — — — — — — DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
Page 221: Module Stop Control Register (Mstpcr)
7.4.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 222: Operation
Operation 7.5.1 Transfer Modes Table 7-5 lists the DMAC modes. Table 7-5 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual (1) Sequential mode TPU channel 0 to 5 Up to 4 channels can address address compare match/input operate independently (2) Idle mode mode...
Page 223 Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed.
Page 224: Sequential Mode
7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
Page 225 Figure 7-3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend: Address T = L DTID DTSZ Address B = L + (–1) • (2 • (N–1)) Where : L = Value set in MAR Address B N = Value set in ETCR...
Page 226 Figure 7-4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. Sequential mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 227: Idle Mode
7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
Page 228 The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
Page 229: Repeat Mode
7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR.
Page 230 The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared.
Page 231 Figure 7-8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. Repeat mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 232: Single Address Mode
7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR.
Page 233 Figure 7-9 illustrates operation in single address mode (when sequential mode is specified). DACK Address T Transfer 1 byte or word transfer performed in response to 1 transfer request Legend: Address T = L DTID DTSZ Address B = L + (–1) •...
Page 234 Figure 7-10 shows an example of the setting procedure for single address mode (when sequential mode is specified). [1] Set each bit in DMABCRH. Single address • Clear the FAE bit to 0 to select short address mode setting mode. •...
Page 235: Normal Mode
7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA.
Page 236 Figure 7-11 illustrates operation in normal mode. Address T Transfer Address T Address B Address B Legend: Address Address SAID DTSZ Address + SAIDE • (–1) • (2 • (N–1)) DAID DTSZ Address + DAIDE • (–1) • (2 • (N–1)) Where : = Value set in MARA = Value set in MARB...
Page 237 For setting details, see section 7.3.4, DMA Controller Register (DMACR). Figure 7-12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. Normal mode setting • Set the FAE bit to 1 to select full address mode.
Page 238: Block Transfer Mode
7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times.
Page 239 Address T Address T 1st block Block area Transfer Address B Consecutive transfer of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend: Address Address SAID DTSZ Address + SAIDE • (–1) •...
Page 240 Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area. Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in response to one request 2nd block Nth block...
Page 241 Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID DTSZ MARA = MARA + SAIDE·(–1) ·2 Write to address specified by MARB DAID DTSZ MARB = MARB + DAIDE·(–1) ·2 ETCRAL = ETCRAL–1 ETCRAL = H'00 Release bus ETCRAL = ETCRAH...
Page 242 [1] Set each bit in DMABCRH. Block transfer • Set the FAE bit to 1 to select full address mode setting mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address in MARA, and the transfer destination address in MARB.
Page 243: Dmac Activation Sources
7.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7-12. Table 7-12 DMAC Activation Sources Short Address Mode Full Address Mode Block...
Page 244 Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin.
Page 245: Basic Dmac Bus Cycles
When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a read strobe for the external device.
Page 246: Dmac Bus Cycles (Dual Address Mode)
7.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
Page 247 Full Address Mode (Cycle Steal Mode): Figure 7-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. read write read...
Page 248 Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and word- size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2- state access space. read write read...
Page 249 Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. read write read...
Page 250 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-23 shows an example of DREQ pin falling edge activated normal mode transfer. Bus release read write release read write...
Page 251 Figure 7-24 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer 1 block transfer Bus release read write dead release read write dead release ø DREQ Transfer Transfer Transfer Transfer Address bus source destination source destination...
Page 252 DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to Figure 7-25 shows an example of DREQ level activated normal mode transfer. read write read write release release release ø...
Page 253 Figure 7-26 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer 1 block transfer Bus release read right dead release read right dead release ø DREQ Transfer Transfer Transfer Transfer Address bus source destination source destination DMA control Idle...
Page 254: Dmac Bus Cycles (Single Address Mode)
7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read...
Page 255 Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA write dead ø...
Page 256 In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-31 shows an example of DREQ pin falling edge activated single address mode transfer.
Page 257 DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-32 shows an example of DREQ pin low level activated single address mode transfer. Bus release DMA single Bus release DMA single release...
Page 258: Write Data Buffer Function
7.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Page 259: Dmac Multi-Channel Operation
read single read single read ø Internal address Internal read signal External address DACK Figure 7-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation.
Page 260: Relation Between External Bus Requests, Refresh Cycles, The Dtc, And The Dmac
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7-13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer.
Page 261: Nmi Interrupts And Dmac
7.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
Page 262: Forced Termination Of Dmac Operation
7.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit.
Page 263: Clearing Full Address Mode
7.5.17 Clearing Full Address Mode Figure 7-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and the DTME bit in Clearing full DMABCRL to 0;...
Page 264: Interrupts
Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7-14 shows the interrupt sources and their priority order. Table 7-14 Interrupt Source Priority Order Interrupt Source Interrupt Interrupt Name Short Address Mode Full Address Mode Priority Order DEND0A Interrupt due to end of...
Page 265: Usage Notes
Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Page 266 (b) DMAC registers are read as shown in figure 7-41, when the DMAC transfer cycle occurs immediately after the DMAC register has been read. CPU longword read DMA transfer cycle MAR lower MAR upper word read DMA read DMA write word read ø...
Page 267 (b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled.
Page 268 When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1.
Page 269: Section 8 Data Transfer Controller
Section 8 Data Transfer Controller Overview The H8S/2357 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: • Transfer possible over any number of channels ...
Page 270: Block Diagram
8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed.
Page 271: Register Configuration
8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 DTC Registers Name Abbreviation Initial Value Address* DTC mode register A —* Undefined —* DTC mode register B —* Undefined —* DTC source address register —* Undefined —* DTC destination address register —* Undefined —*...
Page 272: Register Descriptions
Register Descriptions 8.2.1 DTC Mode Register A (MRA) Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
Page 273: Dtc Mode Register B (Mrb)
Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0—DTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Page 274: Dtc Source Address Register (Sar)
8.2.3 DTC Source Address Register (SAR) – – – – – – Initial value : – – – Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined — — —...
Page 275: Dtc Enable Registers (Dtcer)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
Page 276: Module Stop Control Register (Mstpcr)
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1. Bit 7 SWDTE Description DTC software activation is disabled (Initial value) [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended...
Page 277: Operation
Operation 8.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
Page 278 Table 8-2 DTC Functions Address Registers Transfer Transfer Transfer Mode Activation Source Source Destination • • 24 bits 24 bits Normal mode  One transfer request transfers one byte or one • TPU TGI • word 8-bit timer CMI  Memory addresses are incremented or •...
Page 279: Activation Sources
8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
Page 280: Dtc Vector Table
8.3.3 DTC Vector Table Figure 8-4 shows the correspondence between DTC vector addresses and register information. Table 8-4 shows the correspondence between activation, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420.
Page 281 Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0]<<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424 DTCEA5...
Page 282 Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority TGI5B (GR5B compare match/ H'047A DTCED4 High input capture) channel 5 CMIA0 8-bit timer H'0480 DTCED3 channel 0 CMIB0 H'0482 DTCED2 CMIA1 8-bit timer H'0488 DTCED1 channel 1 CMIB1 H'048A DTCED0...
Page 283: Location Of Register Information In Address Space
DTC vector Register information Register information address start address Chain transfer Figure 8-4 Correspondence between DTC Vector Address and Register Information 8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address).
Page 284: Normal Mode
8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. Table 8-5 Register Information in Normal Mode Name...
Page 285: Repeat Mode
8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
Page 286: Block Transfer Mode
8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
Page 287: Chain Transfer
8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer.
Page 288: Operation Timing
8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. ø DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ø...
Page 289: Number Of Dtc Execution States
ø DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status.
Page 290: Procedures For Using Dtc
The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). + Σ (J · S Number of execution states = I ·...
Page 291 [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception data full (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts.
Page 292: Interrupts
[1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0).
Page 293: Section 9 I/O Ports
Section 9 I/O Ports Overview The H8S/2357 Group has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 9-1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Page 294 Table 9-1 Port Functions Port Description Pins Mode 4* Mode 5* Mode 6 Mode 7 Port 1 • 8-bit I/O /PO15/TIOCB2/TCLKD 8-bit I/O port also functioning as DMA controller output pins port (DACK0 and DACK1), TPU I/O pins (TCLKA, TCLKB, /PO14/TIOCA2 TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, /PO13/TIOCB1/TCLKC...
Page 295 Port Description Pins Mode 4* Mode 5* Mode 6 Mode 7 Port A • 8-bit I/O /IRQ7 When DDR = 0 (after reset): When DDR = Dual function port dual function as input ports 0 (after reset): as I/O ports /IRQ6 •...
Page 296 Port Description Pins Mode 4* Mode 5* Mode 6 Mode 7 Port F • 8-bit I/O /ø When DDR = 0: input port When DDR = port 0 (after reset): When DDR = 1 (after reset): ø output input port When DDR = 1: ø...
Page 297: Port1
Port 1 9.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1).
Page 298 Port 1 Data Direction Register (P1DDR) P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 299: Pin Functions
9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are shown in table 9-3. Table 9-3 Port 1 Pin Functions Selection Method and Pin Functions...
Page 300 Selection Method and Pin Functions /PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bit NDER14 in NDERH, and bit P16DDR.
Page 301 Selection Method and Pin Functions /PO13/TIOCB1/ The pin function is switched as shown below according to the combination of TCLKC the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
Page 302 Selection Method and Pin Functions /PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bit NDER12 in NDERH, and bit P14DDR.
Page 303 Selection Method and Pin Functions /PO11/TIOCD0/ The pin function is switched as shown below according to the combination of TCLKB the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.
Page 304 Selection Method and Pin Functions /PO10/TIOCC0/ The pin function is switched as shown below according to the combination of TCLKA the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
Page 305 Selection Method and Pin Functions /PO9/TIOCB0/ The pin function is switched as shown below according to the combination of DACK1 the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER9 in NDERH, bit SAE1 in DMABCRH, and bit P11DDR.
Page 306 Selection Method and Pin Functions /PO8/TIOCA0/ The pin function is switched as shown below according to the combination of DACK0 the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER8 in NDERH, bit SAE0 in DMABCRH, and bit P10DDR.
Page 307: Port2
Port 2 9.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0), TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1).
Page 308 P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. As the PPG, TPU, and 8-bit timer are initialized by a manual reset*, the pin states are determined by the P2DDR and P2DR specifications.
Page 309: Pin Functions
9.3.3 Pin Functions Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 9-5. Table 9-5 Port 2 Pin Functions Selection Method and Pin Functions...
Page 310 Selection Method and Pin Functions /PO6/TIOCA5/ The pin function is switched as shown below according to the combination of TMO0 the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER6 in NDERL, bits OS3 to OS0 in TCSR0, and bit P26DDR.
Page 311 Selection Method and Pin Functions /PO5/TIOCB4/ This pin is used as the 8-bit timer external clock input pin when external clock TMCI1 is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER5 in NDERL, and bit P25DDR.
Page 312 Selection Method and Pin Functions /PO4/TIOCA4/ This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and TMRI1 CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER4 in NDERL, and bit P24DDR.
Page 313 Selection Method and Pin Functions /PO3/TIOCD3/ This pin is used as the 8-bit timer external clock input pin when external clock TMCI0 is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER3 in NDERL, and bit P23DDR.
Page 314 Selection Method and Pin Functions /PO2/TIOCC3/ This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and TMRI0 CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER2 in NDERL, and bit P22DDR.
Page 315 Selection Method and Pin Functions /PO1/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER1 in NDERL, and bit P21DDR.
Page 316 Selection Method and Pin Functions /PO0/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER0 in NDERL, and bit P20DDR.
Page 317: Port 3
Port 3 9.4.1 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 9-3 shows the port 3 pin configuration. Port 3 pins (I/O)/ SCK1 (I/O)
Page 318 P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications.
Page 319: Pin Functions
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin.
Page 320 Selection Method and Pin Functions /RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. P33DDR — Pin function input pin output pin* RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. /RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR.
Page 321: Port 4
Port 4 9.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port 4 pin configuration.
Page 322: Port 5
Port 5 9.6.1 Overview Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2) and the A/D converter input pin (ADTRG). Port 5 pin functions are the same in all operating modes. Figure 9-5 shows the port 5 pin configuration. Port 5 pins (I/O)/ADTRG (input) (I/O)/SCK2 (I/O)
Page 323 Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port 5 Data Register (P5DR) — — — — P53DR P52DR P51DR P50DR Initial value : Undefined Undefined Undefined Undefined — — — — P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P5 to P5 Bits 7 to 4 are reserved;...
Page 324: Pin Functions
9.6.3 Pin Functions Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), and the A/D converter input pin (ADTRG). Port 5 pin functions are shown in table 9-10. Table 9-10 Port 5 Pin Functions Selection Method and Pin Functions /ADTRG The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D converter ADCR, and bit P53DDR.
Page 325: Port 6
Port 6 9.7.1 Overview Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). The functions of pins P6 to P6 are the same in all operating modes, while the functions of pins P6...
Page 326 Port 6 Data Direction Register (P6DDR) P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Page 327: Pin Functions
9.7.3 Pin Functions Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 9-12. Table 9-12 Port 6 Pin Functions Selection Method and Pin Functions /IRQ3/CS7...
Page 328 Selection Method and Pin Functions /TEND1 The pin function is switched as shown below according to the combination of bit TEE1 in the DMAC DMATCR, and bit P63DDR. TEE1 P63DDR — TEND1 output Pin function input pin output pin /DREQ1 The pin function is switched as shown below according to bit P62DDR.
Page 329: Port A
Port A 9.8.1 Overview Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. Port A has a on-chip MOS input pull-up function that can be controlled by software. Pins PA to PA are schmitt-triggered inputs.
Page 330: Register Configuration
9.8.2 Register Configuration Table 9-13 shows the port A register configuration. Table 9-13 Port A Registers Name Abbreviation Initial Value Address* Port A data direction register PADDR H'00 H'FEB9 Port A data register PADR H'00 H'FF69 Port A register PORTA Undefined H'FF59 Port A MOS pull-up control register*...
Page 331 Port A Data Register (PADR) PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value : PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA to PA PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode.
Page 332: Pin Functions
Port A Open Drain Control Register (PAODR) (On-Chip ROM Version Only) PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA to PA All bits are valid in mode 7.
Page 333 Mode 6 (On-Chip ROM Version Only): In mode 6, port A pins function as address outputs or input ports and interrupt input pins. Input or output can be specified on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port.
Page 334: Mos Input Pull-Up Function (On-Chip Rom Version Only)
9.8.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port A has a on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA to PA in modes 4 and 5, and by all pins in modes 6 and 7. MOS input pull-up can be specified as on or off on an individual bit basis.
Page 335: Port B
Port B 9.9.1 Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-11 shows the port B pin configuration.
Page 336: Register Configuration (On-Chip Rom Version Only)
9.9.2 Register Configuration (On-Chip ROM Version Only) Table 9-15 shows the port B register configuration. Table 9-15 Port B Registers Name Abbreviation Initial Value Address * Port B data direction register PBDDR H'00 H'FEBA Port B data register PBDR H'00 H'FF6A Port B register PORTB...
Page 337 Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port B Register (PORTB) (On-Chip ROM Version Only) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PB to PB PORTB is an 8-bit read-only register that shows the pin states.
Page 338: Pin Functions
9.9.3 Pin Functions Mode 7 (On-Chip ROM Version Only): In mode 7, port B pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port.
Page 339: Mos Input Pull-Up Function (On-Chip Rom Version Only)
Modes 4 and 5: In modes 4 and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 4 and 5 are shown in figure 9-14. (output) (output) (output) (output) Port B (output) (output) (output) (output) Figure 9-14 Port B Pin Functions (Modes 4 and 5)
Page 340: Port C
9.10 Port C 9.10.1 Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-15 shows the port C pin configuration.
Page 341: Register Configuration (On-Chip Rom Version Only)
9.10.2 Register Configuration (On-Chip ROM Version Only) Table 9-17 shows the port C register configuration. Table 9-17 Port C Registers Name Abbreviation Initial Value Address * Port C data direction register PCDDR H'00 H'FEBB Port C data register PCDR H'00 H'FF6B Port C register PORTC...
Page 342 Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port C Register (PORTC) (On-Chip ROM Version Only) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PC to PC PORTC is an 8-bit read-only register that shows the pin states.
Page 343: Pin Functions
9.10.3 Pin Functions Mode 7 (On-Chip ROM Version Only): In mode 7, port C pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port.
Page 344: Mos Input Pull-Up Function (On-Chip Rom Version Only)
Modes 4 and 5: In modes 4 and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 4 and 5 are shown in figure 9-18. (output) (output) (output) (output) Port C (output) (output) (output) (output) Figure 9-18 Port C Pin Functions (Modes 4 and 5)
Page 345: Port D
9.11 Port D 9.11.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. In the H8S/2352, port D pins are dedicated data bus pins. Port D has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only).
Page 346: Register Configuration (On-Chip Rom Version Only)
9.11.2 Register Configuration (On-Chip ROM Version Only) Table 9-19 shows the port D register configuration. Table 9-19 Port D Registers Name Abbreviation Initial Value Address * Port D data direction register PDDDR H'00 H'FEBC Port D data register PDDR H'00 H'FF6C Port D register PORTD...
Page 347 Port D Register (PORTD) (On-Chip ROM Version Only) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PD to PD PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD to PD ) must always be performed on PDDR.
Page 348: Pin Functions
9.11.3 Pin Functions Modes 7 (On-Chip ROM Version Only): In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.
Page 349: Mos Input Pull-Up Function (On-Chip Rom Version Only)
9.11.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port D has a on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin.
Page 350: Port E
9.12 Port E 9.12.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a on-chip MOS input pull-up function that can be controlled by software (on-chip ROM version only). Figure 9-22 shows the port E pin configuration.
Page 351: Register Configuration
9.12.2 Register Configuration Table 9-21 shows the port E register configuration. Table 9-21 Port E Registers Name Abbreviation Initial Value Address* Port E data direction register PEDDR H'00 H'FEBD Port E data register PEDR H'00 H'FF6D Port E register PORTE Undefined H'FF5D Port E MOS pull-up control register*...
Page 352 PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode. Note: * Manual reset is only supported in the H8S/2357 ZTAT. Port E Register (PORTE) Initial value : —* —*...
Page 353: Pin Functions
9.12.3 Pin Functions Mode 7*: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port.
Page 354: Mos Input Pull-Up Function (On-Chip Rom Version Only)
9.12.4 MOS Input Pull-Up Function (On-Chip ROM Version Only) Port E has a on-chip MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis.
Page 355: Port F
9.13 Port F 9.13.1 Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. Figure 9-25 shows the port F pin configuration.
Page 356: Register Configuration
9.13.2 Register Configuration Table 9-23 shows the port F register configuration. Table 9-23 Port F Registers Name Abbreviation Initial Value Address * Port F data direction register PFDDR H'80/H'00* H'FEBE Port F data register PFDR H'00 H'FF6E Port F register PORTF Undefined H'FF5E...
Page 357 Port F Data Register (PFDR) PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial value : PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF to PF PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset*, and in software standby mode.
Page 358: Pin Functions
9.13.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (ø) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9-24.
Page 359 Selection Method and Pin Functions /LCAS/WAIT/ The pin function is switched as shown below according to the combination of BREQO the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE, ABW5 to ABW2, and PF2DDR. Operating Mode Modes 4 to 6* Mode 7* LCASS —...
Page 360: Port G
9.14 Port G 9.14.1 Overview Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). Figure 9-26 shows the port G pin configuration. Port G pins Pin functions in mode 7* Pin functions in modes 4 to 6* (I/O) (input)/CS0 (output)
Page 361 Port G Data Direction Register (PGDDR) — — — PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Modes 6, 7 Initial value : Undefined Undefined Undefined — — — Modes 4, 5 Initial value : Undefined Undefined Undefined — — — PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved.
Page 362 Port G Register (PORTG) — — — Initial value : —* —* —* —* —* Undefined Undefined Undefined — — — Note: * Determined by state of pins PG to PG PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG to PG ) must always be performed on PGDR.
Page 363: Pin Functions
9.14.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). The pin functions are different in mode 7, and modes 4 to 6. Port G pin functions are shown in table 9-26. Table 9-26 Port G Pin Functions Selection Method and Pin Functions /CS0...
Page 364 Rev.6.00 Oct.28.2004 page 336 of 1016 REJ09B0138-0600H...
Page 365: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The H8S/2357 Group has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.1 Features • Maximum 16-pulse input/output  A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ...
Page 366 • A/D converter conversion start trigger can be generated  Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger • Module stop mode can be set  As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10-1 lists the functions of the TPU.
Page 367 Table 10-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock ø/1 ø/1 ø/1 ø/1 ø/1 ø/1 ø/4 ø/4 ø/4 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 ø/64 ø/64 ø/64...
Page 368 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC TGR0A TGR1A TGR2A TGR3A TGR4A TGR5A activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture...
Page 369: Block Diagram
10.1.2 Block Diagram Figure 10-1 shows a block diagram of the TPU. Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5...
Page 370: Pin Configuration
10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel Name Symbol Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase inputs) Clock input B TCLKB Input External clock B input pin...
Page 371: Register Configuration
10.1.4 Register Configuration Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name Abbreviation Initial Value Address * Timer control register 0 TCR0 H'00 H'FFD0 Timer mode register 0 TMDR0 H'C0 H'FFD1 Timer I/O control register 0H TIOR0H H'00 H'FFD2 Timer I/O control register 0L...
Page 372 Channel Name Abbreviation Initial Value Address* Timer control register 3 TCR3 H'00 H'FE80 Timer mode register 3 TMDR3 H'C0 H'FE81 Timer I/O control register 3H TIOR3H H'00 H'FE82 Timer I/O control register 3L TIOR3L H'00 H'FE83 Timer interrupt enable register 3 TIER3 H'40 H'FE84 Timer status register 3...
Page 373: Register Descriptions
10.2 Register Descriptions 10.2.1 Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2...
Page 374 Bits 7 to 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
Page 375 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Page 376 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on ø/256 Counts on TCNT2 overflow/underflow...
Page 377: Timer Mode Register (Tmdr)
Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on ø/1024 Counts on TCNT5 overflow/underflow...
Page 378 The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode.
Page 379: Timer I/O Control Register (Tior)
10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : Channel 0: TIOR0L Channel 3: TIOR3L IOD3 IOD2 IOD1...
Page 380 Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4...
Page 381 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 382 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR2B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 383 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR3D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 384 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR4B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 385 Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel...
Page 386 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 387 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR3A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 388 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR4A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 389: Timer Interrupt Enable Register (Tier)
10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : — — Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 TTGE — TCIEU TCIEV —...
Page 390 Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV Description Interrupt requests (TCIV) by TCFV disabled (Initial value) Interrupt requests (TCIV) by TCFV enabled Bit 3—TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3.
Page 391: Timer Status Register (Tsr)
10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 — — — TCFV TGFD TGFC TGFB TGFA Initial value : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Can only be written with 0 for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4...
Page 392 Bit 4—Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV Description [Clearing condition] (Initial value) When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3.
Page 393 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description [Clearing conditions] (Initial value) • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 •...
Page 394: Timer Counter (Tcnt)
10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel.
Page 395: Timer Synchro Register (Tsyr)
Bits 7 and 6—Reserved: Should always be written with 0. Bits 5 to 0—Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn Description TCNTn count operation is stopped (Initial value) TCNTn performs count operation n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the...
Page 396: Module Stop Control Register (Mstpcr)
10.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 397: Interface To Bus Master
10.3 Interface to Bus Master 10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2.
Page 398: 8-Bit Registers
10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. Examples of 8-bit register access operation are shown in figures 10-3 to 10-5.
Page 399: Operation
10.4 Operation 10.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.
Page 400: Basic Functions
10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure.
Page 401 • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 402 Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. • Example of setting procedure for waveform output by compare match Figure 10-9 shows an example of the setting procedure for waveform output by compare match [1] Select initial value 0 output or 1 output, and Output selection compare match output value 0 output, 1 output,...
Page 403 Figure 10-11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF...
Page 404 • Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 405: Synchronous Operation
10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Page 406 For details of PWM modes, see section 10.4.6, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A Time H'0000 TIOC0A TIOC1A TIOC2A Figure 10-15 Example of Synchronous Operation Rev.6.00 Oct.28.2004 page 378 of 1016 REJ09B0138-0600H...
Page 407: Buffer Operation
10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 408 Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or Buffer operation output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits Select TGR function BFA and BFB in TMDR.
Page 409 • When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 410: Cascaded Operation
10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Page 411: Pwm Modes
Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Page 412 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D.
Page 413 Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 414 Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.
Page 415 Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 416: Phase Counting Mode
10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 417 TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-29 Example of Phase Counting Mode 1 Operation Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKB (Channels 1 and 5) TCLKC (Channels 2 and 4)
Page 418 Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKB (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKD (Channels 2 and 4) Operation High level Don’t care Low level Don’t care Low level Don’t care High level Up-count...
Page 419 Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKB (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKD (Channels 2 and 4) Operation High level Don’t care Low level Don’t care Low level Don’t care High level Up-count...
Page 420 Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKB (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKD (Channels 2 and 4) Operation High level Up-count Low level Low level Don’t care High level High level Down-count Low level...
Page 421 Channel 1 TCLKA Edge TCNT1 detection circuit TCLKB TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) – TGR0C – (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example Rev.6.00 Oct.28.2004 page 393 of 1016 REJ09B0138-0600H...
Page 422: Interrupts
10.5 Interrupts 10.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually.
Page 423 Table 10-13 TPU Interrupts Interrupt DMAC Channel Source Description Activation Activation Priority TGI0A TGR0A input capture/compare match Possible Possible High TGI0B TGR0B input capture/compare match Not possible Possible TGI0C TGR0C input capture/compare match Not possible Possible TGI0D TGR0D input capture/compare match Not possible Possible TCI0V TCNT0 overflow Not possible Not possible...
Page 424: Dtc/Dmac Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
Page 425: Operation Timing
10.6 Operation Timing 10.6.1 Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. ø Falling edge Rising edge Internal clock TCNT input clock TCNT N–1 Figure 10-34 Count Timing in Internal Clock Operation...
Page 426 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.
Page 427 ø Compare match signal Counter clear signal H'0000 TCNT Figure 10-38 Counter Clear Timing (Compare Match) ø Input capture signal Counter clear signal H'0000 TCNT Figure 10-39 Counter Clear Timing (Input Capture) Rev.6.00 Oct.28.2004 page 399 of 1016 REJ09B0138-0600H...
Page 428 Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. ø TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 10-40 Buffer Operation Timing (Compare Match) ø Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 10-41 Buffer Operation Timing (Input Capture) Rev.6.00 Oct.28.2004 page 400 of 1016 REJ09B0138-0600H...
Page 429: Interrupt Signal Timing
10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. ø TCNT input clock TCNT Compare match signal...
Page 430 TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 431 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC or DMAC.
Page 432: Usage Notes
10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states.
Page 433 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case. TCNT write cycle ø...
Page 434 Contention between TGR Write and Compare Match: If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written.
Page 435 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case. TGR read cycle ø...
Page 436 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case. Buffer register write cycle ø...
Page 437 Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-count in the T state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle ø...
Page 438 Rev.6.00 Oct.28.2004 page 410 of 1016 REJ09B0138-0600H...
Page 439: Section 11 Programmable Pulse Generator (Ppg)
Section 11 Programmable Pulse Generator (PPG) 11.1 Overview The H8S/2357 Group has a on-chip programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently.
Page 440: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG. Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 Internal PO12 PODRH NDRH PO11 data bus Pulse output PO10 pins, group 2 Pulse output pins, group 1 PODRL...
Page 441: Pin Configuration
11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Symbol Function Pulse output 0 Output Group 0 pulse output Pulse output 1 Output Pulse output 2 Output Pulse output 3 Output Pulse output 4 Output Group 1 pulse output Pulse output 5 Output...
Page 442: Registers
11.1.4 Registers Table 11-2 summarizes the PPG registers. Table 11-2 PPG Registers Name Abbreviation Initial Value Address* PPG output control register H'FF H'FF46 PPG output mode register H'F0 H'FF47 Next data enable register H NDERH H'00 H'FF48 Next data enable register L NDERL H'00 H'FF49...
Page 443: Register Descriptions
11.2 Register Descriptions 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs, updating the output value.
Page 444: Output Data Registers H And L (Podrh, Podrl)
11.2.2 Output Data Registers H and L (PODRH, PODRL) PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value : R/(W)* R/(W)* R/(W)*...
Page 445 Address H'FF4E — — — — — — — — Initial value : — — — — — — — — If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FF4D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0.
Page 446: Ppg Output Control Register (Pcr)
Address H'FF4D NDR7 NDR6 NDR5 NDR4 — — — — Initial value : — — — — Address H'FF4F — — — — NDR3 NDR2 NDR1 NDR0 Initial value : — — — — 11.2.5 PPG Output Control Register (PCR) G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis.
Page 447: Ppg Output Mode Register (Pmr)
Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). Description Bit 3 Bit 2 G1CMS1 G1CMS0 Output Trigger for Pulse Output Group 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2...
Page 448 Bit 6—Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV Description Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) (Initial value) Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4).
Page 449: Port 1 Data Direction Register (P1Ddr)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). Bit 1 G1NOV Description Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match A or B in the selected TPU channel)
Page 450: Module Stop Control Register (Mstpcr)
11.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 451: Operation
11.3 Operation 11.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 452: Output Timing
11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A.
Page 453: Normal Pulse Output
11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source...
Page 454: Non-Overlapping Pulse Output
Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the...
Page 455 [1] Set TIOR to make TGRA and Non-overlapping TGRB an output compare registers PPG output (with output disabled) Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap Set TGR values margin in TGRA. TPU setup Set counting operation [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR.
Page 456 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four-phase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13 PO12...
Page 457: Inverted Pulse Output
11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7. TCNT value TGRB TCNT...
Page 458: Pulse Output Triggered By Input Capture
11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11-9 shows the timing of this output.
Page 459: Usage Notes
11.4 Usage Notes Operation of Pulse Output Pins: Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins.
Page 460 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin).
Page 461: Section 12 8-Bit Timers
Section 12 8-Bit Timers 12.1 Overview The H8S/2357 Group includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events.
Page 462: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the 8-bit timer module. External clock source Internal clock sources TMCI0 ø/8 TMCI1 ø/64 ø/8192 Clock 1 Clock select Clock 0 TCORA0 TCORA1 Compare match A1 Compare match A0 Comparator A0 Comparator A1 Overflow 1 TMO0...
Page 463: Pin Configuration
12.1.3 Pin Configuration Table 12-1 summarizes the input and output pins of the 8-bit timer. Table 12-1 Input and Output Pins of 8-Bit Timer Channel Name Symbol Function Timer output pin 0 TMO0 Output Outputs at compare match Timer clock input pin 0 TMCI0 Input Inputs external clock for counter...
Page 464: Register Descriptions
12.2 Register Descriptions 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 TCNT1 Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source.
Page 465: Time Constant Registers B0 And B1 (Tcorb0, Tcorb1)
12.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) TCORB0 TCORB1 Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers. TCORB0 and TCORB1 comprise a single 16-bit register so they can be accessed together by word transfer instruction.
Page 466 Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag of TCSR is set to 1. Bit 5 OVIE Description OVF interrupt requests (OVI) are disabled (Initial value) OVF interrupt requests (OVI) are enabled Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select the method by which TCNT is cleared: by compare match A or B, or by an external reset input.
Page 467: Timer Control/Status Registers 0 And 1 (Tcsr0, Tcsr1)
12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1) TCSR0 CMFB CMFA ADTE Initial value : R/(W)* R/(W)* R/(W)* TCSR1 CMFB CMFA — Initial value : R/(W)* R/(W)* R/(W)* — Note: * Only 0 can be written to bits 7 to 5, to clear these flags. TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output.
Page 468 Bit 5—Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed from H'FF to H'00). Bit 5 Description [Clearing condition] (Initial value) Cleared by reading OVF when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare-match A.
Page 469: Module Stop Control Register (Mstpcr)
12.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 470: Operation
12.3 Operation 12.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (ø/8, ø/64, or ø/8192) divided from the system clock (ø) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12-2 shows the count timing. ø...
Page 471: Compare Match Timing
12.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Page 472: Timing Of External Reset On Tcnt
12.3.3 Timing of External RESET on TCNT TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12-7 shows the timing of this operation. ø...
Page 473: Operation With Cascaded Connection
12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode).
Page 474: Interrupts
12.4 Interrupts 12.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12-3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller.
Page 475: Sample Application
12.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12-9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA.
Page 476: Usage Notes
12.6 Usage Notes Application programmers should note that the following kinds of contention can occur in the 8-bit timer. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed.
Page 477: Contention Between Tcnt Write And Increment
12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12-11 shows this operation. TCNT write cycle by CPU ø...
Page 478: Contention Between Tcor Write And Compare Match
12.6.3 Contention between TCOR Write and Compare Match During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is disabled even if a compare match event occurs. Figure 12-12 shows this operation. TCOR write cycle by CPU ø...
Page 479: Switching Of Internal Clocks And Tcnt Operation
12.6.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12-5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected.
Page 480: Interrupts And Module Stop Mode
Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Clock before Switching from high switchover to high Clock after switchover TCNT clock TCNT CKS bit write Notes: 1. Includes switching from low to stop, and from stop to low. 2.
Page 481: Section 13 Watchdog Timer
Section 13 Watchdog Timer 13.1 Overview The H8S/2357 Group has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow.
Page 482: Block Diagram
13.1.2 Block Diagram Figure 13-1 shows a block diagram of the WDT. Overflow ø/2 Interrupt ø/64 WOVI control ø/128 (interrupt request signal) ø/512 Clock Clock select ø/2048 ø/8192 ø/32768 WDTOVF Reset ø/131072 control Internal reset signal Internal clock sources RSTCSR TCNT TSCR interface...
Page 483: Register Configuration
13.1.4 Register Configuration The WDT has three registers, as summarized in table 13-2. These registers control clock selection, WDT mode switching, and the reset signal. Table 13-2 WDT Registers Address* Name Abbreviation Initial Value Write* Read Timer control/status register TCSR R/(W)* H'18 H'FFBC...
Page 484: Register Descriptions
13.2 Register Descriptions 13.2.1 Timer Counter (TCNT) Initial value : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)* or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
Page 485: Reset Control/Status Register (Rstcsr)
Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal* when TCNT overflows.
Page 486 RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows.
Page 487: Notes On Register Access
13.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions.
Page 488: Operation
13.3 Operation 13.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally.
Page 489: Interval Timer Operation
13.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 13-5.
Page 490: Timing Of Setting Of Watchdog Timer Overflow Flag (Wovf)
13.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2357 Group chip.
Page 491: Usage Notes
13.5 Usage Notes 13.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13-8 shows this operation. TCNT write cycle ø...
Page 492: Internal Reset In Watchdog Timer Mode
H8S/2357 Group Reset input Reset signal to entire system WDTOVF * Note: * The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or H8S/2390. Figure 13-9 Circuit for System Reset by WDTOVF Signal (Example) 13.5.5 Internal Reset in Watchdog Timer Mode The H8S/2357 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer...
Page 493: Section 14 Serial Communication Interface (Sci)
Section 14 Serial Communication Interface (SCI) 14.1 Overview The H8S/2357 Group is equipped with a three-channel serial communication interface (SCI). All three channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Page 494 • Four interrupt sources  Four interrupt sources — transmit-data-empty, transmit-end, receive-data-full, and receive error — that can issue requests independently  The transmit-data-empty interrupt and receive-data-full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer •...
Page 495: Block Diagram
14.1.2 Block Diagram Figure 14-1 shows a block diagram of the SCI. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check External clock Legend: SCMR: Smart Card mode register RSR: Receive shift register RDR:...
Page 496: Register Configuration
14.1.4 Register Configuration The SCI has the internal registers shown in table 14-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format, and the bit rate, and to control transmitter/receiver. Table 14-2 SCI Registers Channel Name Abbreviation...
Page 497: Register Descriptions
14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 498: Transmit Data Register (Tdr)
14.2.4 Transmit Data Register (TDR) Initial value : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission.
Page 499 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 Description Parity bit addition and checking disabled...
Page 500: Serial Control Register (Scr)
For details of the multiprocessor communication function, see section 14.3.3, Multiprocessor Communication Function. Bit 2 Description Multiprocessor function disabled (Initial value) Multiprocessor format selected Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0.
Page 501 Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request...
Page 502 The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description Multiprocessor interrupts disabled (normal reception performed) (Initial value) [Clearing conditions] • When the MPIE bit is cleared to 0 •...
Page 503: Serial Status Register (Ssr)
For details of clock source selection, see table 14-9 in section 14.3, Operation. Bit 1 Bit 0 CKE1 CKE0 Description Asynchronous mode Internal clock/SCK pin functions as I/O port* Clocked synchronous Internal clock/SCK pin functions as serial clock mode output Asynchronous mode Internal clock/SCK pin functions as clock output* Clocked synchronous...
Page 504 Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF Description [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception...
Page 505 Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 Description [Clearing condition] (Initial value)* When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* Notes: 1.
Page 506: Bit Rate Register (Brr)
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode.
Page 507 ø = 3.6864 MHz ø = 4 MHz ø = 4.9152 MHz ø = 5 MHz Bit Rate Error Error Error Error (bit/s) 0.70 0.03 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00...
Page 508 ø = 9.8304 MHz ø = 10 MHz ø = 12 MHz ø = 12.288 MHz Bit Rate Error Error Error Error (bit/s) –0.26 2 –0.25 2 0.03 0.08 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 0.00 0.16 0.16 0.00 1200 0.00...
Page 509 ø = 18 MHz ø = 19.6608 MHz ø = 20 MHz Bit Rate Error Error Error (bit/s) –0.12 3 0.31 –0.25 0.16 0.00 0.16 0.16 0.00 0.16 0.16 0.00 0.16 1200 0.16 0.00 0.16 2400 0.16 0.00 0.16 4800 0.16 0.00 0.16...
Page 510 The BRR setting is found from the following formulas. Asynchronous mode: ø × 10 – 1 64 × 2 × B 2n–1 Clocked synchronous mode: ø × 10 – 1 8 × 2 × B 2n–1 Where B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤...
Page 511 Table 14-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 14-6 and 14-7 show the maximum bit rates with external clock input. Table 14-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bit/s) 62500 2.097152 65536...
Page 512 Table 14-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 513: Smart Card Mode Register (Scmr)
14.2.9 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value : — — — — — SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB- first or MSB-first can be selected regardless of the serial communication mode.
Page 514: Module Stop Control Register (Mstpcr)
14.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 515: Operation
14.3 Operation 14.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 14-8.
Page 516 Table 14-8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Multi Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Processor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data 1 bit mode 2 bits 1 bit 2 bits...
Page 517: Operation In Asynchronous Mode
14.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis.
Page 518 Table 14-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
Page 519 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14-9.
Page 520 Figure 14-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Start initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 When the clock is selected in asynchronous mode, it is output Set CKE1 and CKE0 bits in SCR...
Page 521 • Serial data transmission (asynchronous mode) Figure 14-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin.
Page 522 [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output.
Page 523 • Serial data reception (asynchronous mode) Figure 14-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin.
Page 524 Error processing ORER= 1 Overrun error processing FER= 1 Break? Framing error processing Clear RE bit in SCR to 0 PER= 1 Parity error processing Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14-7 Sample Serial Reception Data Flowchart (cont) Rev.6.00 Oct.28.2004 page 496 of 1016 REJ09B0138-0600H...
Page 525 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
Page 526 Table 14-11 Receive Errors and Conditions for Occurrence Receive Error Abbreviation Occurrence Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 RDR.
Page 527: Multiprocessor Communication Function
14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
Page 528 Data Transfer Operations: • Multiprocessor serial data transmission Figure 14-10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start transmission output pin.
Page 529 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
Page 530 • Multiprocessor serial data reception Figure 14-12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start reception input pin.
Page 531 Error processing ORER= 1 Overrun error processing FER= 1 Break? Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14-12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.6.00 Oct.28.2004 page 503 of 1016 REJ09B0138-0600H...
Page 532 Figure 14-13 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) Stop Start Data (Data1) Stop Idle state (mark state) MPIE RDRF value MPIE = 0 RXI interrupt RDR data read If not this station’s ID, RXI interrupt request is request and RDRF flag...
Page 533: Operation In Clocked Synchronous Mode
14.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock.
Page 534 Data Transfer Operations: • SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 535 • Serial data transmission (clocked synchronous mode) Figure 14-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start transmission pin.
Page 536 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
Page 537 • Serial data reception (clocked synchronous mode) Figure 14-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0.
Page 538 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
Page 539 • Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 14-20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the...
Page 540: Sci Interrupts
14.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive- data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 14-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR.
Page 541 Table 14-12 SCI Interrupt Sources Interrupt DMAC Channel Source Description Activation Activation Priority* Interrupt due to receive error High (ORER, FER, or PER) possible possible Interrupt due to receive data full Possible Possible state (RDRF) Interrupt due to transmit data empty Possible Possible state (TDRE)
Page 542: Usage Notes
14.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Page 543 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
Page 544 Where M : Reception margin (%) N : Ratio of bit rate to clock (N = 16) D : Clock duty (D = 0 to 1.0) L : Frame length (L = 9 to 12) F : Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below.
Page 545: Section 15 Smart Card Interface
Section 15 Smart Card Interface 15.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.
Page 546: Block Diagram
15.1.2 Block Diagram Figure 15-1 shows a block diagram of the Smart Card interface. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check Legend: SCMR: Smart Card mode register RSR: Receive shift register RDR:...
Page 547: Register Configuration
15.1.4 Register Configuration Table 15-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI).
Page 548: Register Descriptions
15.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 15.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value : — — — —...
Page 549: Serial Status Register (Ssr)
15.2.2 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different.
Page 550: Serial Mode Register (Smr)
15.2.3 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value : Set value* : CKS1 CKS0 Note: * When the Smart Card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. The function of bit 7 of SMR changes in Smart Card interface mode.
Page 551: Serial Control Register (Scr)
15.2.4 Serial Control Register (SCR) MPIE TEIE CKE1 CKE0 Initial value : In Smart Card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI.
Page 552: Operation
15.3 Operation 15.3.1 Overview The main functions of the Smart Card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
Page 553: Data Format
15.3.3 Data Format Figure 15-3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested.
Page 554: Register Settings
15.3.4 Register Settings Table 15-3 shows a bit map of the registers used by the Smart Card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 15-3 Smart Card Interface Register Settings Register Bit 7 Bit 6...
Page 555: Clock
• Direct convention (SDIR = SINV = O/E = 0) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card.
Page 556 Table 15-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) ø (MHz) 10.00 10.714 13.00 14.285 16.00 18.00 20.00 13441 14400 17473 19200 21505 24194 26882 6720 7200 8737 9600 10753 12097 13441 4480 4800 5824 6400...
Page 557: Data Transfer Operations
15.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
Page 558 Start Initialization Start transmission ERS=0? Error processing TEND=1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS=0? Error processing TEND=1? Clear TE bit to 0 Figure 15-4 Example of Transmission Processing Flow Rev.6.00 Oct.28.2004 page 530 of 1016 REJ09B0138-0600H...
Page 559 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output (3) Serial data output Data 1 In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 560 Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 15-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Page 561 If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1.
Page 562: Operation In Gsm Mode
and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated.
Page 563: Usage Notes
Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 15-9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
Page 564  D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows.
Page 565 [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1.
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Page 567: Section 16 A/D Converter
Section 16 A/D Converter 16.1 Overview The H8S/2357 Group incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 16.1.1 Features A/D converter features are listed below • 10-bit resolution • Eight input channels •...
Page 568: Block Diagram
16.1.2 Block Diagram Figure 16-1 shows a block diagram of the A/D converter. Module data bus Internal data bus 10-bit D/A – Comparator Control circuit Sample-and- hold circuit interrupt ADTRG 8-bit timer or conversion start trigger from TPU Legend: ADCR: A/D control register ADCSR : A/D control/status register...
Page 569: Register Configuration
Table 16-1 A/D Converter Pins Pin Name Symbol Function Analog power supply pin Input Analog block power supply Analog ground pin Input Analog block ground and A/D conversion reference voltage Reference voltage pin Input A/D conversion reference voltage Analog input pin 0 Input Group 0 analog inputs Analog input pin 1...
Page 570: Register Descriptions
16.2 Register Descriptions 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there.
Page 571 Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 Description [Clearing conditions] (Initial value) • When 0 is written to the ADF flag after reading ADF = 1 • When the DTC is activated by an ADI interrupt and ADDR is read [Setting conditions] •...
Page 572: A/D Control Register (Adcr)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). Group Selection Channel Selection Description Single Mode (SCAN=0) Scan Mode (SCAN=1) AN0 (Initial value)
Page 573: Module Stop Control Register (Mstpcr)
16.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 574: Interface To Bus Master
16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows.
Page 575 On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion.
Page 576: Scan Mode (Scan = 1)
16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately.
Page 577: Input Sampling And A/D Conversion Time
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the A/D conversion time.
Page 578: External Trigger Input Timing
16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Page 579: Usage Notes
16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range ≤ ANn ≤ The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AV (2) Relation between AV , AV and V...
Page 580 100 Ω AN0 to AN7 0.1 µF Notes: Values are reference values. 10 µF 0.01 µF : Input impedance 2. R Figure 16-7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: H8S/2357 Group A/D conversion precision definitions are given below. •...
Page 581 Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 16-8 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16-9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2357 Group analog input is designed so that conversion precision is...
Page 582 However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 kohm, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/µs or greater).
Page 583: Section 17 D/A Converter
Section 17 D/A Converter 17.1 Overview The H8S/2357 Group includes a two-channel D/A converter. 17.1.1 Features D/A converter features are listed below • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) •...
Page 584: Pin Configuration
17.1.3 Pin Configuration Table 17-1 summarizes the input and output pins of the D/A converter. Table 17-1 Pin Configuration Pin Name Symbol Function Analog power pin Input Analog power source Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Channel 0 analog output Analog output pin 1...
Page 585: Register Descriptions
17.2 Register Descriptions 17.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) Initial value : DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode.
Page 586: Module Stop Control Register (Mstpcr)
Bit 5—D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together.
Page 587: Operation
17.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0.
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Page 589: Section 18 Ram
Section 18 RAM 18.1 Overview The H8S/2357, H8S/2352, H8S/2398, and H8S/2392 have 8 kbytes of on-chip high-speed static RAM. The H8S/2394 has 32 kbytes of on-chip high-speed static RAM. The H8S/2390 has 4 kbytes of on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 16-bit bus, and accessing both byte data and word data can be performed in a single state.
Page 590: Register Descriptions
18.2 Register Descriptions 18.2.1 System Control Register (SYSCR) — — INTM1 INTM0 NMIEG — — RAME Initial value : — — The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR).
Page 591: Section 19 Rom
Section 19 ROM 19.1 Overview This series has 256, or 128 kbytes of flash memory, 256 or 128 kbytes of masked ROM, or 128 kbytes of PROM. The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing.
Page 592: Register Descriptions
19.2 Register Descriptions 19.2.1 Mode Control Register (MDCR) — — — — — MDS2 MDS1 MDS0 Initial value : —* —* —* — — — — — Note: * Determined by pins MD to MD MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2357 Group. Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Page 593: Operation
19.3 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address.
Page 594: Prom Mode (H8S/2357 Ztat)
Table 19-3 Operating Modes and ROM Area (ZTAT or Masked ROM, ROMless, Versions H8S/2398F-ZTAT) Mode Pin BCRL Operating Mode On-Chip ROM Mode 0 — — — Mode 1 Mode 2* Mode 3* Mode 4* Advanced expanded mode — Disabled with on-chip ROM disabled Mode 5* Advanced expanded mode with on-chip ROM disabled...
Page 595: Socket Adapter And Memory Map
19.4.2 Socket Adapter and Memory Map Programs can be written and verified by attaching a socket adapter to the PROM programmer to convert from a 120/128- pin arrangement to a 32-pin arrangement. Table 19-5 gives ordering information for the socket adapter, and figure 19-2 shows the wiring of the socket adapter.
Page 596 Table 19-5 Socket Adapter Microcontroller Package Socket Adapter H8S/2357 120 pin TQFP (TFP-120) HS2655ESNS1H 128 pin QFP (FP-128B) HS2655ESHS1H Addresses in Addresses in MCU mode PROM mode H'000000 H'00000 On-chip PROM H'01FFFF H'1FFFF Figure 19-3 Memory Map in PROM Mode Rev.6.00 Oct.28.2004 page 568 of 1016 REJ09B0138-0600H...
Page 597: Programming (H8S/2357 Ztat)
19.5 Programming (H8S/2357 ZTAT) 19.5.1 Overview Table 19-6 shows how to select the program, verify, and program-inhibit modes in PROM mode. Table 19-6 Mode Selection in PROM Mode Pins Mode to EO to EA Program Data input Address input Verify Data output Address input Program-inhibit...
Page 598: Programming And Verification
19.5.2 Programming and Verification An efficient, high-speed programming procedure can be used to program and verify PROM data. This procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. It leaves the data H'FF in unused addresses.
Page 599 Table 19-7 DC Characteristics in PROM Mode = 6.0 V ± 0.25 V, V = 12.5 V ± 0.3 V, V = 25°C ± 5°C Conditions: V = 0 V, T Test Item Symbol Min Unit Conditions Input high voltage to EO —...
Page 600: Programming Precautions
The programming voltage (V ) in PROM mode is 12.5 V. If the PROM programmer is set to Renesas Technology HN27C101 specifications, V will be 12.5 V. Applied voltages in excess of the specified values can permanently destroy the MCU. Be particularly careful about the PROM programmer’s overshoot characteristics.
Page 601: Reliability Of Programmed Data
If a series of programming errors occurs while the same PROM programmer is being used, stop programming and check the PROM programmer and socket adapter for defects. Please inform Renesas Technology of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
Page 602: Overview Of Flash Memory (H8S/2357 F-Ztat)
19.6 Overview of Flash Memory (H8S/2357 F-ZTAT) 19.6.1 Features The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode  Program-verify mode  Erase-verify mode • Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase (in single-block units). When erasing multiple blocks, the individual blocks must be erased sequentially.
Page 603: Block Diagram
19.6.2 Block Diagram Internal address bus Internal data bus (16 bits) SYSCR2 FLMCR1 Operating FWE pin Bus interface/controller mode Mode pins FLMCR2 EBR1 EBR2 RAMER Flash memory (128 kbytes) Legend: SYSCR2: System control register 2 FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1...
Page 604: Flash Memory Operating Modes
19.6.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the MCU enters one of the operating modes shown in figure 19-8. In user mode, flash memory can be read but not programmed or erased.
Page 605: Boot Mode
On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the H8S/2357 chip (originally incorporated in the programming control program and new chip) is started and the programming control...
Page 606 • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The FWE assessment program that confirms When the FWE pin is driven high, user software that the FWE pin has been driven high, and (2) confirms this fact, executes the transfer program the program that will transfer the programming/ in the flash memory, and transfers the erase control program to on-chip RAM should be...
Page 607 Flash Memory Emulation in RAM • Reading Overlap Data in User Mode and User Program Mode Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Flash memory Overlap RAM Emulation block...
Page 608 Differences between Boot Mode and User Program Mode Table 19-9 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Block erase Programming control program* Program/program-verify Program/program-verify Erase/erase-verify Note: * To be provided by the user, in accordance with the recommended algorithm. Block Configuration: The flash memory is divided into two 32-kbyte blocks, two 8-kbyte blocks, one 16-kbyte block, one 28-kbyte block, and four 1-kbyte blocks.
Page 609: Pin Configuration
19.6.4 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-10. Table 19-10 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets MCU operating mode Mode 1...
Page 610: Register Descriptions
19.7 Register Descriptions 19.7.1 Flash Memory Control Register 1 (FLMCR1) — — Initial value —* Read/Write — — Note: * Determined by the state of the FWE pin. FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1.
Page 611 Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing.
Page 612: Flash Memory Control Register 2 (Flmcr2)
19.7.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — Initial value Read/Write — — — — — FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode.
Page 613: Erase Block Registers 1 And 2 (Ebr1, Ebr2)
Bit 0 Description Program setup cleared (Initial value) Program setup [Setting condition] When FWE = 1, and SWE = 1 19.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 — — — — — — Initial value Read/Write — —...
Page 614: System Control Register 2 (Syscr2)
19.7.4 System Control Register 2 (SYSCR2) — — — — FLSHE — — — Initial value Read/Write — — — — — — — SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT versions). SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 is available only in the F-ZTAT version.
Page 615 Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory block are program/erase-protected. Bit 2 RAMS Description Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together with bit 2 to select the flash...
Page 616: On-Board Programming Modes
19.8 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19-14. For a diagram of the transitions to the various flash memory modes, see figure 19-8.
Page 617 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Host transmits number MCU measures low period of programming control program of H'00 data transmitted by host bytes (N), upper byte followed by lower byte MCU calculates bit rate and sets value in bit rate register...
Page 618 Automatic SCI Bit Rate Adjustment Start Stop Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 19-16 Automatic SCI Bit Rate Adjustment When boot mode is initiated, the H8S/2357 MCU measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host.
Page 619 H'FFDC00 Boot program area* (2 kbytes) H'FFE3FF Programming control program area (6 kbytes) H'FFFB7F (128 bytes)* H'FFFBFF Notes: 1. The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program.
Page 620: User Program Mode
• If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode* Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Page 621 Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE*...
Page 622: Programming/Erasing Flash Memory
19.9 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU and ESU bits in FLMCR2, and the P, E, PV, and EV bits in FLMCR1.
Page 623 19-19) and transferred to the reprogram data area. After 32 bytes of data have been verified, exit program-verify mode, wait for at least (η) µs, then clear the SWE bit in FLMCR1 to 0. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before.
Page 624: Erase Mode
19.9.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19-20. The wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and the maximum number of programming operations (N) are shown in table 22.42 in section 22.7.6, Flash Memory Characteristics.
Page 625 Start Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) ms n ← n + 1 Clear E bit in FLMCR1 Halt erase Wait (α) µs...
Page 626: Flash Memory Protection
19.10 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.10.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2).
Page 627: Software Protection
19.10.2 Software Protection Software protection can be implemented by setting the SWE bit in FLMCR1, erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in RAMER. When software protection is in effect, setting the P or E bit in flash memory control register 1 (FLMCR1) does not cause a transition to program mode or erase mode.
Page 628 Normal Operating mode Reset or hardware standby Program mode RES = 0 or STBY = 0 (hardware protection) Erase mode RD VF PR ER RD VF PR ER FLER = 0 FLER = 0 RES = 0 or Error occurrence FLMCR1, FLMCR2, STBY = 0 (software standby)
Page 629: Flash Memory Emulation In Ram
19.11 Flash Memory Emulation in RAM 19.11.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory.
Page 630: 19.11.2 Ram Overlap
19.11.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. H'000000 H'000400 This area can be accessed H'000800 from both the RAM area and flash memory area H'000C00 Flash memory EB4 to EB9 H'FFDC00 H'FFDFFF On-chip RAM...
Page 631: Interrupt Handling When Programming/Erasing Flash Memory
19.12 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI interrupt is disabled when flash memory is being programmed or erased (when the P or E bit is set in FLMCR1), and while the boot program is executing in boot mode* , to give priority to the program or erase operation.
Page 632: Flash Memory Programmer Mode
Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports Renesas Technology microcomputer device types with 128-kbyte on-chip flash memory. Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Page 633: 19.13.3 Programmer Mode Operation
19.13.3 Programmer Mode Operation Table 19-19 shows how the different operating modes are set when using programmer mode, and table 19-20 lists the commands used in programmer mode. Details of each mode are given below. • Memory Read Mode Memory read mode supports byte reads. •...
Page 634: Memory Read Mode
Table 19-20 Programmer Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data × Memory read mode 1 + n Write H'00 Read Dout × Auto-program mode Write H'40 Write × × Auto-erase mode Write H'20 Write...
Page 635 Command write Memory read mode Address Address stable nxtc Data H'00 Data Note: Data is latched on the rising edge of WE. Figure 19-25 Memory Read Mode Timing Waveforms after Command Write Table 19-22 AC Characteristics when Entering Another Mode from Memory Read Mode = 5.0 V ±10%, V = 25°C ±5°C Conditions: V...
Page 636 ×× mode command write Address Address stable nxtc Data Data H'×× Note: Do not enable WE and OE at the same time. Figure 19-26 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 19-23 AC Characteristics in Memory Read Mode = 5.0 V ±10%, V = 25°C ±5°C Conditions: V...
Page 637: 19.13.5 Auto-Program Mode
Address Address stable Address stable Data Data Data Figure 19-28 Timing Waveforms for CE/OE Clocked Read 19.13.5 Auto-Program Mode AC Characteristics Table 19-24 AC Characteristics in Auto-Program Mode = 5.0 V ±10%, V = 25°C ±5°C Conditions: V = 0 V, T Item Symbol Unit...
Page 638 Address Address stable nxtc nxtc Data transfer wsts 1 byte to 128 bytes (1 to 3000 ms) write Programming operation end identification signal Programming normal end identification signal Programming wait Data H'40 Data Data Figure 19-29 Auto-Program Mode Timing Waveforms Notes on Use of Auto-Program Mode •...
Page 639: 19.13.6 Auto-Erase Mode
19.13.6 Auto-Erase Mode AC Characteristics Table 19-25 AC Characteristics in Auto-Erase Mode = 5.0 V ±10%, V = 25°C ±5°C Conditions: V = 0 V, T Item Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time —...
Page 640: 19.13.7 Status Read Mode
• The status polling I/O and I/O pin information is retained until the next command write. Until the next command write is performed, reading is possible by enabling CE and OE. 19.13.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 641: Status Polling
Table 19-27 Status Read Mode Return Commands Pin Name I/O Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address error identification erase count exceeded Initial value 0 Indications Normal Command Program- Erase — —...
Page 642: Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
Page 643 • In user program mode, FWE can be switched between high and low level regardless of the reset state. FWE input can also be switched during program execution in flash memory. • Do not apply FWE if program runaway has occurred. •...
Page 644 Programming and erase possible Wait time: x φ min 0 µs OSC1 min 0 µs to MD clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Always fix the level by pulling down or pulling up the mode pins (MD to MD Notes:...
Page 645 Programming and erase possible Wait time: x φ min 0 µs OSC1 to MD clear SWE bit Flash memory access disabled period (x: Wait time after SWE setting) Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Always fix the level by pulling down or pulling up the mode pins (MD to MD Notes:...
Page 646 Programming Programming Programming and Wait Programming and Wait erase erase Wait time: x erase possible Wait time: x possible time: x erase possible time: x possible φ OSC1 min 0µs to MD RESW SWE set SWE clear SWE bit User Boot mode Mode switching * Mode...
Page 647: Overview Of Flash Memory (H8S/2398 F-Ztat)
19.15 Overview of Flash Memory (H8S/2398 F-ZTAT) 19.15.1 Features The H8S/2398 F-ZTAT have 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode ...
Page 648: 19.15.2 Overview
19.15.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating Mode pins Bus interface/controller mode EBR1 EBR2 RAMER SYSCR2 Flash memory (256 kbytes) Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2:...
Page 649: 19.15.3 Flash Memory Operating Modes
19.15.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 19-37. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode.
Page 650: 19.15.4 On-Board Programming Modes
19.15.4 On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the chip (originally incorporated in the chip) is programming control program and new started and the programming control program in...
Page 651 • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the Executes the transfer program in the flash programming/erase control program to on-chip memory, and transfers the programming/erase RAM should be written into the flash memory by control program to RAM.
Page 652: 19.15.5 Flash Memory Emulation In Ram
19.15.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read.
Page 653: Differences Between Boot Mode And User Program Mode
19.15.6 Differences between Boot Mode and User Program Mode Table 19-30 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Entire memory erase Block erase Programming control program* Program/program-verify Erase/erase-verify/program/ program-verify/emulation Note: * To be provided by the user, in accordance with the recommended algorithm. 19.15.7 Block Configuration Products include 256 kbytes of flash memory are divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4- kbyte blocks.
Page 654: 19.15.8 Pin Configuration
19.15.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 19-31. Table 19-31 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Mode 2 Input Sets MCU operating mode Mode 1 Input Sets MCU operating mode Mode 0 Input Sets MCU operating mode...
Page 655: Register Descriptions
19.16 Register Descriptions 19.16.1 Flash Memory Control Register 1 (FLMCR1) Initial value : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1, then setting the PSU bit, and finally setting the P bit.
Page 656 Bit 3—Erase-Verify (EV): Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 Description Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] When SWE = 1 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing.
Page 657: Flash Memory Control Register 2 (Flmcr2)
19.16.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value : — — — — — — — FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode.
Page 658: Erase Block Registers 2 (Ebr2)
19.16.4 Erase Block Registers 2 (EBR2) EBR2 — — — — EB11 EB10 Initial value : — — — — EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set.
Page 659: Ram Emulation Register (Ramer)
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained). Bit 3 FLSHE Description...
Page 660: On-Board Programming Modes
Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 19-34.) Table 19-34 Flash Memory Area Divisions RAM Area Block Name RAMS RAM2...
Page 661: 19.17.1 Boot Mode
19.17.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2398 F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
Page 662 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Host transmits number Chip measures low period of programming control program of H'00 data transmitted by host bytes (N), upper byte followed by lower byte Chip calculates bit rate and sets value in bit rate register...
Page 663 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, H8S/2398 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
Page 664 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19-46. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF.
Page 665: 19.17.2 User Program Mode
Do not change the mode pin input levels in boot mode. • If the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR) will change according to the change in the microcomputer’s operating mode* Therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer.
Page 666: Programming/Erasing Flash Memory
19.18 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased.
Page 667 program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Write pulse application subroutine Start of programming Perform programming in the erased state. Sub-routine write pulse Start Do not perform additional programming Enable WDT Set SWE bit in FLMCR1 on previously programmed addresses.
Page 668: 19.18.3 Erase Mode
19.18.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19-49. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.3.6, Flash Memory Characteristics.
Page 669 Start Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) ms n ← n + 1 Clear E bit in FLMCR1 Halt erase Wait (α) µs...
Page 670: Flash Memory Protection
19.19 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.19.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset.
Page 671: Software Protection
19.19.2 Software Protection Software protection can be implemented by setting the SWE bit in flash memory control register 1 (FLMCR1), erase block registers 1 and 2 (EBR1, EBR2), and the RAMS bit in the RAM emulation register (RAMER). When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode.
Page 672: 19.19.3 Error Protection
19.19.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
Page 673: Flash Memory Emulation In Ram
19.20 Flash Memory Emulation in RAM 19.20.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory.
Page 674: 19.20.2 Ram Overlap
19.20.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFDC00 H'FFEBFF Flash memory...
Page 675: Interrupt Handling When Programming/Erasing Flash Memory
Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas Technology microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V5A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Page 676: 19.22.2 Socket Adapters And Memory Map
19.22.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is connected to the chip as shown in figure 19-54. Figure 19-53 shows the on-chip ROM memory map and figure 19-54 show the socket adapter pin assignments. H8S/2398 MCU mode address Programmer mode address F-ZTAT...
Page 677 H8S/2398 F-ZTAT HN27C4096HG (40 Pins) Socket Adapter (40-Pin Conversion) TFP-120 FP-128B Pin No. Pin Name Pin Name Capacitor 1, 40 1, 30, 33, 52, 55,74, 5, 34, 39, 58, 61, 82, 75, 76, 81, 93, 94 83, 84, 89, 103, 104 11, 30 5, 6, 7 6, 15, 24, 31, 32, 38,...
Page 678: 19.22.3 Programmer Mode Operation
19.22.3 Programmer Mode Operation Table 19-40 shows how the different operating modes are set when using programmer mode, and table 19-41 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.
Page 679: Memory Read Mode
19.22.4 Memory Read Mode • After the end of an auto-program, auto-erase, or status read operation, the command wait state is entered. To read memory contents, a transition must be made to memory read mode by means of a command write before the read is executed.
Page 680 Table 19-43 AC Characteristics when Entering Another Mode from Memory Read Mode = 5.0 V ±10%, V = 25°C ±5°C Conditions: V = 0 V, T Item Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time —...
Page 681: 19.22.5 Auto-Program Mode
to A Address stable Address stable to I/O Figure 19-57 Timing Waveforms for CE/OE Enable State Read Address stable Address stable to A to I/O Figure 19-58 Timing Waveforms for CE/OE Clocked Read 19.22.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed.
Page 682 AC Characteristics Table 19-45 AC Characteristics in Auto-Program Mode = 5.0 V ±10%, V = 25°C ±5°C Conditions: V = 0 V, T Item Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time — Data hold time —...
Page 683: 19.22.6 Auto-Erase Mode
19.22.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O . Alternatively, status read mode can also be used for this purpose (the I/O status polling pin is used to identify the end of an auto-erase operation).
Page 684: 19.22.7 Status Read Mode
19.22.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19-47 AC Characteristics in Status Read Mode = 5.0 V ±10%, V = 25°C ±5°C...
Page 685: 19.22.8 Status Polling
Table 19-48 Status Read Mode Return Commands Pin Name I/O Attribute Normal Command Program- Erase — — Program- Effective error ming error error ming or address error identification erase count exceeded Initial value 0 Indications Normal Command Program- Erase — —...
Page 686: 19.22.10 Notes On Memory Programming
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.
Page 687 one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the PROM programmer: Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned.
Page 688 Rev.6.00 Oct.28.2004 page 660 of 1016 REJ09B0138-0600H...
Page 689: Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator 20.1 Overview The H8S/2357 Group has a on-chip clock pulse generator (CPG) that generates the system clock (ø), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-speed clock divider, and a bus master clock selection circuit.
Page 690: Register Descriptions
20.2 Register Descriptions 20.2.1 System Clock Control Register (SCKCR) PSTOP — — — — SCK2 SCK1 SCK0 Initial value : —/(R/W)* — — SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * R/W in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398.
Page 691: Oscillator
20.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 20.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 20-2. Select the damping resistance R according to table 20-2.
Page 692: External Clock Input
Note on Board Design: When a crystal resonator is connected, the following points should be noted. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 20-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins.
Page 693: Duty Adjustment Circuit
Table 20-4 and figure 20-6 show the input conditions for the external clock. Table 20-4 External Clock Input Conditions = 5.0 V ± = 2.7 V to 5.5 V Test Item Symbol Unit Conditions External clock input — — Figure 20-6 low pulse width External clock input —...
Page 694 Rev.6.00 Oct.28.2004 page 666 of 1016 REJ09B0138-0600H...
Page 695: Section 21 Power-Down Modes
Section 21 Power-Down Modes 21.1 Overview In addition to the normal program execution state, the H8S/2357 Group has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.
Page 696: Register Configuration
21.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 21-2 summarizes these registers. Table 21-2 Power-Down Mode Registers Name Abbreviation Initial Value Address* Standby control register SBYCR H'08 H'FF38 System clock control register SCKCR H'00 H'FF3A Module stop control register H...
Page 697: Register Descriptions
21.2 Register Descriptions 21.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — — Initial value : — — SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode.
Page 698: System Clock Control Register (Sckcr)
Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode. Bit 3 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value)
Page 699: Module Stop Control Register (Mstpcr)
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description Bus master in high-speed mode (Initial value) Medium-speed clock is ø/2 Medium-speed clock is ø/4 Medium-speed clock is ø/8 Medium-speed clock is ø/16 Medium-speed clock is ø/32...
Page 700: Medium-Speed Mode
21.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium-speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits.
Page 701: Module Stop Mode
21.5 Module Stop Mode 21.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 702: Usage Notes
21.5.2 Usage Notes DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated.
Page 703: Software Standby Mode
21.6 Software Standby Mode 21.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained.
Page 704: Software Standby Mode Application Example
Table 21-4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time MHz Unit 8,192 states 0.41 0.51 0.68 0.8 16,384 states 0.82 1.0 32,768 states 8.2 16.4 65,536 states...
Page 705: Usage Notes
Oscillator ø NMIEG SSBY NMI exception Software standby mode NMI exception Oscillation handling (power-down mode) handling stabilization NMIEG=1 time t SSBY=1 OSC2 SLEEP instruction Figure 21-2 Software Standby Mode Application Example 21.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained.
Page 706: Hardware Standby Mode
21.7 Hardware Standby Mode 21.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation.
Page 707: Clock Output Disabling Function
21.8 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle, and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0.
Page 708 Rev.6.00 Oct.28.2004 page 680 of 1016 REJ09B0138-0600H...
Page 709: Section 22 Electrical Characteristics
Section 22 Electrical Characteristics 22.1 Electrical Characteristics of Masked ROM Version (H8S/2398) and ROMless Versions (H8S/2394, H8S/2392, and H8S/2390) 22.1.1 Absolute Maximum Ratings Table 22-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except port 4) –0.3 to + V +0.3 Input voltage (port 4)
Page 710: Dc Characteristics
22.1.2 DC Characteristics Table 22-2 lists the DC characteristics. Table 22-3 lists the permissible output currents. Table 22-2 DC Characteristics = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: V = 4.5 V to AV = AV = 0 V* , Ta = -20 to +75°C (regular specifications), Ta = -40 to +85°C (wide-range specifications)
Page 711 Item Symbol Unit Test Conditions Current Normal — f = 20 MHz dissipation* operation (5.0 V) Sleep mode — f = 20 MHz (5.0 V) µA ≤ 50°C Standby — 0.01 mode* — — 50°C < T Analog power During A/D —...
Page 712: Ac Characteristics
The chip 2 kΩ Port Darlington Pair Figure 22-1 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C Figure 22-2 LED Drive Circuit (Example) 22.1.3 AC Characteristics Figure 22-3 show, the test conditions for the AC characteristics. C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G LSI output pin...
Page 713 (1) Clock Timing Table 22-4 lists the clock timing Table 22-4 Clock Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø = 10 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition...
Page 714 EXTAL DEXT DEXT STBY OSC1 OSC1 ø Figure 22-5 Oscillator Settling Timing (2) Control Signal Timing Table 22-5 lists the control signal timing. Table 22-5 Control Signal Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV...
Page 715 ø RESS RESS RESW Figure 22-6 Reset Input Timing ø NMIH NMIS NMIW IRQW IRQS IRQH Edge input IRQS Level input Figure 22-7 Interrupt Input Timing Rev.6.00 Oct.28.2004 page 687 of 1016 REJ09B0138-0600H...
Page 716 (3) Bus Timing Table 22-6 lists the bus timing. Table 22-6 Bus Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø= 10 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition...
Page 717 Condition Test Item Symbol Unit Conditions 0.5 × WR hold time — Figure 22-8 to – 10 Figure 22-15 0.5 × CAS setup time — Figure 22-12 – 10 WAIT setup time — Figure 22-10 WAIT hold time — BREQ setup time —...
Page 718 ø to A CSD1 CS7 to CS0 RSD1 ACC4 RSD2 (read) ACC5 to D (read) WRD1 WRD2 HWR, LWR (write) WSW2 to D (write) Figure 22-9 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.2004 page 690 of 1016 REJ09B0138-0600H...
Page 719 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 22-10 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.2004 page 691 of 1016 REJ09B0138-0600H...
Page 720 ø to A CSD3 ACC4 CS5 to CS2 (RAS) CSD2 CASD CASD ACC1 ACC3 to D (read) WRD2 WRD2 HWR, LWR (write) to D (write) Figure 22-11 DRAM Bus Timing ø CSD2 CSD1 CS5 to CS2 (RAS) CASD CASD Figure 22-12 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.2004 page 692 of 1016 REJ09B0138-0600H...
Page 721 ø CSD2 CSD2 CS5 to CS2 (RAS) CASD CASD Figure 22-13 Self-Refresh Timing or T ø to A RSD2 (read) ACC3 to D (read) Figure 22-14 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 693 of 1016 REJ09B0138-0600H...
Page 722 or T ø to A RSD2 (read) ACC1 to D (read) Figure 22-15 Burst ROM Access Timing (One-State Access) ø BRQS BRQS BREQ BACD BACD BACK to A CS7 to CS0, AS, RD, HWR, LWR, Figure 22-16 External Bus Release Timing Rev.6.00 Oct.28.2004 page 694 of 1016 REJ09B0138-0600H...
Page 723 ø BRQOD BRQOD BREQO Figure 22-17 External Bus Request Output Timing (4) DMAC Timing Table 22-7 lists the DMAC timing. Table 22-7 DMAC Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø...
Page 724 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) DACD2 DACD1 DACK0 , DACK1 Figure 22-18 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 696 of 1016 REJ09B0138-0600H...
Page 725 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) DACD2 DACD1 DACK0, DACK1 Figure 22-19 DMAC Single Address Transfer Timing (Three-State Access) or T ø TEND0, TEND1 Figure 22-20 DMAC TEND Output Timing ø...
Page 726 (5) Timing of On-Chip Supporting Modules Table 22-8 lists the timing of on-chip supporting modules. Table 22-8 Timing of On-Chip Supporting Modules = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø...
Page 727 ø Ports 1 to 6, A to G (read) Ports 1 to 3, 5, 6, A to G (write) Figure 22-22 I/O Port Input/Output Timing ø PO15 to PO0 Figure 22-23 PPG Output Timing ø TOCD Output compare output * TICS Input capture input*...
Page 728 ø TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 22-25 TPU Clock Input Timing ø TMOD TMO0, TMO1 Figure 22-26 8-Bit Timer Output Timing ø TMCS TMCS TMCI0, TMCI1 TMCWL TMCWH Figure 22-27 8-Bit Timer Clock Input Timing ø TMRS TMRI0, TMRI1 Figure 22-28 8-Bit Timer Reset Input Timing SCKW...
Page 729: A/D Conversion Characteristics
SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 22-30 SCI Input/Output Timing (Clock Synchronous Mode) ø TRGS ADTRG Figure 22-31 A/D Converter External Trigger Input Timing 22.1.4 A/D Conversion Characteristics Table 22-9 lists the A/D conversion characteristics. Table 22-9 A/D Conversion Characteristics = 5.0 V ±...
Page 730: D/A Conversion Characteristics
22.1.5 D/A Conversion Characteristics Table 22-10 lists the D/A conversion characteristics. Table 22-10 D/A Conversion Characteristics = 5.0 V ± 10%, V Conditions: V = AV = 4.5 V to AV = AV = 0 V, φ = 10 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Item...
Page 731: Electrical Characteristics Of H8S/2398 F-Ztat
22.3 Electrical Characteristics of H8S/2398 F-ZTAT 22.3.1 Absolute Maximum Ratings Table 22-11 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (except port 4) –0.3 to + V +0.3 Input voltage (port 4) –0.3 to AV +0.3 Reference voltage –0.3 to AV...
Page 732: Dc Characteristics
22.3.2 DC Characteristics Table 22-12 lists the DC characteristics. Table 22-13 lists the permissible output currents. Table 22-12 DC Characteristics = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: V = 4.5 V to AV = AV = 0 V* = -20 to +75°C (regular specifications), T...
Page 733 Item Symbol Unit Test Conditions Current Normal — f = 20 MHz dissipation* operation (5.0 V) Sleep mode — f = 20 MHz (5.0 V) µA ≤ 50°C Standby — 0.01 mode* — — 50°C < T Analog power During A/D —...
Page 734: Ac Characteristics
The chip 2 kΩ Port Darlington Pair Figure 22-33 Darlington Pair Drive Circuit (Example) The chip 600 Ω Ports 1, A to C Figure 22-34 LED Drive Circuit (Example) 22.3.3 AC Characteristics Figure 22-35 show, the test conditions for the AC characteristics. C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G LSI output pin...
Page 735 (1) Clock Timing Table 22-14 lists the clock timing Table 22-14 Clock Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø = 10 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition...
Page 736 EXTAL DEXT DEXT STBY OSC1 OSC1 ø Figure 22-37 Oscillator Settling Timing (2) Control Signal Timing Table 22-15 lists the control signal timing. Table 22-15 Control Signal Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV...
Page 737 ø RESS RESS RESW Figure 22-38 Reset Input Timing ø NMIS NMIH NMIW IRQW IRQS IRQH Edge input IRQS Level input Figure 22-39 Interrupt Input Timing Rev.6.00 Oct.28.2004 page 709 of 1016 REJ09B0138-0600H...
Page 738 (3) Bus Timing Table 22-16 lists the bus timing. Table 22-16 Bus Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø= 10 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition...
Page 739 Condition Test Item Symbol Unit Conditions 0.5 × WR hold time — Figure 22-40 to – 10 Figure 22-47 0.5 × CAS setup time — Figure 22-44 – 10 WAIT setup time — Figure 22-42 WAIT hold time — BREQ setup time —...
Page 740 ø to A CSD1 CS7 to CS0 RSD1 ACC4 RSD2 (read) ACC5 to D (read) WRD1 WRD2 HWR, LWR (write) WSW2 to D (write) Figure 22-41 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.2004 page 712 of 1016 REJ09B0138-0600H...
Page 741 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 22-42 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.2004 page 713 of 1016 REJ09B0138-0600H...
Page 742 ø to A CSD3 ACC4 CS5 to CS2 (RAS) CSD2 CASD CASD ACC1 ACC3 to D (read) WRD2 WRD2 HWR, LWR (write) to D (write) Figure 22-43 DRAM Bus Timing ø CSD2 CSD1 CS5 to CS2 (RAS) CASD CASD Figure 22-44 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.2004 page 714 of 1016 REJ09B0138-0600H...
Page 743 ø CSD2 CSD2 CS5 to CS2 (RAS) CASD CASD Figure 22-45 Self-Refresh Timing or T ø to A RSD2 (read) ACC3 to D (read) Figure 22-46 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 715 of 1016 REJ09B0138-0600H...
Page 744 or T ø to A RSD2 (read) ACC1 to D (read) Figure 22-47 Burst ROM Access Timing (One-State Access) ø BRQS BRQS BREQ BACD BACD BACK to A CS7 to CS0, AS, RD, HWR, LWR, Figure 22-48 External Bus Release Timing Rev.6.00 Oct.28.2004 page 716 of 1016 REJ09B0138-0600H...
Page 745 ø BRQOD BRQOD BREQO Figure 22-49 External Bus Request Output Timing (4) DMAC Timing Table 22-17 lists the DMAC timing. Table 22-17 DMAC Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø...
Page 746 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) DACD2 DACD1 DACK0 , DACK1 Figure 22-50 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 718 of 1016 REJ09B0138-0600H...
Page 747 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) DACD2 DACD1 DACK0, DACK1 Figure 22-51 DMAC Single Address Transfer Timing (Three-State Access) or T ø TEND0, TEND1 Figure 22-52 DMAC TEND Output Timing ø...
Page 748 (5) Timing of On-Chip Supporting Modules Table 22-18 lists the timing of on-chip supporting modules. Table 22-18 Timing of On-Chip Supporting Modules = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0 V, ø...
Page 749 ø Ports 1 to 6, A to G (read) Ports 1 to 3, 5, 6, A to G (write) Figure 22-54 I/O Port Input/Output Timing ø PO15 to PO0 Figure 22-55 PPG Output Timing ø TOCD Output compare output * TICS Input capture input*...
Page 750 ø TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 22-57 TPU Clock Input Timing ø TMOD TMO0, TMO1 Figure 22-58 8-Bit Timer Output Timing ø TMCS TMCS TMCI0, TMCI1 TMCWL TMCWH Figure 22-59 8-Bit Timer Clock Input Timing ø TMRS TMRI0, TMRI1 Figure 22-60 8-Bit Timer Reset Input Timing SCKW...
Page 751: A/D Conversion Characteristics
SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 22-62 SCI Input/Output Timing (Clock Synchronous Mode) ø TRGS ADTRG Figure 22-63 A/D Converter External Trigger Input Timing 22.3.4 A/D Conversion Characteristics Table 22-19 lists the A/D conversion characteristics. Table 22-19 A/D Conversion Characteristics = 5.0 V ±...
Page 752: D/A Conversion Characteristics
22.3.5 D/A Conversion Characteristics Table 22-20 lists the D/A conversion characteristics. Table 22-20 D/A Conversion Characteristics = 5.0 V ± 10%, V Conditions: V = AV = 4.5 V to AV = AV = 0 V, φ = 10 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Item...
Page 753 Test Item Symbol Min Unit Condition θ µs Programming Wait time after SWE bit clear* — — Maximum programming — — 1000* Times count* µs Erase Wait time after SWE bit — — setting* µs Wait time after ESU bit —...
Page 754 Table 22-22 Flash Memory Characteristics (HD64F2398F20T, HD64F2398TE20T) = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Conditions: = 4.5 V to AV = AV = 0V = 0 to +75°C (Programming/erasing operating temperature, regular specifications), T = 0 to + 85°C (Programming/erasing operating temperature, wide-range specifications) Test Item...
Page 755: Notes On Use
5. The maximum writing count (N) must be set to the maximum writing time (t (max)) or less according the actual set value (z). Wait time (z) must be switched after setting of bit P according to writing count (n). Writing count n 1 ≤...
Page 756: Electrical Characteristics Of H8S/2357 Masked Rom And Ztat Versions, And H8S/2352
22.6 Electrical Characteristics of H8S/2357 Masked ROM and ZTAT Versions, and H8S/2352 22.6.1 Absolute Maximum Ratings Table 22-23 lists the absolute maximum ratings. Table 22-23 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Programming voltage* –0.3 to +13.5 Input voltage (except port 4) –0.3 to V...
Page 757 Item Symbol Unit Test Conditions RES, STBY, Input low –0.3 — voltage to MD NMI, EXTAL, –0.3 — Ports 1, 3 to 5, B to G, to P6 to PA = –200 µA Output high All output pins V – 0.5 — —...
Page 758 Table 22-24 DC Characteristics (2) Conditions: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 V to AV = AV = 0 V* = –20 to +75°C (regular specifications), T = –40 to +85°C (wide-range specifications) Item Symbol Unit...
Page 759 Item Symbol Unit Test Conditions Current Normal — f = 10 MHz dissipation* operation (3.0 V) Sleep mode — f = 10 MHz (3.0 V) µA ≤ 50°C Standby — 0.01 mode* — — 20.0 50°C < T Analog power During A/D —...
Page 760 Item Symbol Unit Test Conditions = –200 µA Output high All output pins V – 0.5 — — voltage – 1.0 — — = –1 mA Output low All output pins V — — = 1.6 mA voltage ≤ 4.0 V Ports 1, A to C —...
Page 761 Table 22-25 Permissible Output Currents Conditions: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 to AV = AV = 0 V, = –20 to +75°C (regular specifications), T = –40 to +85°C (wide-range specifications) Item Symbol Unit...
Page 762: Ac Characteristics
22.6.3 AC Characteristics Figure 22-67 show, the test conditions for the AC characteristics. C = 90 pF: Ports 1, A to F C = 30 pF: Ports 2, 3, 5, 6, G LSI output pin = 2.4 kΩ = 12 kΩ I/O timing test levels •...
Page 763 ø Figure 22-68 System Clock Timing EXTAL DEXT DEXT STBY OSC1 OSC1 ø Figure 22-69 Oscillator Settling Timing Rev.6.00 Oct.28.2004 page 735 of 1016 REJ09B0138-0600H...
Page 764 (2) Control Signal Timing Table 22-27 lists the control signal timing. Table 22-27 Control Signal Timing Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 2 to 10 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) = 5.0 V ±...
Page 765 ø NMIH NMIS NMIW IRQi (i= 0 to 2) IRQW IRQS IRQH Edge input IRQS Level input Figure 22-71 Interrupt Input Timing Rev.6.00 Oct.28.2004 page 737 of 1016 REJ09B0138-0600H...
Page 766 (3) Bus Timing Table 22-28 lists the bus timing. Table 22-28 Bus Timing Condition A: V = 2.7 to 5.5 V, AV = 2.7 to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 2 to 10 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) = 5.0 V ±...
Page 767 Condition A Condition B Condition C Test Item Symbol Min Unit Conditions 1.5 × 1.5 × 1.5 × WR pulse width 2 — — — Figure 22-72 WSW2 – 40 – 20 – 40 Figure 22-79 Write data delay time t —...
Page 768 ø to A CSD1 CS7 to CS0 RSD2 RSD1 ACC2 (read) ACC3 to D (read) WRD2 WRD2 HWR, LWR (write) WSW1 to D (write) Figure 22-72 Basic Bus Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 740 of 1016 REJ09B0138-0600H...
Page 769 ø to A CSD1 CS7 to CS0 RSD1 ACC4 RSD2 (read) ACC5 to D (read) WRD1 WRD2 HWR, LWR (write) WSW2 to D (write) Figure 22-73 Basic Bus Timing (Three-State Access) Rev.6.00 Oct.28.2004 page 741 of 1016 REJ09B0138-0600H...
Page 770 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) WAIT Figure 22-74 Basic Bus Timing (Three-State Access with One Wait State) Rev.6.00 Oct.28.2004 page 742 of 1016 REJ09B0138-0600H...
Page 771 ø to A CSD3 ACC4 CS5 to CS2 (RAS) CSD2 CASD CASD ACC1 ACC3 to D (read) WRD2 WRD2 HWR, LWR (write) to D (write) Figure 22-75 DRAM Bus Timing ø CSD2 CSD1 CS5 to CS2 (RAS) CASD CASD Figure 22-76 CAS-Before-RAS Refresh Timing Rev.6.00 Oct.28.2004 page 743 of 1016 REJ09B0138-0600H...
Page 772 ø CSD2 CSD2 CS5 to CS2 (RAS) CASD CASD Figure 22-77 Self-Refresh Timing or T ø to A RSD2 (read) ACC3 to D (read) Figure 22-78 Burst ROM Access Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 744 of 1016 REJ09B0138-0600H...
Page 773 or T ø to A RSD2 (read) ACC1 to D (read) Figure 22-79 Burst ROM Access Timing (One-State Access) ø BRQS BRQS BREQ BACD BACD BACK to A CS7 to CS0, AS, RD, HWR, LWR, Figure 22-80 External Bus Release Timing Rev.6.00 Oct.28.2004 page 745 of 1016 REJ09B0138-0600H...
Page 774 ø BRQOD BRQOD BREQO Figure 22-81 External Bus Request Output Timing (4) DMAC Timing Table 22-29 lists the DMAC timing. Table 22-29 DMAC Timing Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0V, ø...
Page 775 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) DACD2 DACD1 DACK0 , DACK1 Figure 22-82 DMAC Single Address Transfer Timing (Two-State Access) Rev.6.00 Oct.28.2004 page 747 of 1016 REJ09B0138-0600H...
Page 776 ø to A CS7 to CS0 (read) to D (read) HWR, LWR (write) to D (write) DACD2 DACD1 DACK0, DACK1 Figure 22-83 DMAC Single Address Transfer Timing (Three-State Access) or T ø TEND0, TEND1 Figure 22-84 DMAC TEND Output Timing ø...
Page 777 (5) Timing of On-Chip Supporting Modules Table 22-30 lists the timing of on-chip supporting modules. Table 22-30 Timing of On-Chip Supporting Modules Condition A: V = 2.7 V to 5.5 V, AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø...
Page 778 Condition A Condition B Condition C Test Item Symbol Min Max Unit Conditions Transmit data delay — — — Figure 22-95 time Receive data setup — — — time (synchronous) Receive data hold — — — time (synchronous) Trigger input setup —...
Page 779 ø TOCD Output compare output * TICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22-88 TPU Input/Output Timing ø TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 22-89 TPU Clock Input Timing ø...
Page 780 ø TMRS TMRI0, TMRI1 Figure 22-92 8-Bit Timer Reset Input Timing ø WOVD WOVD WDTOVF Figure 22-93 WDT Output Timing SCKW SCKr SCKf SCK0 to SCK2 Scyc Figure 22-94 SCK Clock Input Timing SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 22-95 SCI Input/Output Timing (Clock Synchronous Mode)
Page 781: A/D Conversion Characteristics
22.6.4 A/D Conversion Characteristics Table 22-31 lists the A/D conversion characteristics. Table 22-31 A/D Conversion Characteristics Condition A: V = AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 2 to 10 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) = 5.0 V ±...
Page 782: D/A Convervion Characteristics
22.6.5 D/A Convervion Characteristics Table 22-32 lists the D/A conversion characteristics Table 22-32 D/A Conversion Characteristics Condition A: V = AV = 2.7 V to 5.5 V, V = 2.7 V to AV = AV = 0 V, ø = 2 to 10 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) = 5.0 V ±...
Page 783: Electrical Characteristics Of H8S/2357 F-Ztat Version
22.7 Electrical Characteristics of H8S/2357 F-ZTAT Version 22.7.1 Absolute Maximum Ratings Table 22-33 lists the absolute maximum ratings. Table 22-33 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +7.0 Input voltage (FWE)* –0.3 to V +0.3 Input voltage (except port 4)* –0.3 to V +0.3...
Page 784 Item Symbol Unit Test Conditions Input low NMI, EXTAL, –0.3 — voltage Ports 1, 3 to 5, B to G, to P6 to PA = –200 µA Output high All output pins V – 0.5 — — voltage — — = –1 mA Output low All output pins V...
Page 785 Table 22-34 DC Characteristics (2) Conditions: V = 3.0 to 5.5 V, AV = 3.0 to 5.5 V, V = 3.0 V to AV = AV = 0 V* = –20 to +75°C (regular specifications), T = –40 to +85°C (wide-range specifications) Item Symbol Unit...
Page 786 Item Symbol Unit Test Conditions Current Normal — f = 13 MHz dissipation* operation (3.3 V) Sleep mode — f = 13 MHz (3.3 V) µA ≤ 50°C Standby — 0.01 mode* — — 50°C < T 0°C ≤ T ≤...
Page 787: Ac Characteristics
22.7.3 AC Characteristics (1) Clock Timing Table 22-36 lists the clock timing Table 22-36 Clock Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Condition B: V = 4.5 V to AV = AV = 0 V, ø = 2 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition C: V...
Page 788 (2) Control Signal Timing Table 22-37 lists the control signal timing. Table 22-37 Control Signal Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Condition B: V = 4.5 V to AV = AV = 0 V, ø = 2 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition C: V...
Page 789 (3) Bus Timing Table 22-38 lists the bus timing. Table 22-38 Bus Timing = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Condition B: V = 4.5 V to AV = AV = 0 V, ø= 2 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition C: V...
Page 790 Condition B Condition C Item Symbol Unit Test Conditions Write data delay time — — Figure 22-72 to Figure 22-79 0.5 × 0.5 × Write data setup time — — – 20 – 36 0.5 × 0.5 × Write data hold time —...
Page 791 (5) Timing of On-Chip Supporting Modules Table 22-40 lists the timing of on-chip supporting modules. Table 22-40 Timing of On-Chip Supporting Modules = 5.0 V ± 10%, AV = 5.0 V ± 10%, V Condition B: V = 4.5 V to AV = AV = 0 V, ø...
Page 792: A/D Conversion Characteristics
Condition B Condition C Test Item Symbol Min Unit Conditions Transmit data delay — — Figure 22-95 time Receive data setup — — time (synchronous) Receive data hold — — time (synchronous) Trigger input setup — — Figure 22-96 TRGS converter time 22.7.4...
Page 793: D/A Conversion Characteristics
22.7.5 D/A Conversion Characteristics Table 22-42 lists the D/A conversion characteristics Table 22-42 D/A Conversion Characteristics = 5.0 V ± 10%, V Condition B: V = AV = 4.5 V to AV = AV = 0 V, ø = 2 to 20 MHz, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Condition C: V...
Page 794 Test Item Symbol Min Unit Condition η µs Programming Wait time after PV bit clear* — — z = 200 µs Maximum programming — — 1000* Times count* µs Erase Wait time after SWE bit — — setting* µs Wait time after ESU bit —...
Page 795 Test Item Symbol Min Unit Condition µs Programming Wait time after SWE bit — — setting* µs Wait time after PSU bit — — setting* µs Wait time after P bit — setting* α µs Wait time after P bit clear* —...
Page 796: Usage Note
22.8 Usage Note Although the ZTAT, F-ZTAT, and masked ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects.
Page 797: Appendix A Instruction Set
Appendix A Instruction Set Instruction List Operand Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-and-accumulate register (32-bit register)* (EAd) Destination operand (EAs) Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
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Page 820: Instruction Codes
Instruction Codes Table A-2 shows the instruction codes. Rev.6.00 Oct.28.2004 page 792 of 1016 REJ09B0138-0600H...
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Page 834: Operation Code Map
Operation Code Map Table A-3 shows the operation code map. Rev.6.00 Oct.28.2004 page 806 of 1016 REJ09B0138-0600H...
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Page 838: Number Of States Required For Instruction Execution
Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle.
Page 839 Table A-5 Number of Cycles in Instruction Execution Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd...
Page 840 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16...
Page 841 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16...
Page 842 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16...
Page 843 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic JMP @ERn JMP @aa:24 JMP @@aa:8 Advanced JSR @ERn Advanced JSR @aa:24 Advanced JSR @@aa:8 Advanced LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR...
Page 844 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd)
Page 845 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH PUSH.W Rn...
Page 846 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd...
Page 847 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd Cannot be used in the H8S/2357 Group STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd...
Page 848: Bus States During Instruction Execution
Bus States during Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction Internal operation JMP@aa:24 R:W 2nd R:W EA...
Page 849 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ø Address bus HWR, LWR High level Internal R:W 2nd R:W EA...
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Page 862: Condition Code Modification
Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand...
Page 863 Table A-7 Condition Code Modification Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 864 Instruction Definition N = Rm Z = Rm · Rm–1 · ..· R0 C: decimal arithmetic carry N = Rm Z = Rm · Rm–1 · ..· R0 C: decimal arithmetic borrow — — N = Rm Z = Rm · Rm–1 · ..· R0 V = Dm ·...
Page 865 Instruction Definition — — N = Rm Z = Rm · Rm–1 · ..· R0 — — N = Rm Z = Rm · Rm–1 · ..· R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. —...
Page 866 Instruction Definition STMAC Cannot be used in the H8S/2357 Group H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 867: Appendix B Internal I/O Register
Appendix B Internal I/O Register Addresses Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’F800 16/32* bits H’FBFF CHNE DISEL — — — —...
Page 868 Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FEA0 TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU5 16 bits H’FEA1 TMDR5 —...
Page 869 Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FEE0 MAR0AH — — — — — — — — DMAC 16 bits H’FEE1 H’FEE2 MAR0AL H’FEE3 H’FEE4...
Page 870 Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width Short H’FF06 FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A 16 bits DMABCRH address mode Full FAE1 FAE0...
Page 871 Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FF5E PORTF Port 8 bits H’FF5F PORTG — — — H’FF60 P1DR P17DR P16DR P15DR P14DR P13DR P12DR...
Page 872 Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FF8C SSR2 TDRE RDRF ORER FER/ TEND MPBT SCI2, 8 bits ERS* Smart Card interface 2 H’FF8D RDR2 H’FF8E...
Page 873 Address Register Data Bus (low) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 16 bits H’FFD1 TMDR0 —...
Page 874 6. Applies to the H8S/2357 ZTAT only. 7. Applies to the H8S/2357 F-ZTAT only. 8. Applies to the H8S/2398 F-ZTAT only. Rev.6.00 Oct.28.2004 page 846 of 1016 REJ09B0138-0600H...
Page 875: Functions
Functions MRA—DTC Mode Register A H'F800—H'FBFF Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — DTC Data Transfer Size Byte-size transfer Word-size transfer DTC Transfer Mode Select Destination side is repeat area or block area Source side is repeat area or block area...
Page 876 MRB—DTC Mode Register B H'F800—H'FBFF CHNE DISEL — — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — Reserved Only 0 should be written to these bits DTC Interrupt Select After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0...
Page 877 CRB—DTC Transfer Count Register B H'F800—H'FBFF Initial value Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined Read/Write —...
Page 878 TMDR3—Timer Mode Register 3 H'FE81 TPU3 — — Initial value Read/Write — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 × ×...
Page 879 TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 Initial value IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Read/Write TGR3A I/O Control TGR3A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled Initial output is...
Page 880 TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TRG3C I/O Control TGR3C Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 881 TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value Read/Write — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB)
Page 882 TSR3—Timer Status Register 3 H'FE85 TPU3 — — — TCFV TGFD TGFC TGFB TGFA Initial value Read/Write — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 883 TGR3A—Timer General Register 3A H'FE88 TPU3 TGR3B—Timer General Register 3B H'FE8A TPU3 TGR3C—Timer General Register 3C H'FE8C TPU3 TGR3D—Timer General Register 3D H'FE8E TPU3 Initial value Read/Write TCR4—Timer Control Register 4 H'FE90 TPU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write...
Page 884 TMDR4—Timer Mode Register 4 H'FE91 TPU4 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 885 TIOR4—Timer I/O Control Register 4 H'FE92 TPU4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR4A I/O Control TGR4A Output disabled is output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 886 TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value — — Read/Write — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by...
Page 887 TSR4—Timer Status Register 4 H'FE95 TPU4 TCFD — TCFU TCFV — — TGFB TGFA Initial value — Read/Write R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 888 TGR4A—Timer General Register 4A H'FE98 TPU4 TGR4B—Timer General Register 4B H'FE9A TPU4 Initial value Read/Write TCR5—Timer Control Register 5 H'FEA0 TPU5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64...
Page 889 TMDR5—Timer Mode Register 5 H'FEA1 TPU5 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 890 TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR5A I/O Control TGR5A Output disabled is output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
Page 891 TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB)
Page 892 TSR5—Timer Status Register 5 H'FEA5 TPU5 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 893 TGR5A—Timer General Register 5A H'FEA8 TPU5 TGR5B—Timer General Register 5B H'FEAA TPU5 Initial value Read/Write P1DDR—Port 1 Data Direction Register H'FEB0 Port 1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value Read/Write Specify input or output for individual port 1 pins P2DDR—Port 2 Data Direction Register H'FEB1 Port 2...
Page 894 P6DDR—Port 6 Data Direction Register H'FEB5 Port 6 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write Specify input or output for individual port 6 pins PADDR—Port A Data Direction Register H'FEB9 Port A PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR...
Page 895 PDDDR—Port D Data Direction Register H'FEBC Port D [On-chip ROM version Only] PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value Read/Write Specify input or output for individual port D pins PEDDR—Port E Data Direction Register H'FEBD Port E PE7DDR PE6DDR PE5DDR...
Page 896 IPRA — Interrupt Priority Register A H'FEC4 Interrupt Controller IPRB — Interrupt Priority Register B H'FEC5 Interrupt Controller IPRC — Interrupt Priority Register C H'FEC6 Interrupt Controller IPRD — Interrupt Priority Register D H'FEC7 Interrupt Controller IPRE — Interrupt Priority Register E H'FEC8 Interrupt Controller IPRF —...
Page 897 ABWCR—Bus Width Control Register H'FED0 Bus Controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value Mode 4 Initial value Read/Write Area 7 to 0 Bus Width Control Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Note: * Modes 6 and 7 are provided in the On-chip ROM version only.
Page 898 WCRH—Wait Control Register H H'FED2 Bus Controller Initial value Read/Write Area 4 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 5 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted...
Page 899 WCRL—Wait Control Register L H'FED3 Bus Controller Initial value Read/Write Area 0 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 1 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted...
Page 900 BCRH—Bus Control Register H H'FED4 Bus Controller ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 Initial value Read/Write RAM Type Select RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 Normal space DRAM Normal space space Normal DRAM space space DRAM space —...
Page 901 BCRL—Bus Control Register L H'FED5 Bus Controller BRLE BREQOE LCASS — WDBE WAITE Initial value Read/Write WAIT Pin Enable Wait input by WAIT pin disabled Wait input by WAIT pin enabled Write Data Buffer Enable Write data buffer function not used Write data buffer function used Reserved Only 1 should be written to this bit...
Page 902 MCR—Memory Control Register H'FED6 Bus Controller RCDM MXC1 MXC0 RLW1 RLW0 Initial value Read/Write Refresh Cycle Wait Control No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted Multiplex Shift Count 8-bit shift 9-bit shift 10-bit shift —...
Page 903 DRAMCR—DRAM Control Register H'FED7 Bus Controller RFSHE RMODE CMIE CKS2 CKS1 CKS0 Initial value Read/Write Refresh Counter Clock Select Count operation disabled Count uses ø/2 Count uses ø/8 Count uses ø/32 Count uses ø/128 Count uses ø/512 Count uses ø/2048 Count uses ø/4096 Compare Match Interrupt Enable Interrupt request (CMI) by CMF flag disabled...
Page 904 RTCOR—Refresh Time Constant Register H'FED9 Bus Controller Initial value Read/Write Sets the period for compare match operations with RTCNT RAMER—RAM Emulation Register H'FEDB Bus Controller [for H8S/2398F-ZTAT Only] — — — — RAMS RAM2 RAM1 RAM0 Initial value Read/Write — —...
Page 905 RAMER—RAM Emulation Register H'FEDB Bus Controller (for H8S/2357F-ZTAT only) — — — — — RAMS RAM1 RAM0 Initial value Read/Write — — — — — RAM Select, Flash Memory Area RAMS RAM1 RAM0 Area × × H'FFDC00 to H'FFDFFF H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF...
Page 906 ETCR0A—Transfer Count Register 0A H'FEE6 DMAC ETCR0A Initial value Read/Write Sequential Transfer counter mode Idle mode Normal mode Repeat mode Transfer number storage register Transfer counter Block transfer mode Block size storage register Block size counter * : Undefined MAR0BH—Memory Address Register 0BH H'FEE8 DMAC MAR0BL—Memory Address Register 0BL...
Page 907 ETCR0B—Transfer Count Register 0B H'FEEE DMAC ETCR0B Initial value Read/Write Sequential mode and Transfer counter idle mode Repeat mode Transfer number storage register Transfer counter Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. MAR1AH—Memory Address Register 1AH H'FEF0 DMAC...
Page 908 ETCR1A—Transfer Count Register 1A H'FEF6 DMAC ETCR1A Initial value Read/Write Sequential mode Transfer counter Idle mode Normal mode Repeat mode Transfer number storage register Transfer counter Block transfer mode Block size storage register Block size counter * : Undefined MAR1BH — Memory Address Register 1BH H'FEF8 DMAC MAR1BL —...
Page 909 IOAR1B—I/O Address Register 1B H'FEFC DMAC IOAR1B Initial value Read/Write * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1B—Transfer Count Register 1B H'FEFE DMAC ETCR1B Initial value Read/Write Sequential mode and idle mode Transfer counter Repeat mode...
Page 910 DMAWER—DMA Write Enable Register H'FF00 DMAC DMAWER — — — — WE1B WE1A WE0B WE0A Initial value Read/Write — — — — Write Enable 0A Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled...
Page 911 DMATCR—DMA Terminal Control Register H'FF01 DMAC DMATCR — — TEE1 TEE0 — — — — Initial value Read/Write — — — — — — Transfer End Enable 0 TEND0 pin output disabled TEND0 pin output enabled Transfer End Enable 1 TEND1 pin output disabled TEND1 pin output enabled DMACR0A—DMA Control Register 0A...
Page 912 Full address mode (cont) — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 DMACRB Initial value Read/Write Reserved Reserved Only 0 should be Only 0 should be written to this bit. written to this bit. Data Transfer Factor Normal Mode Block Transfer Mode —...
Page 913 Short address mode DMACR DTSZ DTID DTDIR DTF3 DTF2 DTF1 DTF0 Initial value Read/Write Data Transfer Factor Channel A Channel B — Data Transfer Direction Activated by A/D converter conversion Dual address mode: Transfer with end interrupt MAR as source address and IOAR as destination address —...
Page 914 DMABCRH — DMA Band Control Register H'FF06 DMAC DMABCRL — DMA Band Control Register H'FF07 DMAC Full address mode FAE1 FAE0 — — DTA1 — DTA0 — DMABCRH Initial value Read/Write Reserved Reserved Reserved Only 0 should be Only 0 should be Only 0 should be written to this bit.
Page 915 Full address mode (cont) DMABCRL DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value Read/Write Channel 0 Data Transfer Interrupt Enable A Transfer end interrupt disabled Transfer end interrupt enabled Channel 0 Data Transfer Interrupt Enable B Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 1 Data Transfer Interrupt Enable A...
Page 916 Short address mode DMABCRH FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value Read/Write Channel 0A Data Transfer Acknowledge Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Data Transfer Acknowledge Clearing of selected internal interrupt source...
Page 917 Short address mode (cont) DMABCRL DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Initial value Read/Write Channel 0A Data Transfer Interrupt Enable Transfer end interrupt disabled Transfer end interrupt enabled Channel 0B Data Transfer Interrupt Enable Transfer end interrupt disabled Transfer end interrupt enabled Channel 1A Data Transfer Interrupt Enable...
Page 918 ISCRH — IRQ Sense Control Register H H'FF2C Interrupt Controller ISCRL — IRQ Sense Control Register L H'FF2D Interrupt Controller ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value Read/Write IRQ7 to IRQ4 Sense Control ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB...
Page 919 ISR—IRQ Status Register H'FF2F Interrupt Controller IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing. DTCERA to DTCERF—DTC Enable Registers H'FF30 to H'FF35 DTCE7...
Page 920 DTVECR—DTC Vector Register H'FF37 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value Read/Write R/(W)* Sets vector number for DTC software activation DTC Software Activation Enable DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions]...
Page 921 SBYCR—Standby Control Register H'FF38 Power-Down State SSBY STS2 STS1 STS0 — — — Initial value Read/Write — — Reserved Only 0 should be written to this bit Output Port Enable In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state Standby Timer Select...
Page 922 SYSCR—System Control Register H'FF39 — — INTM1 INTM0 NMIEG — — RAME Initial value Read/Write — —/(R/W) RAM Enable On-chip RAM disabled On-chip RAM enabled Reserved Only 0 should be written to this bit Reserved for H8S/2398, H8S/2394, H8S/2392, and H8S/2390. Only 0 should be written to this bit.
Page 923 SCKCR—System Clock Control Register H'FF3A Clock Pulse Generator PSTOP — — — — SCK2 SCK1 SCK0 Initial value Read/Write —/(R/W) — — Bus Master Clock Select Reserved for H8S/2398, Bus master is in high-speed mode H8S/2394, Medium-speed clock is ø/2 H8S/2392, and H8S/2390.
Page 924 SYSCR2—System Control Register 2 H'FF42 [F-ZTAT version Only] — — — — FLSHE — — — Initial value Read/Write — — — — — — — Flash memory control register enable Flash memory control register is not selected Flash memory control register is selected Note: SYSCR2 can only be accessed in the F-ZTAT version.
Page 925 PCR—PPG Output Control Register H'FF46 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G0CMS0 G1CMS0 G0CMS1 Initial value Read/Write Output Trigger for Pulse Output Group 0 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 1 Compare match in TPU channel 0...
Page 926 PMR—PPG Output Mode Register H'FF47 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value Read/Write Pulse Output Group n Normal/Non-Overlap Operation Select Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A...
Page 927 NDERH — Next Data Enable Registers H H'FF48 NDERL — Next Data Enable Registers L H'FF49 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Pulse Output Enable/Disable Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled NDERL NDER7 NDER6...
Page 928 PODRH — Output Data Register H H'FF4A PODRL — Output Data Register L H'FF4B PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Stores output data for use in pulse output PODRL POD7 POD6...
Page 929 NDRH—Next Data Register H H'FF4C (FF4E) (1) When pulse output group output triggers are the same (a) Address: H'FF4C NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Stores the next data for pulse output groups 3 and 2 (b) Address: H'FF4E —...
Page 930 NDRL—Next Data Register L H'FF4D (FF4F) (1) When pulse output group output triggers are the same (a) Address: H'FF4D NDR7 NDR6 NDR5 NDR4 NDR3 NDR0 NDR2 NDR1 Initial value Read/Write Stores the next data for pulse output groups 1 and 0 (b) Address: H'FF4F —...
Page 931 PORT1—Port 1 Register H'FF50 Port 1 Initial value —* —* —* —* —* —* —* —* Read/Write State of port 1 pins Note: * Determined by the state of pins P1 to P1 PORT2—Port 2 Register H'FF51 Port 2 Initial value —* —* —*...
Page 932 PORT5—Port 5 Register H'FF54 Port 5 — — — — Initial value Undefined Undefined Undefined Undefined —* —* —* —* Read/Write — — — — State of port 5 pins Note: * Determined by the state of pins P5 to P5 PORT6—Port 6 Register H'FF55 Port 6...
Page 933 PORTC—Port C Register H'FF5B Port C [On-chip ROM version Only)] Initial value —* —* —* —* —* —* —* —* Read/Write State of port C pins Note: * Determined by the state of pins PC to PC PORTD—Port D Register H'FF5C Port D [On-chip ROM version Only]...
Page 934 PORTG—Port G Register H'FF5F Port G — — — Initial value Undefined Undefined Undefined —* —* —* —* —* Read/Write — — — State of port G pins Note: * Determined by the state of pins PG to PG P1DR—Port 1 Data Register H'FF60 Port 1 P17DR...
Page 935 P5DR—Port 5 Data Register H'FF64 Port 5 — — — — P53DR P52DR P51DR P50DR Initial value Undefined Undefined Undefined Undefined Read/Write — — — — Stores output data for port 5 pins (P5 to P5 P6DR—Port 6 Data Register H'FF65 Port 6 P67DR...
Page 936 PCDR—Port C Data Register H'FF6B Port C PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value Read/Write Stores output data for port C pins (PC to PC PDDR—Port D Data Register H'FF6C Port D PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR...
Page 937 PGDR—Port G Data Register H'FF6F Port G — — — PG4DR PG3DR PG2DR PG1DR PG0DR Initial value Undefined Undefined Undefined Read/Write — — — Stores output data for port G pins (PG to PG PAPCR—Port A MOS Pull-Up Control Register H'FF70 Port A [On-chip ROM version Only]...
Page 938 PDPCR—Port D MOS Pull-Up Control Register H'FF73 Port D [On-chip ROM version Only] PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value Read/Write Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390. PEPCR—Port E MOS Pull-Up Control Register H'FF74 Port E...
Page 939 SMR0—Serial Mode Register 0 H'FF78 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock Select ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 1 stop bit 2 stop bits Parity Mode Even parity Odd parity Parity Enable...
Page 940 SMR0—Serial Mode Register 0 H'FF78 Smart Card Interface 0 STOP CKS1 CKS0 Initial value Read/Write Clock Select ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Setting prohibited Stop Bit Length Setting prohibited 2 stop bits Parity Mode Even parity Odd parity...
Page 941 BRR0—Bit Rate Register 0 H'FF79 SCI0, Smart Card Interface 0 Initial value Read/Write Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.2004 page 913 of 1016 REJ09B0138-0600H...
Page 942 SCR0—Serial Control Register 0 H'FF7A SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Asynchronous Internal clock/SCK pin functions as I/O port mode Internal clock/SCK pin functions Synchronous as serial clock output mode Asynchronous Internal clock/SCK pin functions mode as clock output* Internal clock/SCK pin functions Synchronous...
Page 943 SCR0—Serial Control Register 0 H'FF7A Smart Card Interface 0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable SCMR SCR setting SCK pin function SMIF C/A,GM CKE1 CKE0 See SCI specification Operates as port input Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK...
Page 944 SSR0—Serial Status Register 0 H'FF7C SCI0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition]...
Page 945 SSR0—Serial Status Register 0 H'FF7C Smart Card Interface 0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received...
Page 946 RDR0—Receive Data Register 0 H'FF7D SCI0, Smart Card Interface 0 Initial value Read/Write Stores received serial data SCMR0—Smart Card Mode Register 0 H'FF7E SCI0, Smart Card Interface 0 — — — — SDIR SINV — SMIF Initial value Read/Write — —...
Page 947 SMR1—Serial Mode Register 1 H'FF80 SCI1 STOP CKS1 CKS0 Initial value Read/Write Clock Select ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 1 stop bit 2 stop bits Parity Mode Even parity Odd parity Parity Enable...
Page 948 SMR1—Serial Mode Register 1 H'FF80 Smart Card Interface 1 STOP CKS1 CKS0 Initial value Read/Write Clock Select ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Setting prohibited Stop Bit Length Setting prohibited 2 stop bits Parity Mode Even parity Odd parity...
Page 949 BRR1—Bit Rate Register 1 H'FF81 SCI1, Smart Card Interface 1 Initial value Read/Write Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.2004 page 921 of 1016 REJ09B0138-0600H...
Page 950 SCR1—Serial Control Register 1 H'FF82 SCI1 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Internal clock/SCK pin functions Asynchronous as I/O port mode Synchronous Internal clock/SCK pin functions mode as serial clock output Asynchronous Internal clock/SCK pin functions mode as clock output* Synchronous Internal clock/SCK pin functions...
Page 951 SCR1—Serial Control Register 1 H'FF82 Smart Card Interface 1 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable SCMR SCR setting SCK pin function SMIF C/A,GM CKE1 CKE0 See SCI specification Operates as port input Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK...
Page 952 SSR1—Serial Status Register 1 H'FF84 SCI1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition]...
Page 953 SSR1—Serial Status Register 1 H'FF84 Smart Card Interface 1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received...
Page 954 RDR1—Receive Data Register 1 H'FF85 SCI1, Smart Card Interface 1 Initial value Read/Write Stores received serial data SCMR1—Smart Card Mode Register 1 H'FF86 SCI1, Smart Card Interface 1 — — — — SDIR SINV — SMIF Initial value Read/Write — —...
Page 955 SMR2—Serial Mode Register 2 H'FF88 SCI2 STOP CKS1 CKS0 Initial value Read/Write Clock Select ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 1 stop bit 2 stop bits Parity Mode Even parity Odd parity Parity Enable...
Page 956 SMR2—Serial Mode Register 2 H'FF88 Smart Card Interface 2 STOP CKS1 CKS0 Initial value Read/Write Clock Select ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode Multiprocessor function disabled Setting prohibited Stop Bit Length Setting prohibited 2 stop bits Parity Mode Even parity Odd parity...
Page 957 BRR2—Bit Rate Register 2 H'FF89 SCI2, Smart Card Interface 2 Initial value Read/Write Sets the serial transfer bit rate Note: See section 14.2.8, Bit Rate Register (BRR), for details. Rev.6.00 Oct.28.2004 page 929 of 1016 REJ09B0138-0600H...
Page 958 SCR2—Serial Control Register 2 H'FF8A SCI2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Internal clock/SCK pin functions Asynchronous as I/O port mode Synchronous Internal clock/SCK pin functions mode as serial clock output Asynchronous Internal clock/SCK pin functions mode as clock output* Synchronous Internal clock/SCK pin functions...
Page 959 SCR2—Serial Control Register 2 H'FF8A Smart Card Interface 2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable SCMR SCR setting SCK pin function SMIF C/A,GM CKE1 CKE0 See SCI specification Operates as port input Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK...
Page 960 SSR2—Serial Status Register 2 H'FF8C SCI2 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition]...
Page 961 SSR2—Serial Status Register 2 H'FF8C Smart Card Interface 2 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received...
Page 962 RDR2—Receive Data Register 2 H'FF8D SCI2, Smart Card Interface 2 Initial value Read/Write Stores received serial data SCMR2—Smart Card Mode Register 2 H'FF8E SCI2, Smart Card Interface 2 — — — — SDIR SINV — SMIF Initial value Read/Write — —...
Page 963 ADDRAH — A/D Data Register AH H'FF90 A/D Converter ADDRAL — A/D Data Register AL H'FF91 A/D Converter ADDRBH — A/D Data Register BH H'FF92 A/D Converter ADDRBL — A/D Data Register BL H'FF93 A/D Converter ADDRCH — A/D Data Register CH H'FF94 A/D Converter ADDRCL —...
Page 964 ADCSR—A/D Control/Status Register H'FF98 A/D Converter ADIE ADST SCAN Initial value Read/Write R/(W)* Channel Select Channel Group select select Single Mode Group Mode AN0, AN1 AN0 to AN2 AN0 to AN3 AN4, AN5 AN4 to AN6 AN4 to AN7 Group Select Conversion time= 266 states (max.) Conversion time= 134 states (max.) Scan Mode...
Page 965 ADCR—A/D Control Register H'FF99 TRGS1 TRGS0 — — — — — — Initial value Read/Write — — —/(R/W)* —/(R/W)* — — Timer Trigger Select Description TRGS1 TRGS1 A/D conversion start by external trigger is disabled A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Note: * Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390.
Page 966 DACR—D/A Control Register H'FFA6 DAOE1 DAOE0 — — — — — Initial value Read/Write — — — — — D/A Output Enable 0 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled...
Page 967 TCR0—Time Control Register 0 H'FFB0 8-Bit Timer Channel 0 TCR1—Time Control Register 1 H'FFB1 8-Bit Timer Channel 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select Clock input disabled Internal clock: counted at falling edge of ø/8 Internal clock: counted at falling edge of ø/64...
Page 968 TCSR0—Timer Control/Status Register 0 H'FFB2 8-Bit Timer Channel 0 TCSR1—Timer Control/Status Register 1 H'FFB3 8-Bit Timer Channel 1 TCSR0 CMFB CMFA ADTE Initial value Read/Write R/(W)* R/(W)* R/(W)* TCSR1 CMFB CMFA — Initial value R/(W)* R/(W)* R/(W)* — Read/Write Output Select No change when compare match A occurs 0 is output when compare...
Page 969 TCORA0—Time Constant Register A0 H'FFB4 8-Bit Timer Channel 0 TCORA1—Time Constant Register A1 H'FFB5 8-Bit Timer Channel 1 TCORA0 TCORA1 Initial value Read/Write TCORB0—Time Constant Register B0 H'FFB6 8-Bit Timer Channel 0 TCORB1—Time Constant Register B1 H'FFB7 8-Bit Timer Channel 1 TCORB0 TCORB1 Initial value...
Page 970 TCSR—Timer Control/Status Register H'FFBC (W), H'FFBC (R) WT/IT — — CKS2 CKS1 CKS0 Initial value Read/Write R/(W) — — Clock Select Overflow period* CKS2 CKS1 CKS0 Clock (when ø = 20 MHz) ø/2 (initial value) 25.6µs ø/64 819.2µs ø/128 1.6ms ø/512 6.6ms ø/2,048...
Page 971 TCNT—Timer Counter H'FFBC (W), H'FFBD (R) Initial value Read/Write TCNT is an 8-bit readable/writable* up-counter. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 13.2.4, Notes on Register Access. RSTCSR—Reset Control/Status Register H'FFBE (W) , H'FFBF (R) WOVF RSTE RSTS...
Page 972 TSTR—Timer Start Register H'FFC0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value Read/Write — — Counter Start TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
Page 973 FLMCR1—Flash Memory Control Register 1 H'FFC8 FLASH (For the H8S/2357 F-ZTAT) — — Initial value —* Read/Write — — Program Clears program mode Program mode is entered [Setting condition] FWE=1, SWE=1, and PSU=1 Erase Clears erase mode Erase mode is entered [Setting condition] FWE=1, SWE=1, and ESU=1 Program Verify...
Page 974 FLMCR2—Flash Memory Control Register 2 H'FFC9 FLASH (For the H8S/2357 F-ZTAT) FLER — — — — — Initial value Read/Write — — — — — Program Setup Clears program setup Program setup [Setting condition] FWE=1 and SWE=1 Erase Setup Clears erase setup Erase setup [Setting condition] FWE=1 and SWE=1...
Page 975 EBR1—Erase Block Specification Register 1 H'FFCA FLASH (For the H8S/2357 F-ZTAT) EBR2— Erase Block Specification Register 2 H'FFCB FLASH (For the H8S/2357 F-ZTAT) EBR1 — — — — — — Initial value Read/Write — — — — — — EBR2 Initial value Read/Write Deviding Erase Blocks...
Page 976 FLMCR1—Flash Memory Control Register 1 H'FFC8 FLASH (For the H8S/2398 F-ZTAT) Initial value Read/Write Program 1* Clears program mode Program mode is entered [Setting condition] SWE=1 and PSU=1 Erase 1* Clears erase mode Erase mode is entered [Setting condition] SWE=1 and ESU=1 Program Verify 1* Clears program verify mode Program verify mode is entered...
Page 977 FLMCR2—Flash Memory Control Register 2 H'FFC9 FLASH (For the H8S/2398 F-ZTAT) FLER — — — — — — — Initial value Read/Write — — — — — — — Flash Memory Error Flash memory operates normally. Writing/erasing protect (error protect) to flash memory is disabled.
Page 978 TCR0—Timer Control Register 0 H'FFD0 TPU0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 979 TMDR0—Timer Mode Register 0 H'FFD1 TPU0 — — Initial value Read/Write — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 × ×...
Page 980 TIOR0H—Timer I/O Control Register 0H H'FFD2 TPU0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR0A I/O Control TGR0A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled Initial output is...
Page 981 TIOR0L—Timer I/O Control Register 0L H'FFD3 TPU0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TGR0C I/O Control TGR0C Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled Initial output is...
Page 982 TIER0—Timer Interrupt Enable Register 0 H'FFD4 TPU0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value Read/Write — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB)
Page 983 TSR0—Timer Status Register 0 H'FFD5 TPU0 — — — TCFV TGFD TGFC TGFB TGFA Initial value Read/Write — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 984 TCNT0—Timer Counter 0 H'FFD6 TPU0 Initial value Read/Write Up-counter TGR0A—Timer General Register 0A H'FFD8 TPU0 TGR0B—Timer General Register 0B H'FFDA TPU0 TGR0C—Timer General Register 0C H'FFDC TPU0 TGR0D—Timer General Register 0D H'FFDE TPU0 Initial value Read/Write Rev.6.00 Oct.28.2004 page 956 of 1016 REJ09B0138-0600H...
Page 985 TCR1—Timer Control Register 1 H'FFE0 TPU1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on ø/256...
Page 986 TMDR1—Timer Mode Register 1 H'FFE1 TPU1 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 987 TIOR1—Timer I/O Control Register 1 H'FFE2 TPU1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR1A I/O Control TGR1A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled Initial output is...
Page 988 TIER1—Timer Interrupt Enable Register 1 H'FFE4 TPU1 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB)
Page 989 TSR1—Timer Status Register 1 H'FFE5 TPU1 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 990 TGR1A—Timer General Register 1A H'FFE8 TPU1 TGR1B—Timer General Register 1B H'FFEA TPU1 Initial value Read/Write TCR2—Timer Control Register 2 H'FFF0 TPU2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: counts on ø/1 Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64...
Page 991 TMDR2—Timer Mode Register 2 H'FFF1 TPU2 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
Page 992 TIOR2—Timer I/O Control Register 2 H'FFF2 TPU2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR2A I/O Control TGR2A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled 0 output at compare match...
Page 993 TIER2—Timer Interrupt Enable Register 2 H'FFF4 TPU2 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB)
Page 994 TSR2—Timer Status Register 2 H'FFF5 TPU2 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
Page 995 TCNT2—Timer Counter 2 H'FFF6 TPU2 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A—Timer General Register 2A H'FFF8 TPU2...
Page 996: Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams Port 1 Block Diagram Reset P1nDDR WDDR1 Reset P1nDR WDR1 PPG module Pulse output enable Pulse output DMA controller DMA transfer acknowledge enable DMA transfer acknowledge TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1...
Page 997 Reset P1nDDR WDDR1 Reset P1nDR WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input External clock input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR...
Page 998 Reset P1nDDR WDDR1 Reset P1nDR WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Legend: WDDR1: Write to P1DDR WDR1: Write to P1DR RDR1: Read P1DR RPOR1:...
Page 999: Port 2 Block Diagram
Port 2 Block Diagram Reset P2nDDR WDDR2 Reset P2nDR WDR2 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR RDR2:...
Page 1000 Reset P2nDDR WDDR2 Reset P2nDR WDR2 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR...
Page 1001 Reset P2nDDR WDDR2 Reset P2nDR WDR2 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: Write to P2DDR WDR2: Write to P2DR...

This manual is also suitable for:

H8s/2300 series H8s/2357 series Ztat h8s/2398f Ztat h8s/2357f

Renesas H8S Series Hardware Manual

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 DMA Controller

Section 8 Data Transfer Controller

Section 9 I/O Ports

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Summary of Contents for Renesas H8S Series