Conflict Between Tcor Write And Compare-Match; Figure 13.15 Conflict Between Tcor Write And Compare-Match - Renesas H8S Series Hardware Manual

13.9.3

Conflict between TCOR Write and Compare-Match

If a compare-match occurs during the T
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input
capture conflicts with a compare-match in the same way as with a write to TCORC. In this case
also, the input capture takes priority and the compare-match signal is disabled.
φ
Address
Internal write signal
TCNT
TCOR
Compare-match signal

Figure 13.15 Conflict between TCOR Write and Compare-Match

state of a TCOR write cycle as shown in figure 13.15, the
2
TCOR write cycle by CPU
T 1 T 2
TCOR address
N
N
Section 13 8-Bit Timer (TMR)
N + 1
M
TCOR write data
Disabled
Rev. 3.00 Jul. 14, 2005 Page 409 of 986
REJ09B0098-0300