Figure 16.31 Stop Condition Issuance Timing - Renesas H8S Series Hardware Manual

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
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9. Note on when I C bus interface stop condition instruction is issued
In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a
large bus load capacity or where a slave device in which a wait can be inserted by driving the
SCL pin low is used, the stop condition instruction should be issued after reading SCL after the
rise of the 9th clock pulse and determining that it is low.
SCL
SDA
IRIC
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
Secures a high period
9th clock
VIH
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination

Figure 16.31 Stop Condition Issuance Timing

Section 16 I
Stop condition generation
[2] Stop condition instruction issuance
Rev. 3.00 Jul. 14, 2005 Page 575 of 986
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C Bus Interface (IIC)
REJ09B0098-0300