Internal Interrupt Sources; Interrupt Exception Handling Vector Tables - Renesas H8S Series Hardware Manual

Section 5 Interrupt Controller
5.4.2

Internal Interrupt Sources

Internal interrupts issued from the on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
• The control level for each interrupt can be set by ICR.
• The DTC can be activated by an interrupt request from an on-chip peripheral module.
• An interrupt request that activates the DTC is not affected by the interrupt control mode or the
status of the CPU interrupt mask bits.
5.5

Interrupt Exception Handling Vector Tables

Tables 5.4 and 5.5 list interrupt exception handling sources, vector addresses, and interrupt
priorities. H8S/2140B Group compatible vector mode or extended vector mode can be selected for
the vector addresses by the EIVS bit in system control register 3 (SYSCR3).
For default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the interrupt control
level and the I and UI bits in CCR are given priority and processed before interrupt requests from
modules that are set to interrupt control level 0 (no priority).
Rev. 3.00 Jul. 14, 2005 Page 102 of 986
REJ09B0098-0300