Page 1 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2368 Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series Rev.2.00 2003.5.23...
Page 3 Renesas 16-Bit Single-Chip Microcomputer H8S/Family/H8S/2300 Series H8S/2368 Group Hardware Manual REJ09B0050-0200O...
Page 4 The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination.
Page 5: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 6 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 7: Preface
Preface The H8S/2368 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing Renesas Technology’s original architecture as their cores, and the peripheral functions required to configure a system. The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation.
Page 8: List Of Registers
Signal notation: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/ H8S/2368 Group manuals: Manual Title ADE No. H8S/2368 Group Hardware Manual...
Page 9 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) H8S/2366 added. 1.1 Features Table amended. ROM Type Model Remarks Flash memory version HD64F2367 384 kbytes 24 kbytes HD64F2366 384 kbytes 30 kbytes In planning stage Masked ROM version HD6432365 256 kbytes...
Page 10 Item Page Revision (See Manual for Details) 1.3.1 Pin Arrangement Pin name of pin 86 amended and note added to pin Figure 1.5 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363 Notes: *1 The NC pin should be fixed to Vss or should be open.
Page 11 Item Page Revision (See Manual for Details) 5.4.1 External Interrupts Description amended in the 13th line. Using ISCRL, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. 6.8.1 Operation Description added in the 1st line.
Page 12 Item Page Revision (See Manual for Details) 9.6.4 Pin Functions Amended. • P81/TxD3 (Error) TxD3 input → (Correction) TxD3 output 9.8.6 Port Function Control Bit table amended. Register 0 (PFCR0) Bit Name Initial Value Description CS7E enable Enable/disable corresponding output. CS6E 0: Set as I/O port.
Page 13 Item Page Revision (See Manual for Details) Values when operating frequency φ is 7.1424 MHz 14.3.9 Bit Rate Register (BRR) deleted. Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) Values when operating frequency φ is 2 MHz to 14.8 IrDA Operation 7.3728 MHz deleted.
Page 14 Revision (See Manual for Details) 19.1 Features Table amended. • Size Product Classification ROM Size ROM Address H8S/2368 Series HD64F2367 384 kbytes H'000000 to H'05FFFF (Modes 3, 4, and 7) HD64F2366 • Flash memory emulation Note * added by RAM* Note: * This function is not supported by the H8S/2367 or H8S/2366.
Page 15 Item Page Revision (See Manual for Details) 21.2.2 External Clock Input Description added in the 5th line. Table 21.3 shows the input conditions for the external clock. The frequency of an external clock to be input should be 8 MHz to 25 MHz. 21.4 Frequency Divider Description amended in the 11th line.
Page 16: Register Bits
Item Page Revision (See Manual for Details) 23.2 Register Bits Table amended. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module — — — — — — — — — —...
Page 17 Item Page Revision (See Manual for Details) 23.3 Register States in Table amended. Each Operating Mode Register High- Clock Module All Module Software Hardware Reset Division Sleep Module Name Speed Stop Clock Stop Standby Standby SCI_0 TDR_ Initialized — — —...
Page 18 Item Page Revision (See Manual for Details) 24.1.3 AC Characteristics Note amended. Notes: DACK timing: when DDS = 0 Figure 24.16 DRAM RAS timing: when RAST = 1 Access Timing: Three-State Access (RAST = 1) 24.1.4 A/D Conversion Table amended. Characteristics Item Unit...
Page 19 Item Page Revision (See Manual for Details) Appendix A. I/O Port States Port name amended. in Each Pin State (Error) P35 → (Correction) P35/(OE) Table amended. Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State...
Page 20 Rev. 2.00, 05/03, page xx of lii...
Page 21: Table Of Contents
Contents Section 1 Overview................... Features ..........................Block Diagram ........................Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Arrangement in Each Operating Mode............1.3.3 Pin Functions ....................... 14 Section 2 CPU....................21 Features ..........................21 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ........22 2.1.2 Differences from H8/300 CPU ................
Page 22 Processing States....................... 54 Usage Note........................55 2.9.1 Note on Bit Manipulation Instructions..............55 Section 3 MCU Operating Modes ..............57 Operating Mode Selection ....................57 Register Descriptions ......................58 3.2.1 Mode Control Register (MDCR) ................. 58 3.2.2 System Control Register (SYSCR) ..............58 Operating Mode Descriptions ...................
Page 23 5.4.1 External Interrupts ....................90 5.4.2 Internal Interrupts....................91 Interrupt Exception Handling Vector Table..............92 Interrupt Control Modes and Interrupt Operation ............. 97 5.6.1 Interrupt Control Mode 0 ..................97 5.6.2 Interrupt Control Mode 2 ..................99 5.6.3 Interrupt Exception Handling Sequence .............. 100 5.6.4 Interrupt Response Times ..................
Page 24 6.5.3 Basic Timing......................140 6.5.4 Wait Control ......................148 6.5.5 Read Strobe (RD) Timing..................149 6.5.6 Extension of Chip Select (CS) Assertion Period..........150 DRAM Interface ....................... 152 6.6.1 Setting DRAM Space................... 152 6.6.2 Address Multiplexing ..................152 6.6.3 Data Bus....................... 153 6.6.4 Pins Used for DRAM Interface................
Page 25 Register Descriptions ......................201 7.3.1 Memory Address Registers (MARA and MARB) ..........202 7.3.2 I/O Address Registers (IOARA and IOARB) ............203 7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ........203 7.3.4 DMA Control Registers (DMACRA and DMACRB) ......... 204 7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).....
Page 26 8.2.1 DTC Mode Register A (MRA) ................277 8.2.2 DTC Mode Register B (MRB)................278 8.2.3 DTC Source Address Register (SAR)..............278 8.2.4 DTC Destination Address Register (DAR)............278 8.2.5 DTC Transfer Count Register A (CRA) .............. 278 8.2.6 DTC Transfer Count Register B (CRB)............... 279 8.2.7 DTC Enable Registers A to G (DTCERA to DTCERG) ........
Page 27 9.2.4 Pin Functions ....................... 315 Port 3..........................323 9.3.1 Port 3 Data Direction Register (P3DDR)............. 323 9.3.2 Port 3 Data Register (P3DR)................324 9.3.3 Port 3 Register (PORT3)..................324 9.3.4 Port 3 Open Drain Control Register (P3ODR)............. 325 9.3.5 Port Function Control Register 2 (PFCR2) ............326 9.3.6 Pin Functions .......................
Page 28 9.10.2 Port C Data Register (PCDR) ................353 9.10.3 Port C Register (PORTC) ..................353 9.10.4 Port C MOS Pull-Up Control Register (PCPCR) ..........354 9.10.5 Pin Functions ....................... 354 9.10.6 Port C MOS Input Pull-Up States ................ 355 9.11 Port D..........................356 9.11.1 Port D Data Direction Register (PDDDR) ............
Page 29 10.4 Operation .......................... 411 10.4.1 Basic Functions....................411 10.4.2 Synchronous Operation..................416 10.4.3 Buffer Operation ....................418 10.4.4 Cascaded Operation ..................... 422 10.4.5 PWM Modes ......................424 10.4.6 Phase Counting Mode ..................429 10.5 Interrupts ........................... 435 10.6 DTC Activation......................... 437 10.7 DMAC Activation......................
Page 30 11.4.4 Non-Overlapping Pulse Output................467 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output......468 11.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) ....469 11.4.7 Inverted Pulse Output ..................471 11.4.8 Pulse Output Triggered by Input Capture ............472 11.5 Usage Notes ........................
Page 31 Section 13 Watchdog Timer ................495 13.1 Features ..........................495 13.2 Input/Output Pin........................ 496 13.3 Register Descriptions ......................497 13.3.1 Timer Counter (TCNT)..................497 13.3.2 Timer Control/Status Register (TCSR) ..............497 13.3.3 Reset Control/Status Register (RSTCSR) ............499 13.4 Operation .......................... 500 13.4.1 Watchdog Timer Mode ..................
Page 32 14.5.1 Multiprocessor Serial Data Transmission ............552 14.5.2 Multiprocessor Serial Data Reception ..............554 14.6 Operation in Clocked Synchronous Mode ................ 558 14.6.1 Clock........................558 14.6.2 SCI Initialization (Clocked Synchronous Mode)..........559 14.6.3 Serial Data Transmission (Clocked Synchronous Mode) ........560 14.6.4 Serial Data Reception (Clocked Synchronous Mode) .........
Page 33 15.3.8 I C Bus Receive Data Register (ICDRR) ............. 601 15.3.9 I C Bus Shift Register (ICDRS) ................601 15.4 Operation .......................... 602 15.4.1 I C Bus Format..................... 602 15.4.2 Master Transmit Operation .................. 603 15.4.3 Master Receive Operation..................605 15.4.4 Slave Transmit Operation ..................
Page 34 17.5.1 Setting for Module Stop Mode ................642 17.5.2 D/A Output Hold Function in Software Standby Mode........642 Section 18 RAM ....................643 Section 19 Flash Memory (F-ZTAT Version)...........645 19.1 Features..........................645 19.2 Mode Transitions ......................646 19.3 Block Configuration ......................650 19.4 Input/Output Pins ......................
Page 35 21.5 Usage Notes ........................681 21.5.1 Notes on Clock Pulse Generator ................681 21.5.2 Notes on Oscillator ....................681 21.5.3 Notes on Board Design ..................682 Section 22 Power-Down Modes ............... 683 22.1 Register Descriptions ......................686 22.1.1 Standby Control Register (SBYCR) ..............686 22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)....
Page 36 24.2.4 D/A Conversion Characteristics................780 24.3 Flash Memory Characteristics ..................781 24.4 Usage Note........................783 Appendix ......................785 I/O Port States in Each Pin State..................785 Product Lineup........................792 Package Dimensions ......................793 Bus State during Execution of Instructions............... 795 Index ........................817 Rev.
Page 37 Figures Section 1 Overview Figure 1.1 Internal Block Diagram of H8S/2367, H8S/2365, and H8S/2363 ......3 Figure 1.2 Internal Block Diagram of H8S/2366 ................4 Figure 1.3 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363........5 Figure 1.4 Pin Arrangement of H8S/2366...................6 Figure 1.5 Pin Arrangement of H8S/2367, H8S/2365, and H8S/2363........7 Figure 1.6 Pin Arrangement of H8S/2366...................8...
Page 38 Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2................... 100 Figure 5.5 Interrupt Exception Handling ................101 Figure 5.6 Contention between Interrupt Generation and Disabling........104 Section 6 Bus Controller (BSC) Figure 6.1 Block Diagram of Bus Controller ................108 Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) ...............
Page 39 Figure 6.33 RTCNT Operation ....................169 Figure 6.34 Compare Match Timing ..................169 Figure 6.35 CBR Refresh Timing .....................170 Figure 6.36 CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ....170 Figure 6.37 Example of CBR Refresh Timing (CBRM = 1).............171 Figure 6.38 Self-Refresh Timing....................172 Figure 6.39...
Page 40 Figure 7.11 Operation in Normal Mode..................242 Figure 7.12 Example of Normal Mode Setting Procedure ............243 Figure 7.13 Operation in Block Transfer Mode (BLKDIR = 0) ..........245 Figure 7.14 Operation in Block Transfer Mode (BLKDIR = 1) ..........246 Figure 7.15 Operation Flow in Block Transfer Mode...............
Page 41 Figure 8.11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) ........291 Figure 8.12 DTC Operation Timing (Example of Chain Transfer)...........291 Figure 8.13 Chain Transfer when Counter = 0................296 Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.1 Block Diagram of TPU ..................376 Figure 10.2...
Page 42 Figure 10.39 TGI Interrupt Timing (Input Capture) ..............442 Figure 10.40 TCIV Interrupt Setting Timing ................442 Figure 10.41 TCIU Interrupt Setting Timing ................443 Figure 10.42 Timing for Status Flag Clearing by CPU............... 443 Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC Activation........ 444 Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode....
Page 43 Figure 13.3 Operation in Interval Timer Mode .................502 Figure 13.4 Writing to TCNT, TCSR, and RSTCSR ...............503 Figure 13.5 Contention between TCNT Write and Increment ..........504 Circuit for System Reset by WDTOVF Signal (Example) ........505 Figure 13.6 Section 14 Serial Communication Interface (SCI, IrDA) Figure 14.1 Block Diagram of SCI ...................508 Figure 14.2...
Page 44 Figure 14.30 Example of Reception Processing Flow ..............575 Figure 14.31 Timing for Fixing Clock Output Level ..............575 Figure 14.32 Clock Halt and Restart Procedure................576 Figure 14.33 Block Diagram of IrDA ..................577 Figure 14.34 IrDA Transmit/Receive Operations ............... 578 Figure 14.35 Example of Synchronous Transmission Using DTC ..........
Page 45 Figure 19.1 Block Diagram of Flash Memory .................646 Figure 19.2 Flash Memory State Transitions ................647 Figure 19.3 Boot Mode ......................648 Figure 19.4 User Program Mode....................649 Figure 19.5 384-kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) .....651 Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode.......661 Figure 19.7 Flowchart for Flash Memory Emulation in RAM..........662...
Page 46 Figure 24.15 DRAM Access Timing: Two-State Burst Access..........754 Figure 24.16 DRAM Access Timing: Three-State Access (RAST = 1) ........755 Figure 24.17 DRAM Access Timing: Three-State Burst Access ..........756 Figure 24.18 CAS-Before-RAS Refresh Timing ................ 757 Figure 24.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion)......757 Figure 24.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) .....
Page 47 Tables Section 1 Overview Table 1.1 Pin Arrangement in Each Operating Mode..............9 Table 1.2 Pin Functions ......................14 Section 2 CPU Table 2.1 Instruction Classification ..................37 Table 2.2 Operation Notation....................38 Table 2.3 Data Transfer Instructions..................39 Table 2.4 Arithmetic Operations Instructions ................40 Table 2.5 Logic Operations Instructions..................42 Table 2.6...
Page 48 Table 6.9 Pin States in Bus Released State ................192 Section 7 DMA Controller (DMAC) Table 7.1 Pin Configuration....................201 Table 7.2 Short Address Mode and Full Address Mode (Channel 0) ........202 Table 7.3 DMAC Activation Sources ..................226 Table 7.4 DMAC Transfer Modes ..................
Page 49 Table 10.13 TIORL_0........................389 Table 10.14 TIOR_1 ........................390 Table 10.15 TIOR_2 ........................391 Table 10.16 TIORH_3 .......................392 Table 10.17 TIORL_3........................393 Table 10.18 TIOR_4 ........................394 Table 10.19 TIOR_5 ........................395 Table 10.20 TIORH_0 .......................396 Table 10.21 TIORL_0........................397 Table 10.22 TIOR_1 ........................398 Table 10.23 TIOR_2 ........................399 Table 10.24 TIORH_3 .......................400 Table 10.25 TIORL_3........................401 Table 10.26 TIOR_4 ........................402...
Page 50 Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372)..................535 Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372)....................... 536 Table 14.10 Serial Transfer Formats (Asynchronous Mode).............
Page 51 Table 24.2 DC Characteristics (1)....................734 Table 24.3 DC Characteristics (2)....................735 Table 24.4 Permissible Output Currents ..................736 Table 24.5 Clock Timing ......................738 Table 24.6 Control Signal Timing ...................740 Table 24.7 Bus Timing (1)....................... 742 Table 24.8 Bus Timing (2)....................... 743 Table 24.9 DMAC Timing.......................759 Table 24.10 Timing of On-Chip Peripheral Modules ..............762...
Page 52 Rev. 2.00, 05/03, page lii of lii...
Page 53: Section 1 Overview
Section 1 Overview Features • High-speed H8S/2000 central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 65 basic instructions • Various peripheral functions DMA controller (DMAC)* Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) Programmable pulse generator (PPG)* 8-bit timer (TMR)
Page 54 Package Code Body Size Pin Pitch × TFP-120 TFP-120 (TFP-120V*) 14.0 14.0 mm 0.4 mm × QFP-128 FP-128B (FP-128BV*) 14.0 20.0 mm 0.5 mm Note: * Pb free version Rev. 2.00, 05/03, page 2 of 820...
Page 55: Block Diagram
Block Diagram Figures 1.1 and 1.2 show the internal block diagrams of this LSI. Port D Port E PA7/A23/ PA6/A22/ EXTAL PA5/A21/ XTAL PA4/A20/ EMLE PA3/A19 PA2/A18 PA1/A17 H8S/2000 CPU PA0/A16 Clock PB7/A15 pulse PB6/A14 generator PB5/A13 PB4/A12 φ PF7/ Interrupt controller PB3/A11 PF6/...
Page 56: Figure 1.2 Internal Block Diagram Of H8S/2366
Port D Port E PA7/A23/ PA6/A22/ EXTAL PA5/A21/ XTAL PA4/A20/ EMLE PA3/A19 PA2/A18 PA1/A17 H8S/2000 CPU PA0/A16 Clock PB7/A15 pulse PB6/A14 generator PB5/A13 PB4/A12 φ PF7/ Interrupt controller PB3/A11 PF6/ PB2/A10 PF5/ PB1/A9 PF4/ PB0/A8 PF3/ PC7/A7 PF2/ PC6/A6 PF1/ (Flash memory) PC5/A5 PF0/...
Page 57: Pin Description
Pin Description 1.3.1 Pin Arrangement Figures 1.3 to 1.6 show the pin arrangements of this LSI. PG2/ PE7/D7 PG3/ PE6/D6 Vref PE5/D5 P40/AN0/( PE4/D4 P41/AN1/( PE3/D3 P42/AN2/( PE2/D2 P43/AN3/( PE1/D1 P44/AN4/( PE0/D0 P45/AN5/( P85/SCK3 P46/AN6/( P27/PO7/TIOCB5 P47/AN7/( P26/PO6/TIOCA5 P94/AN12/DA2 TFP-120 P25/PO5/TIOCB4/TMO1 P95/AN13/DA3 (Top view)
Page 58: Figure 1.4 Pin Arrangement Of H8S/2366
PG2/ PE7/D7 PG3/ PE6/D6 Vref PE5/D5 P40/AN0/( PE4/D4 P41/AN1/( PE3/D3 P42/AN2/( PE2/D2 P43/AN3/( PE1/D1 P44/AN4/( PE0/D0 P45/AN5/( P85/SCK3 P46/AN6/( P27/TIOCB5 P47/AN7/( P26/TIOCA5 P94/AN12/DA2 TFP-120 P25/TIOCB4/TMO1 P95/AN13/DA3 (Top view) P24/TIOCA4/TMO0/RxD4 P23/TIOCD3/TMCI1/TxD4 PG4/ P22/TIOCC3/TMCI0 PG5/ P21/TIOCB3/TMRI1 PG6/ P20/TIOCA3/TMRI0 P50/TxD2/ P17/TIOCB2/TCLKD P51/RxD2/ P16/TIOCA2 P52/SCK2/ P15/TIOCB1/TCLKC P53/...
Page 59: Figure 1.5 Pin Arrangement Of H8S/2367, H8S/2365, And H8S/2363
Vref PE6/D6 P40/AN0/( PE5/D5 P41/AN1/( PE4/D4 P42/AN2/( PE3/D3 P43/AN3/( PE2/D2 P44/AN4/( PE1/D1 P45/AN5/( PE0/D0 P46/AN6/( P85/SCK3 P47/AN7/( P27/PO7/TIOCB5 P94/AN12/DA2 P26/PO6/TIOCA5 FP-128B P95/AN13/DA3 P25/PO5/TIOCB4/TMO1 (Top view) P24/PO4/TIOCA4/TMO0/RxD4 PG4/ P23/PO3/TIOCD3/TMCI1/TxD4 PG5/ P22/PO2/TIOCC3/TMCI0 PG6/ P21/PO1/TIOCB3/TMRI1 P50/TxD2/ P20/PO0/TIOCA3/TMRI0 P51/RxD2/ P17/PO15/TIOCB2/TCLKD P52/SCK2/ P16/PO14/TIOCA2 P53/ P15/PO13/TIOCB1/TCLKC/ P35/SCK1/SCL0/( P14/PO12/TIOCA1/ P34/SCK0/SCK4/SDA0...
Page 60: Figure 1.6 Pin Arrangement Of H8S/2366
Vref PE6/D6 P40/AN0/( PE5/D5 P41/AN1/( PE4/D4 P42/AN2/( PE3/D3 P43/AN3/( PE2/D2 P44/AN4/( PE1/D1 P45/AN5/( PE0/D0 P46/AN6/( P85/SCK3 P47/AN7/( P27/TIOCB5 P94/AN12/DA2 P26/TIOCA5 FP-128B P95/AN13/DA3 P25/TIOCB4/TMO1 (Top view) P24/TIOCA4/TMO0/RxD4 PG4/ P23/TIOCD3/TMCI1/TxD4 PG5/ P22/TIOCC3/TMCI0 PG6/ P21/TIOCB3/TMRI1 P50/TxD2/ P20/TIOCA3/TMRI0 P51/RxD2/ P17/TIOCB2/TCLKD P52/SCK2/ P16/TIOCA2 P53/ P15/TIOCB1/TCLKC P35/SCK1/SCL0 P14/TIOCA1 P34/SCK0/SCK4/SDA0...
Page 61: Pin Arrangement In Each Operating Mode
1.3.2 Pin Arrangement in Each Operating Mode Table 1.1 Pin Arrangement in Each Operating Mode Pin No. Pin Name TFP-120 QFP-128 Mode 1 Mode 2 Mode 4 Mode 7 Flash Memory Programmer EXPE = 1 EXPE = 0 Mode PC0/A0 PC0/A0 PC1/A1 PC1/A1...
Page 62: Manual
Pin No. Pin Name TFP-120 QFP-128 Mode 1 Mode 2 Mode 4 Mode 7 Flash Memory Programmer EXPE = 1 EXPE = 0 Mode EMLE EMLE EMLE EMLE EMLE EMLE   WDTOVF WDTOVF WDTOVF WDTOVF WDTOVF P10/PO8*/ P10/PO8*/ P10/PO8*/ P10/PO8*/ P10/PO8*/ TIOCA0/DREQ0*...
Page 63 Pin No. Pin Name TFP-120 QFP-128 Mode 1 Mode 2 Mode 4 Mode 7 Flash Memory Programmer EXPE = 1 EXPE = 0 Mode P25/PO5*/ P25/PO5*/ P25/PO5*/ P25/PO5*/ P25/PO5*/ TIOCB4/TMO1 TIOCB4/TMO1 TIOCB4/TMO1 TIOCB4/TMO1 TIOCB4/TMO1 P26/PO6*/ P26/PO6*/ P26/PO6*/ P26/PO6*/ P26/PO6*/ TIOCA5 TIOCA5 TIOCA5 TIOCA5...
Page 64 Pin No. Pin Name TFP-120 QFP-128 Mode 1 Mode 2 Mode 4 Mode 7 Flash Memory Programmer EXPE = 1 EXPE = 0 Mode PF6/AS PF6/AS PF6/AS PF6/AS PLLVcc PLLVcc PLLVcc PLLVcc PLLVcc PLLVss PLLVss PLLVss PLLVss PLLVss PF7/φ PF7/φ PF7/φ...
Page 65 Pin No. Pin Name TFP-120 QFP-128 Mode 1 Mode 2 Mode 4 Mode 7 Flash Memory Programmer EXPE = 1 EXPE = 0 Mode AVss AVss AVss AVss AVss PG4/CS4/ PG4/CS4/ PG4/CS4/ PG4/CS4/ BREQO BREQO BREQO BREQO PG5/BACK PG5/BACK PG5/BACK PG5/BACK PG6/BREQ PG6/BREQ...
Page 66: Pin Functions
1.3.3 Pin Functions Table 1.2 Pin Functions Pin No. Type Symbol Function TFP-120 QFP-128 Power 2,33,60, 6,39,66, Input Power supply pins. V pins should 83,84 91,92 be connected to the system power supply. 8,17,22, 3,4,12, Input Ground pins. V pins should be 58,80,87 21,26,35, connected to the system power...
Page 67 Pin No. Type Symbol Function TFP-120 QFP-128 Address bus A23 to 29 to 23, 33 to 27, Output Address output pins. 21 to 18, 25 to 22, 16 to 9, 20 to 13, 7 to 3 11 to 7 Data bus D15 to 68 to 61, 76 to 69,...
Page 68 Pin No. Type Symbol Function TFP-120 QFP-128 LCAS* Bus control Output Lower column address strobe signal for accessing the 16-bit DRAM space. RAS2* Output Row address strobe signal for the RAS3* DRAM interface. WAIT* Input Requests insertion of a wait state in the bus cycle when accessing external 3-state address space.
Page 69 Pin No. Type Symbol Function TFP-120 QFP-128 16-bit timer TIOCA2 Input/ TGRA_2 and TGRB_2 input capture pulse unit TIOCB2 output input/output compare output/PWM (TPU) output pins. TIOCA3 Input/ TGRA_3 to TGRD_3 input capture TIOCB3 output input/output compare output/PWM TIOCC3 output pins. TIOCD3 TIOCA4 Input/...
Page 70 Pin No. Type Symbol Function TFP-120 QFP-128 IIC bus SCL1 115, 125, Input/ IIC clock input/output pins. interface2 SCL0 output (IIC2) IIC bus SDA1 116, 126, Input/ IIC data input/output pins. interface (IIC) SDA0 output A/D converter AN13, 104 to 95 114 to 105 Input Analog input pins.
Page 71 Pin No. Type Symbol Function TFP-120 QFP-128 I/O ports P85, Input/ Three-bit input/output pins. P83, output P95, 104, 114, Input Two-bit input pins. PA7 to 29 to 23, 33 to 27, Input/ Eight-bit input/output pins. output PB7 to 20 to 18, 24 to 22, Input/ Eight-bit input/output pins.
Page 72 Rev. 2.00, 05/03, page 20 of 820...
Page 73: Section 2 Cpu
Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU.
Page 74: Differences Between H8S/2600 Cpu And H8S/2000 Cpu
• Two CPU operating modes  Normal mode*  Advanced mode Note: * For this LSI, normal mode is not available. • Power-down state  Transition to power-down state by SLEEP instruction  Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Page 75: Differences From H8/300 Cpu
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added.
Page 76: Cpu Operating Modes
CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode.
Page 77: Advanced Mode
H'0000 Reset exception vector H'0001 H'0002 (Reserved for system use) H'0003 H'0004 H'0005 (Reserved for system use) H'0006 Exception vector table H'0007 H'0008 Exception vector 1 H'0009 H'000A Exception vector 2 H'000B Figure 2.1 Exception Vector Table (Normal Mode) EXR* (16 bits) Reserved* (SP *...
Page 78: Figure 2.3 Exception Vector Table (Advanced Mode)
• Exception vector table and memory indirect branch addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in 32-bit units. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (see figure 2.3).
Page 79: Figure 2.4 Stack Structure In Advanced Mode
EXR* Reserved Reserved* (24 bits) (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: *1 When EXR is not used, it is not stored on the stack. *2 SP when EXR is not used. *3 Ignored when returning. Figure 2.4 Stack Structure in Advanced Mode Rev.
Page 80: Address Space
Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product.
Page 81: Register Configuration
Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR). General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers...
Page 82: General Registers
2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
Page 83: Program Counter (Pc)
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR)
Page 84: Condition-Code Register (Ccr)
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Page 85 Bit Name Initial Value R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. For details, refer to section 5, Interrupt Controller.
Page 86: Initial Register Values
2.4.5 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace (T) bit in EXR to 0, and sets the interrupt mask (I) bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
Page 87: Figure 2.9 General Register Data Formats (2)
Data Type Register Number Data Format Word data Word data Longword data Legend : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.9 General Register Data Formats (2) Rev.
Page 88: Memory Data Formats
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
Page 89: Instruction Set
Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.1 Instruction Classification Function Instructions Size Types Data transfer B/W/L POP* , PUSH* LDM, STM MOVFPE* , MOVTPE* Arithmetic ADD, SUB, CMP, NEG B/W/L...
Page 90: Table Of Instructions Classified By Function
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination)* General register (source)* General register* General register (32-bit register) (EAd)
Page 91: Table 2.3 Data Transfer Instructions
Table 2.3 Data Transfer Instructions Instruction Size* Function (EAs) → Rd, Rs → (EAd) B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in this LSI. MOVTPE Cannot be used in this LSI.
Page 92: Table 2.4 Arithmetic Operations Instructions
Table 2.4 Arithmetic Operations Instructions Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd B/W/L Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes.
Page 93 Instruction Size* Function Rd ÷ Rs → Rd DIVXS Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. B/W/L Rd –...
Page 94: Table 2.5 Logic Operations Instructions
Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Page 95: Table 2.7 Bit Manipulation Instructions
Table 2.7 Bit Manipulation Instructions Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Page 96 Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ∼ (<bit-No.> of <EAd>) → C BIXOR Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the...
Page 97: Table 2.8 Branch Instructions
Table 2.8 Branch Instructions Instruction Size Function – Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA (BT) Always (true) Always BRN (BF) Never (false) Never C ∨ Z = 0 High C ∨...
Page 98: Table 2.9 System Control Instructions
Table 2.9 System Control Instructions Instruction Size* Function TRAPA – Starts trap-instruction exception handling. – Returns from an exception-handling routine. SLEEP – Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR.
Page 99: Basic Instruction Formats
Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B – Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: if R4 ≠ 0 then EEPMOV.W – Repeat @ER5+ → @ER6+ R4–1 →...
Page 100: Addressing Modes And Effective Address Calculation
(1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16, etc.
Page 101: Register Direct-Rn
2.7.1 Register Direct—Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2.7.2 Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn) which contains the...
Page 102: Immediate-#Xx:8, #Xx:16, Or #Xx:32
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2.12 Absolute Address Access Ranges Absolute Address Normal Mode Advanced Mode Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16)
Page 103: Effective Address Calculation
In normal mode, the memory operand is a word operand and the branch address is 16 bits long. In advanced mode, the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00). Note that the top area of the address range in which the branch address is stored is also used for the exception vector area.
Page 104: Table 2.13 Effective Address Calculation
Table 2.13 Effective Address Calculation Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Register direct (Rn) Operand is general register contents. Register indirect (@ERn) General register contents General register contents Sign extension Register indirect with post-increment or pre-decrement •Register indirect with post-increment @ERn+ General register contents...
Page 105 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address Sign extension Immediate Operand is immediate data. PC contents Sign extension Memory contents Memory contents Note: * For this LSI, normal mode is not available. Rev. 2.00, 05/03, page 53 of 820...
Page 106: Processing States
Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
Page 107: Usage Note
End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Exception Software standby handling state mode = High = High, = Low Hardware standby Reset state* mode* Reset state Power down state* Notes: *1 From any state except hardware standby mode, a transition to the reset state occurs whenever goes low.
Page 108 Rev. 2.00, 05/03, page 56 of 820...
Page 109: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Operating Mode Selection This LSI has five operating modes (modes 1 to 4 and 7). Modes 1 to 4 and 7 are available in the flash memory version. Modes 1, 2, 4, and 7 are available in the masked ROM version. Modes 1 and 2 are available in the ROMless version.
Page 110: Register Descriptions
Register Descriptions The following registers are related to the operating mode. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this LSI. Bit Name Initial Value Descriptions −...
Page 111 Bit Name Initial Value Descriptions − Reserved − The initial value should not be modified. − Reserved − The initial value should not be modified. FLSHE Flash Memory Control Register Enable Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). If this bit is set to 1, the flash memory control registers can be read/written to.
Page 112: Operating Mode Descriptions
Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of ports F, and G, carry bus control signals.
Page 113: Mode 7
3.3.5 Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, and the chip starts up in single-chip mode. External address space cannot be used in single-chip mode. The initial mode after a reset is single-chip mode, with all I/O ports available for use as input/output ports.
Page 114: Memory Map In Each Operating Mode
Memory Map in Each Operating Mode Figures 3.1 to 3.7 show memory maps for each product. RAM: 24 kbytes ROM: 384 kbytes Modes 1 and 2 RAM: 24 kbytes (Expanded mode with Mode 3 on-chip ROM disabled) (Boot mode) H'000000 H'000000 On-chip ROM External address...
Page 115: Figure 3.2 H8S/2367 Memory Map (2)
ROM: 384 kbytes ROM: 384 kbytes RAM: 24 kbytes RAM: 24 kbytes Mode 7 Mode 4 (Single-chip activation (Expanded mode with expanded mode, with on-chip ROM enabled) on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'060000 H'060000 External address External address space/ space...
Page 116: Figure 3.3 H8S/2366 Memory Map (1)
RAM: 30 kbytes ROM: 384 kbytes Modes 1 and 2 RAM: 30 kbytes (Expanded mode with Mode 3 on-chip ROM disabled) (Boot mode) H'000000 H'000000 On-chip ROM External address space H'060000 External address space/ Reserved area * H'FF4000 H'FF4000 Reserved area * Reserved area * H'FF4800 H'FF4800...
Page 117: Figure 3.4 H8S/2366 Memory Map (2)
ROM: 384 kbytes ROM: 384 kbytes RAM: 30 kbytes RAM: 30 kbytes Mode 7 Mode 4 (Single-chip activation (Expanded mode with expanded mode, with on-chip ROM enabled) on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'060000 H'060000 External address External address space/ space...
Page 118: Figure 3.5 H8S/2365 Memory Map (1)
ROM: 256 kbytes RAM: 16 kbytes RAM: 16 kbytes Modes 1 and 2 Mode 4 (Expanded mode with (Expanded mode with on-chip ROM disabled) on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 Reserved area* External address space H'060000 External address space H'FF4000 H'FF4000...
Page 119: Figure 3.6 H8S/2365 Memory Map (2)
ROM: 258 kbytes RAM: 16 kbytes Mode 7 (Single-chip activation expanded mode, with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area * H'060000 External address space/ reserved area * H'FF4000 Reserved area H'FF8000 On-chip RAM/ external address space * H'FFC000 Reserved area H'FFC800...
Page 120: Figure 3.7 H8S/2363 Memory Map
RAM: 16 kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FF8000 On-chip RAM/ external address space * H'FFC000 Reserved area * H'FFC800 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF...
Page 121: Section 4 Exception Handling
Section 4 Exception Handling Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 122: Table 4.2 Exception Handling Vector Table
Table 4.2 Exception Handling Vector Table Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Power-on reset H'0000 to H'0001 H'0000 to H'0003 Manual reset * H'0002 to H'0003 H'0004 to H'0007 Reserved for system use H'0004 to H'0005 H'0008 to H'000B H'0006 to H'0007 H'000C to H'000F...
Page 123: Reset
Vector Address* Exception Source Vector Number Normal Mode* Advanced Mode Internal interrupt* H'0040 to H'0041 H'0080 to H'0083    H'00EC to H'00ED H'01D8 to H'01DB Notes: *1 Lower 16 bits of the address. *2 Not available in this LSI. *3 Not available in this LSI.
Page 124: Figure 4.1 Reset Sequence (Advanced Mode With On-Chip Rom Enabled)
Prefetch of first Internal Vector fetch program instruction processing φ Internal address bus Internal read signal Internal write High signal Internal data (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.1 Reset Sequence (Advanced Mode with On-Chip ROM Enabled)
Page 125: Interrupts After Reset
Internal Prefetch of first processing program instruction Vector fetch Address bus High D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted.
Page 126: Traces
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 127: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack.
Page 128: Stack Status After Exception Handling
Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes Reserved* CCR* CCR* PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 (b) Advanced Modes Reserved* PC (24 bits)
Page 129: Usage Notes
Usage Notes When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
Page 130 Rev. 2.00, 05/03, page 78 of 820...
Page 131: Section 5 Interrupt Controller
Section 5 Interrupt Controller Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
Page 132: Figure 5.1 Block Diagram Of Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number ITSR ISCRL Priority SSIER determination Internal interrupt sources I2 to I0 SWDTEND to IICI1 Interrupt controller...
Page 133: Input/Output Pins
Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name Function Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ7 to IRQ0 Input Maskable external interrupts Rising edge, falling edge, both edges, or level sensing, can be selected.
Page 134: Interrupt Control Register (Intcr)
5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Name Initial Value Description − − Reserved − These bits are always read as 0 and cannot be modified. INTM1 Interrupt Control Select Mode 1 and 0 INTM0 These bits select either of two interrupt control modes for the interrupt controller.
Page 135 Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified. IPR14 Sets the priority of the corresponding interrupt IPR13 source. IPR12 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5...
Page 136: Irq Enable Register (Ier)
Bit Name Initial Value Description − − Reserved This bit is always read as 0 and cannot be modified. IPR2 Sets the priority of the corresponding interrupt IPR1 source. IPR0 000: Priority level 0 (Lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5...
Page 137: Irq Sense Control Register L (Iscrl)
Initial Value Description Name IRQ2E IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. IRQ1E IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. IRQ0E IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1.
Page 138 Bit Name Initial Value Description IRQ5SCB IRQ5 Sense Control B IRQ5SCA IRQ5 Sense Control A 00: Interrupt request generated at IRQ5 input low level 01: Interrupt request generated at falling edge of IRQ5 input 10: Interrupt request generated at rising edge of IRQ5 input 11: Interrupt request generated at both falling and rising edges of IRQ5 input...
Page 139 Bit Name Initial Value Description IRQ2SCB IRQ2 Sense Control B IRQ2SCA IRQ2 Sense Control A 00: Interrupt request generated at IRQ2 input low level 01: Interrupt request generated at falling edge of IRQ2 input 10: Interrupt request generated at rising edge of IRQ2 input 11: Interrupt request generated at both falling and rising edges of IRQ2 input...
Page 140: Irq Status Register (Isr)
5.3.5 IRQ Status Register (ISR) ISR is an IRQ7 to IRQ0 interrupt request flag register. Name Initial Value Description − 15 to 8 Reserved The write value should always be 0. IRQ7F R/(W)* [Setting conditions] IRQ6F R/(W)* When the interrupt source selected by ISCR IRQ5F R/(W)* occurs...
Page 141: Irq Pin Select Register (Itsr)
5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ7 to IRQ0. Name Initial Value Description − 15 to 8 Reserved The write value should always be 0. Selects IRQ7 input pin. ITS7 0: PA7 1: P47 Selects IRQ6 input pin. ITS6 0: PA6 1: P46...
Page 142: Software Standby Release Irq Enable Register (Ssier)
5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Name Initial Value Description − 15 to 8 Reserved The write value should always be 0. SSI7 Software Standby Release IRQ Setting SSI6 These bits select the IRQn pins used to recover SSI5...
Page 143: Internal Interrupts
When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in the interrupt handling routine and clear the IRQnF bit (n = 0 to 7) in ISR to 0. Interrupts may not be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Page 144: Interrupt Exception Handling Vector Table
Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities.
Page 145: Table 5.2 Interrupt Sources, Vector Addresses, And Interrupt Priorities
Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC* Source Mode Source Number Priority Activation Activation External H'001C — High — — IRQ0 H'0040 IPRA14 to IPRA12 — IRQ1 H'0044 IPRA10 to IPRA8 —...
Page 146 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC* Source Source Number Mode Priority Activation Activation TPU_0 IPRF6 to IPRF4 TGI0D H'00AC High — TCI0V H'00B0 — — — Reserved for H’00B4 — — system use H’00B8 — — H’00BC —...
Page 147 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC* Source Source Number Mode Priority Activation Activation IPRH14 to IPRH12 High — — — Reserved for H’012C system use TMR_1 CMIA1 H'0130 IPRH10 to IPRH8 — — CMIB1 H'0134 — — OVI1 H'0138 —...
Page 148 Vector Address* Origin of Interrupt Interrupt Vector Advanced DMAC* Source Source Number Mode Priority Activation Activation SCI_4 ERI4 H’01A0 IPRJ2 to IPRJ0 High — — RXI4 — H’01A4 TXI4 H’01A8 — TEI4 — — H’01AC — Reserved for H’01B0 IPRK14 to IPRK12 —...
Page 149: Interrupt Control Modes And Interrupt Operation
Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2.
Page 150: Figure 5.3 Flowchart Of Procedure Up To Interrupt Acceptance
Program execution status Interrupt generated? I = 0 Hold pending IRQ0 IRQ1 IICI1 Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.
Page 151: Interrupt Control Mode 2
5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
Page 152: Interrupt Exception Handling Sequence
Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 or below? Level 1 interrupt? Mask level 5 or below? Mask level 0? Hold Save PC, CCR, and EXR pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance...
Page 153: Figure 5.5 Interrupt Exception Handling
Figure 5.5 Interrupt Exception Handling Rev. 2.00, 05/03, page 101 of 820...
Page 154: Interrupt Response Times
5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5. This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Page 155: Dtc And Dmac* Activation By Interrupt
5.6.5 DTC and DMAC* Activation by Interrupt The DTC and DMAC* can be activated by an interrupt. In this case, the following options are available: • Interrupt request to CPU • Activation request to DTC • Activation request to DMAC* •...
Page 156: Instructions That Disable Interrupts
TIER_0 write cycle by CPU TCIV exception handling φ Internal TIER_0 address address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Contention between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed.
Page 157: Change Of Irq Pin Select Register (Itsr) Setting
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
Page 158 Rev. 2.00, 05/03, page 106 of 820...
Page 159: Section 6 Bus Controller (Bsc)
Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus masters—the CPU, DMA controller (DMAC)* and data transfer controller (DTC). Note: * Not supported by the H8S/2366.
Page 160: Figure 6.1 Block Diagram Of Bus Controller
A block diagram of the bus controller is shown in figure 6.1. Internal address bus Area decoder External bus controller Internal bus master bus request signal External bus Internal bus master bus acknowledge signal arbiter External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal...
Page 161: Input/Output Pins
Input/Output Pins Table 6.1 summarizes the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol Function Address strobe Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Read Output Strobe signal indicating that normal space is being read.
Page 162: Register Descriptions
Name Symbol Function Output enable* Output Output enable signal for the DRAM space. WAIT Wait Input Wait request signal when accessing external address space. BREQ Bus request Input Request signal for release of bus to external bus master. BACK Bus request acknowledge Output Acknowledge signal indicating that bus has been released to external bus master.
Page 163: Bus Width Control Register (Abwcr)
6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Name Initial Value* Description ABW7 Area 7 to 0 Bus Width Control ABW6 These bits select whether the corresponding ABW5 area is to be designated as 8-bit access space ABW4...
Page 164: Wait Control Registers Ah, Al, Bh, And Bl (Wtcrah, Wtcral, Wtcrbh, And Wtcrbl)
6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. • WTCRAH Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified.
Page 165 Bit Name Initial Value Description Area 6 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1. 000: Program wait not inserted 001: 1 program wait state inserted 010: 2 program wait states inserted 011: 3 program wait states inserted 100: 4 program wait states inserted...
Page 166 Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 4 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 4 while AST4 bit in ASTCR = 1.
Page 167 • WTCRBH Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 3 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1.
Page 168 • WTCRBL Bit Name Initial Value Description − Reserved This bit is always read as 0 and cannot be modified. Area 1 Wait Control 2 to 0 These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
Page 169: Read Strobe Timing Control Register (Rdncr)
6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Name Initial Value Description RDN7 Read Strobe Timing Control 7 to 0 RDN6 These bits set the negation timing of the read RDN5 strobe in a corresponding area read access.
Page 170: Cs Assertion Period Control Registers H, L (Csacrh, Csacrl)
CS Assertion Period Control Registers H, L (CSACRH, CSACRL) 6.3.5 CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.
Page 171: Figure 6.3 Cs And Address Assertion Period Extension (Example Of 3-State Access Space And Rdnn = 0)
Bus cycle Address Read Data Write Data Figure 6.3 CS CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Rev. 2.00, 05/03, page 119 of 820...
Page 172: Area 0 Burst Rom Interface Control Register (Bromcrh) Area 1 Burst Rom Interface Control Register (Bromcrl)
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively.
Page 173: Bus Control Register (Bcr)
6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Name Initial Value Description BRLE External Bus Release Enable...
Page 174 Name Initial Value Description ICIS0 Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted WDBE Write Data Buffer Enable The write data buffer function can be used for...
Page 175: Dram Control Register (Dramcr)
6.3.8 DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The DRAM interface is not supported by the H8S/2366. Bit Name Initial Value Description OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output from the (OE) pin.
Page 176 Bit Name Initial Value Description RMTS2 DRAM Space Select RMTS1 These bits designate DRAM space for areas 2 RMTS0 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin.
Page 177 Bit Name Initial Value Description RAS Down Mode RCDM When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode).
Page 178 Bit Name Initial Value Description MXC2 Address Multiplex Select MXC1 These bits select the size of the shift toward the MXC0 lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM interface, these bits also select the row address bits to be used for comparison.
Page 179: Figure 6.4 Ras Signal Assertion Timing
Bus cycle Row address Column address Address RAST = 0 RAST = 1 Figure 6.4 RAS RAS Signal Assertion Timing (2-State Column Address Output Cycle, Full Access) Rev. 2.00, 05/03, page 127 of 820...
Page 180: Dram Access Control Register (Draccr)
6.3.9 DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM interface bus specifications. Note: The DRAM interface is not supported by the H8S/2366. Bit Name Initial Value Description DRMI Idle Cycle Insertion An idle cycle can be inserted after a DRAM access cycle when a continuous normal space access cycle follows a DRAM access cycle.
Page 181: Refresh Control Register (Refcr)
6.3.10 Refresh Control Register (REFCR) REFCR specifies DRAM interface refresh control. Note: The DRAM interface is not supported by the H8S/2366. Bit Name Initial Value Description R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR. [Clearing conditions] •...
Page 182 Bit Name Initial Value Description RTCK2 Refresh Counter Clock Select RTCK1 These bits select the clock to be used to RTCK0 increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up. 000: Count operation halted 001: Count on φ/2 010: Count on φ/8...
Page 183 Bit Name Initial Value Description SLFRF Self-Refresh Enable If this bit is set to 1, DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations.
Page 184: Refresh Timer Counter (Rtcnt)
6.3.11 Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00.
Page 185: Figure 6.5 Area Divisions
H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7...
Page 186: Bus Specifications
6.4.2 Bus Specifications The external space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 187: Table 6.2 Bus Specifications For Each Area (Basic Bus Interface)
Table 6.2 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WTCRA, WTCRB Bus Specifications (Basic Bus Interface) Access Program Wait ABWn ASTn Bus Width States States — — — — — — (n = 0 to 7) Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in the basic bus interface space.
Page 188: Memory Interfaces
6.4.3 Memory Interfaces The memory interfaces in this LSI comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on a synchronous DRAM interface* that allows direct connection of synchronous DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area.
Page 189: Chip Select Signals
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In externally expanded mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on- chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in external space.
Page 190: Basic Bus Interface
Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size.
Page 191: Valid Strobes
Upper data bus Lower data bus D8 D7 Byte size • Even address Byte size • Odd address Word size 1st bus cycle Longword size 2nd bus cycle Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space) 6.5.2 Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces.
Page 192: Basic Timing
6.5.3 Basic Timing 8-Bit, 2-State Access Space: Figure 6.9 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle Address bus D15 to D8...
Page 193: Figure 6.10 Bus Timing For 8-Bit, 3-State Access Space
8-Bit, 3-State Access Space: Figure 6.10 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle Address bus D15 to D8...
Page 194: Figure 6.11 Bus Timing For 16-Bit, 2-State Access Space (Even Address Byte Access)
16-Bit, 2-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted.
Page 195: Figure 6.12 Bus Timing For 16-Bit, 2-State Access Space (Odd Address Byte Access)
Bus cycle Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) Rev.
Page 196: Figure 6.13 Bus Timing For 16-Bit, 2-State Access Space (Word Access)
Bus cycle Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Rev.
Page 197: Figure 6.14 Bus Timing For 16-Bit, 3-State Access Space (Even Address Byte Access)
16-Bit, 3-State Access Space: Figures 6.14 to 6.16 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Page 198: Figure 6.15 Bus Timing For 16-Bit, 3-State Access Space (Odd Address Byte Access)
Bus cycle Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Rev.
Page 199: Figure 6.16 Bus Timing For 16-Bit, 3-State Access Space (Word Access)
Bus cycle Address bus D15 to D8 Read Valid D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Word Access) Rev.
Page 200: Wait Control
6.5.4 Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T state and T state on an individual area basis in 3-state access space, according to the settings in...
Page 201: Read Strobe (Rd) Timing
By program wait Address bus Read Data bus Read data Write Data bus Write data Notes: 1. Downward arrows indicate the timing of pin sampling. 2. When RDN = 0 Figure 6.17 Example of Wait State Insertion Timing RD) Timing 6.5.5 Read Strobe (RD The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to...
Page 202: Extension Of Chip Select (Cs) Assertion Period
Bus cycle Address bus RDNn = 0 Data bus RDNn = 1 Data bus Figure 6.18 Example of Read Strobe Timing CS) Assertion Period 6.5.6 Extension of Chip Select (CS Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR.
Page 203: Figure 6.19 Example Of Timing When Chip Select Assertion Period Is Extended
Bus cycle Address bus Read (when RDNn = 0) Data bus Read data Write Data bus Write data Figure 6.19 Example of Timing when Chip Select Assertion Period is Extended Both extension state T inserted before the basic bus cycle and extension state T inserted after the basic bus cycle, or only one of these, can be specified for individual areas.
Page 204: Dram Interface
DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode.
Page 205: Data Bus
Table 6.5 Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing DRAMCR Address Pins MXC2 MXC1 MXC0 Shift Size A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 8 bits A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 address 9 bits...
Page 206: Pins Used For Dram Interface
6.6.4 Pins Used for DRAM Interface Table 6.6 shows the pins used for DRAM interfacing and their functions. Since the CS2, CS5 pins are in the input state after a reset, set the corresponding DDR to 1 when RAS2, RAS5 signals are output.
Page 207: Basic Timing
6.6.5 Basic Timing Figure 6.20 shows the basic access timing for DRAM space. The four states of the basic timing consist of one T (precharge cycle) state, one T (row address output cycle) state, and the T and two T (column address output cycle) states.
Page 208: Column Address Output Cycle Control
6.6.6 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI.
Page 209: Figure 6.22 Example Of Access Timing When Ras Signal Goes Low From Beginning Of T State (Cast = 0)
frequency of this LSI. Figure 6.22 shows an example of the timing when the RAS signal goes low from the beginning of the T state. Address bus Row address Column address High Read Data bus Write High Data bus Note: n = 2, 3 Figure 6.22 Example of Access Timing when RAS RAS Signal Goes Low from Beginning of T...
Page 210: Figure 6.23 Example Of Timing With One Row Address Output Maintenance State (Rast = 0, Cast = 0)
If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three T states, in which row address output is maintained, cycle, in which the RAS signal goes low, and the T to be inserted between the T cycle, in which the column address is output.
Page 211: Precharge State Control
6.6.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one T state is always inserted when DRAM space is accessed. From one to four T states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T cycles according to the DRAM connected and the operating frequency of this LSI.
Page 212: Wait Control
6.6.9 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
Page 213: Figure 6.25 Example Of Wait State Insertion Timing (2-State Column Address Output)
By program wait Row address Column address Address bus High Read Data bus Write High Data bus Notes: Downward arrows indicate the timing of pin sampling. n = 2, 3 Figure 6.25 Example of Wait State Insertion Timing (2-State Column Address Output) Rev.
Page 214: Figure 6.26 Example Of Wait State Insertion Timing (3-State Column Address Output)
By program wait Row address Column address Address bus High Read Data bus Write High Data bus Notes: Downward arrows indicate the timing of pin sampling. n = 2, 3 Figure 6.26 Example of Wait State Insertion Timing (3-State Column Address Output) Rev.
Page 215: Byte Access Control
6.6.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.27 shows the control timing for 2-CAS access, and figure 6.28 shows an example of 2-CAS DRAM connection. Address bus Row address Column address...
Page 216: Burst Operation
This LSI 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration (Address shift size set to 10 bits) 10-bit column address Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 D15 to D0 Figure 6.28 Example of 2-CAS DRAM Connection 6.6.11 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a...
Page 217: Figure 6.29 Operation Timing In Fast Page Mode (Rast = 0, Cast = 0)
Row address Column address 1 Column address 2 Address bus High Read Data bus Write High Data bus Note: n = 2, 3 Figure 6.29 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) Rev. 2.00, 05/03, page 165 of 820...
Page 218: Figure 6.30 Operation Timing In Fast Page Mode (Rast = 0, Cast = 1)
Row address Column address 1 Column address 2 Address bus High Read Data bus Write High Data bus Note: n = 2, 3 Figure 6.30 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access.
Page 219: Figure 6.31 Example Of Operation Timing In Ras Down Mode (Rast = 0, Cast = 0)
 the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Page 220: Refresh Control
• RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.32 shows an example of the timing in RAS up mode.
Page 221: Figure 6.33 Rtcnt Operation
CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit to 1 in REFCR. With CBR refreshing, RTCNT counts up using the input clock selected by bits RTCK2 to RTCK0 in REFCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed.
Page 222: Figure 6.35 Cbr Refresh Timing
Note: n = 2, 3 Figure 6.35 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Page 223: Figure 6.37 Example Of Cbr Refresh Timing (Cbrm = 1)
Normal space access request A23 to A0 Refresh period Figure 6.37 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR.
Page 224: Figure 6.38 Self-Refresh Timing
Software standby High Note: n = 2, 3 Figure 6.38 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
Page 225: Dmac Single Address Transfer Mode And Dram Interface
Software DRAM space write standby Address bus Data bus Note: n = 2, 3 Figure 6.39 Example of Timing when Precharge Time after Self-Refreshing is Extended by 2 States Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the...
Page 226: Figure 6.40 Example Of Dack Output Timing When Dds = 1 (Rast = 0, Cast = 0)
Figure 6.40 shows the DACK output timing for the DRAM interface when DDS = 1. Address bus Row address Column address High Read Data bus Write High Data bus Note: n = 2, 3 Figure 6.40 Example of DACK DACK DACK Output Timing when DDS = 1 (RAST = 0, CAST = 0) DACK When DDS = 0 : When DRAM space is accessed in DMAC single address transfer mode, full...
Page 227: Figure 6.41 Example Of Dack Output Timing When Dds = 0 (Rast = 0, Cast = 1)
Address bus Row address Column address High Read Data bus Write High Data bus Note: n = 2, 3 Figure 6.41 Example of DACK DACK DACK Output Timing when DDS = 0 (RAST = 0, CAST = 1) DACK Rev. 2.00, 05/03, page 175 of 820...
Page 228: Burst Rom Interface
Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR.
Page 229: Figure 6.42 Example Of Burst Rom Access Timing (Astn = 1, 2-State Burst Cycle)
Full access Burst access Upper address bus Lower address bus Data bus Note: n = 1, 0 Figure 6.42 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Rev. 2.00, 05/03, page 177 of 820...
Page 230: Wait Control
Full access Burst access Upper address bus Lower address bus Data bus Note: n = 1, 0 Figure 6.43 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.7.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface.
Page 231: Idle Cycle
Idle Cycle 6.8.1 Operation When this LSI accesses external address space, it can insert an idle cycle (T ) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle.
Page 232: Figure 6.45 Example Of Idle Cycle Operation (Write After Read)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.45 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 233: Figure 6.46 Example Of Idle Cycle Operation (Read After Write)
Bus cycle A Bus cycle B Bus cycle A Bus cycle B Address bus Address bus (area A) (area A) (area B) (area B) Data bus Data bus Data collision Idle cycle Long output floating time (a) No idle cycle insertion (b) Idle cycle insertion (ICIS2 = 0) (ICIS2 = 1, initial value)
Page 234: Figure 6.47 Relationship Between Chip Select (Cs) And Read (Rd)
Bus cycle A Bus cycle B Bus cycle A Bus cycle B Address bus Address bus (area A) (area A) (area B) (area B) Idle cycle Overlap period between (area B) may occur (b) Idle cycle insertion (a) No idle cycle insertion (ICIS1 = 1, initial value) (ICIS1 = 0) CS) and Read (RD...
Page 235: Figure 6.49 Example Of Idle Cycle Operation In Ras Down Mode (Consecutive Reads In Different Areas) (Idlc = 0, Rast = 0, Cast = 0)
In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 6.49 and 6.50. DRAM space read External read DRAM space read Address bus Data bus...
Page 236: Figure 6.51 Example Of Idle Cycle Operation After Dram Access (Consecutive Reads In Different Areas) (Idlc = 0, Rast = 0, Cast = 0)
Idle Cycle in Case of Normal Space Access after DRAM Space Access: • Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1.
Page 237: Figure 6.52 Example Of Idle Cycle Operation After Dram Access (Write After Read) (Idlc = 0, Rast = 0, Cast = 0)
DRAM space read External address space write DRAM space read Address bus Data bus Idle cycle Figure 6.52 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) Rev. 2.00, 05/03, page 185 of 820...
Page 238: Figure 6.53 Example Of Idle Cycle Operation After Dram Write Access (Idlc = 0, Icis1 = 0, Rast = 0, Cast = 0)
• Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit.
Page 239: Table 6.7 Idle Cycles In Mixed Accesses To Normal Space And Dram
Table 6.7 shows whether an idle cycle is inserted or not in mixed access to normal space and DRAM. Table 6.7 Idle Cycles in Mixed Accesses to Normal Space and DRAM Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space read Normal space read...
Page 240: Figure 6.54 Example Of Timing For Idle Cycle Insertion In Case Of Consecutive Read
Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space write Normal space read — — — — Disabled — — — 1 state inserted 2 states inserted DRAM/ space read — — — — Disabled — —...
Page 241: Pin States In Idle Cycle
6.8.2 Pin States in Idle Cycle Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High* UCAS* , LCAS*...
Page 242: Bus Release
On-chip memory read Internal I/O register read External write cycle Internal address bus Internal memory Internal I/O register address Internal read signal External address A23 to A0 External space write D15 to D0 Figure 6.55 Example of Timing when Write Data Buffer Function is Used 6.10 Bus Release This LSI can release the external bus in response to a bus request from an external device.
Page 243 In the external bus released state, internal bus masters can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. If a refresh request is generated in the external bus released state, or if a SLEEP instruction is executed to place the chip in software standby mode or all-module-clocks-stopped mode, refresh control and software standby or all-module-clocks-stopped control is deferred until the bus request from...
Page 244: Pin States In External Bus Released State
6.10.2 Pin States in External Bus Released State Table 6.9 shows pin states in the external bus released state. Table 6.9 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn (n = 7 to 0) High impedance UCAS*, LCAS*...
Page 245: Transition Timing
6.10.3 Transition Timing Figure 6.56 shows the timing for transition to the bus released state. External space access cycle cycle External bus released state High-Z Address bus High-Z Data bus High-Z High-Z High-Z signal is sampled at rise of φ. [1] Low level of [2] Bus control signal returns to be high at end of external space access cycle.
Page 246: Bus Arbitration
6.11 Bus Arbitration This LSI has a bus arbiter that arbitrates bus master operations (bus arbitration). There are three bus masters—the CPU, DTC, and DMAC*—which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Page 247: Bus Transfer Timing
6.11.2 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately.
Page 248: Bus Controller Operation In Reset
6.12 Bus Controller Operation in Reset In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted. 6.13 Usage Notes 6.13.1 External Bus Release Function and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered...
Page 249: Breqo Output Timing
BREQO BREQO Output Timing BREQO BREQO 6.13.4 When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ.
Page 250 Rev. 2.00, 05/03, page 198 of 820...
Page 251: Section 7 Dma Controller (Dmac)
Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. Note: Not supported by the H8S/2366. Features • Choice of short address mode or full address mode ...
Page 252: Figure 7.1 Block Diagram Of Dmac
A block diagram of the DMAC is shown in figure 7.1. Internal address bus Internal interrupts TGI0A Address buffer TGI1A TGI2A Processor TGI3A TGI4A TGI5A MAR_0AH MAR_0AL TXI0 IOAR_0A RXI0 Control logic TXI1 ETCR_0A RXI1 MAR_0BH MAR_0BL External pins IOAR_0B ETCR_0B DMAWER MAR_1AH...
Page 253: Input/Output Pins
Input/Output Pins Table 7.1 summarizes the pins of the interrupt controller. Table 7.1 Pin Configuration Channel Pin Name Symbol Function DREQ0 DMA request 0 Input Channel 0 external request DMA transfer acknowledge 0 DACK0 Output Channel 0 single address transfer acknowledge TEND0 DMA transfer end 0 Output...
Page 254: Memory Address Registers (Mara And Marb)
• DMA band control register H (DMABCRH) • DMA band control register L (DMABCRL) • DMA write enable register (DMAWER) • DMA terminal control register (DMATCR) The functions of MAR, IOAR, ETCR, DMACR, and DMABCR differ according to the transfer mode (short address mode or full address mode).
Page 255: I/O Address Registers (Ioara And Ioarb)
MAR is not initialized by a reset or in standby mode. Short Address Mode: In short address mode, MARA and MARB operate independently. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated.
Page 256: Dma Control Registers (Dmacra And Dmacrb)
Short Address Mode: The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends.
Page 257 Short Address Mode: • DMACR_0A, DMACR_0B, DMACR_1A, and DMARC_1B Bit Name Initial Value Description DTSZ Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer DTID Data Transfer Increment/Decrement Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode.
Page 258 Bit Name Initial Value Description DTF3 Data Transfer Factor 3 to 0 DTF2 These bits select the data transfer factor (activation source). There are some differences DTF1 in activation sources for channel A and channel DTF0 • Channel A 0000: Setting prohibited 0001: Activated by A/D converter conversion end interrupt 0010: Setting prohibited...
Page 259 Bit Name Initial Value Description • DTF3 Channel B DTF2 0000: Setting prohibited DTF1 0001: Activated by A/D converter conversion end interrupt DTF0 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmission complete interrupt...
Page 260 Full Address Mode: • DMACR_0A and DMACR_1A Bit Name Initial Value Description DTSZ Data Transfer Size Selects the size of data to be transferred at one time. 0: Byte-size transfer 1: Word-size transfer SAID Source Address Increment/Decrement SAIDE Source Address Increment/Decrement Enable These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data...
Page 261 Bit Name Initial Value Description  Reserved Though these bits can be read from or written to, the write value should always be 0. Legend x: Don't care • DMACR_0B and DMACR_1B Bit Name Initial Value Description  Reserved Though this bit can be read from or written to, the write value should always be 0.
Page 262 Bit Name Initial Value Description DTF3 • Normal Mode DTF2 0000: Setting prohibited DTF1 0001: Setting prohibited 0010: Activated by DREQ pin falling edge input DTF0 (for the first transfer after data transfer is enabled, activated by DREQ pin low-level input) 0011: Activated by DREQ pin low-level input 010x: Setting prohibited...
Page 263: Dma Band Control Registers H And L (Dmabcrh And Dmabcrl)
Bit Name Initial Value Description DTF3 The same factor can be selected for more than one channel. In this case, activation starts with DTF2 the highest-priority channel according to the DTF1 relative channel priorities. For relative channel priorities, see section 7.5.12, Multi-Channel DTF0 Operation.
Page 264 Bit Name Initial Value Description SAE0 Single Address Enable 0 Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. 0: Dual address mode 1: Single address mode DTA1B Data Transfer Acknowledge 1B...
Page 265 • DMABCRL Bit Name Initial Value Description DTE1B Data Transfer Enable 1B DTE1A Data Transfer Enable 1A DTE0B Data Transfer Enable 0B DTE0A Data Transfer Enable 0A If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Page 266 Bit Name Initial Value Description DTIE1B Data Transfer End Interrupt Enable 1B DTIE1A Data Transfer End Interrupt Enable 1A DTIE0B Data Transfer End Interrupt Enable 0B DTIE0A Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
Page 267 Full Address Mode: • DMABCRH Bit Name Initial Value Description FAE1 Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as channel 1.
Page 268 Bit Name Initial Value Description DTA1 Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1. It the DTA1 bit is set to 1 when DTE1 = 1, the internal interrupt source is cleared automatically by DMA transfer.
Page 269 Bit Name Initial Value Description DTA0 Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer.
Page 270 • DMABCRL Bit Name Initial Value Description DTME1 Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel If channel 1 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME1 bit is cleared, the transfer is interrupted,...
Page 271 Bit Name Initial Value Description DTE1 Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored.
Page 272 Bit Name Initial Value Description DTME0 Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel If channel 0 is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME0 bit is cleared, the transfer is interrupted,...
Page 273 Bit Name Initial Value Description DTE0 Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored.
Page 274 Bit Name Initial Value Description DTIE1A Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. When DTE1 is cleared to 0 while this bit is set to 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Page 275: Dma Write Enable Register (Dmawer)
7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
Page 276: Figure 7.2 Areas For Register Re-Setting By Dtc (Channel 0A)
MAR_0A First transfer area IOAR_0A ETCR_0A MAR_0B IOAR_0B ETCR_0B MAR_1A IOAR_1A ETCR_1A MAR_1B IOAR_1B ETCR_1B DMAWER DMATCR DMACR_0A DMACR_0B DMACR_1A DMACR_1B Second transfer area DMABCR using chain transfer Figure 7.2 Areas for Register Re-Setting by DTC (Channel 0A) Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings.
Page 277: Dma Terminal Control Register (Dmatcr)
7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. In short address mode, the TEND pin is only available for channel B. The transfer end signal indicates the transfer cycle in which the transfer counter has become 0 regardless of the transfer source.
Page 278: Activation Sources
Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and auto- requests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.3 DMAC Activation Sources Short Address Mode Full Address Mode Block...
Page 279: Activation By External Request
If the DMAC is activated by a CPU interrupt source or an interrupt request that is not used as a DTC activation source (DTA = 1), the interrupt request flag is cleared automatically by the DMA transfer. With ADI, TXI and RXI interrupts, however, the interrupt source flag is not cleared unless the relevant register is accessed in a DMA transfer.
Page 280: Operation
Operation 7.5.1 Transfer Modes Table 7.4 lists the DMAC transfer modes. Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual address mode TPU channel 0 to 5 Up to 4 channels can address • compare match/input operate independently 1-byte or 1-word transfer mode...
Page 281 Transfer Mode Transfer Source Remarks • • Short Single address mode TPU channel 0 to 5 Up to 4 channels can address • compare match/input operate independently 1-byte or 1-word transfer mode capture A interrupt • for a single transfer External request •...
Page 282: Sequential Mode
7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR.
Page 283: Figure 7.3 Operation In Sequential Mode
Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N – 1)) Where : L = Value set in MAR Address B N = Value set in ETCR Figure 7.3 Operation in Sequential Mode...
Page 284: Idle Mode
[1] Set each bit in DMABCRH. Sequential mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 285: Figure 7.5 Operation In Idle Mode
by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.6 Register Functions in Idle Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting Operation Source Destination Start address of...
Page 286: Repeat Mode
[1] Set each bit in DMABCRH. Idle mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 287: Table 7.7 Register Functions In Repeat Mode
their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in repeat mode. Table 7.7 Register Functions in Repeat Mode Function Register DTDIR = 0 DTDIR = 1 Initial Setting...
Page 288: Figure 7.7 Operation In Repeat Mode
not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR...
Page 289: Single Address Mode
[1] Set each bit in DMABCRH. Repeat mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address and transfer destination address in MAR and IOAR.
Page 290: Table 7.8 Register Functions In Single Address Mode
One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.8 Register Functions in Single Address Mode Function...
Page 291: Figure 7.9 Operation In Single Address Mode (When Sequential Mode Is Specified)
Address T Transfer 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N – 1)) Where : L = Value set in MAR Address B N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified)
Page 292: Normal Mode
[1] Set each bit in DMABCRH. Single address • Clear the FAE bit to 0 to select short address mode setting mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal Set DMABCRH interrupt clearing with the DTA bit.
Page 293: Table 7.9 Register Functions In Normal Mode
to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7.9 summarizes register functions in normal mode. Table 7.9 Register Functions in Normal Mode Register Function Initial Setting...
Page 294: Figure 7.11 Operation In Normal Mode
Address T Transfer Address T Address B Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) · (2 · (N – 1)) DAID DTSZ Address + DAIDE · (–1) · (2 · (N – 1)) Where : = Value set in MARA = Value set in MARB = Value set in ETCRA...
Page 295: Block Transfer Mode
[1] Set each bit in DMABCRH. Normal mode setting • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Set DMABCRH [2] Set the transfer source address in MARA, and the transfer destination address in MARB.
Page 296: Table 7.10 Register Functions In Block Transfer Mode
ETCRB. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7.10 summarizes register functions in block transfer mode. Table 7.10 Register Functions in Block Transfer Mode Register Function...
Page 297: Figure 7.13 Operation In Block Transfer Mode (Blkdir = 0)
Address T Address T 1st block Block area Transfer Address B Consecutive transfer of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) ·...
Page 298: Figure 7.14 Operation In Block Transfer Mode (Blkdir = 1)
Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in response to one request 2nd block Nth block Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) ·...
Page 299: Figure 7.15 Operation Flow In Block Transfer Mode
Figure 7.15 shows the operation flow in block transfer mode. Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID DTSZ MARA = MARA + SAIDE·(–1) ·2 Write to address specified by MARB DAID DTSZ MARB = MARB + DAIDE·(–1) ·2...
Page 300: Figure 7.16 Example Of Block Transfer Mode Setting Procedure
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH.
Page 301: Basic Bus Cycles
7.5.8 Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, word- size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed.
Page 302: Figure 7.18 Example Of Short Address Mode Transfer
read read read write write write dead Address bus Bus release Bus release Bus release Last transfer cycle release Figure 7.18 Example of Short Address Mode Transfer A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
Page 303: Figure 7.19 Example Of Full Address Mode Transfer (Cycle Steal)
read write read write read write dead Address bus Bus release Bus release Bus release Last transfer cycle release Figure 7.19 Example of Full Address Mode Transfer (Cycle Steal) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
Page 304: Figure 7.20 Example Of Full Address Mode Transfer (Burst Mode)
read write read write read write dead Address bus Last transfer cycle Bus release Bus release Burst transfer Figure 7.20 Example of Full Address Mode Transfer (Burst Mode) In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle.
Page 305: Figure 7.21 Example Of Full Address Mode Transfer (Block Transfer Mode)
read write read write dead read write read write dead Address bus Bus release Block transfer Bus release Last block transfer release Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode) A one-block transfer is performed for a single transfer request, and after the transfer the bus is released.
Page 306: Figure 7.22 Example Of Dreq Pin Falling Edge Activated Normal Mode Transfer
Bus release read write release read write release Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle control Channel Request clear period Request Request clear period Request Minimum Minimum of 2 cycles of 2 cycles Acceptance resumes Acceptance resumes Acceptance after transfer enabling;...
Page 307: Figure 7.23 Example Of Dreq Pin Falling Edge Activated Block Transfer Mode Transfer
1 block transfer 1 block transfer Bus release read write dead release read write dead release Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Dead Idle Read Write Dead Idle control Request clear period Request clear period Channel Request Request...
Page 308: Figure 7.24 Example Of Dreq Pin Low Level Activated Normal Mode Transfer
release read write release read write release Address Transfer source Transfer destination Transfer source Transfer destination Idle Read Write Idle Read Write Idle control Channel Request Request clear period Request clear period Request Minimum Minimum of 2 cycles of 2 cycles Acceptance resumes Acceptance resumes Acceptance after transfer enabling;...
Page 309: Dma Transfer (Single Address Mode) Bus Cycles
1 block transfer 1 block transfer Bus release read write dead release read write dead release Address Transfer source Transfer source Transfer destination Transfer destination Idle Read Write Dead Idle Read Write Dead Idle control Request clear period Request clear period Channel Request Request...
Page 310: Figure 7.26 Example Of Single Address Mode Transfer (Byte Read)
DMA read DMA read DMA read DMA read dead Address bus Last transfer release release release release cycle release Figure 7.26 Example of Single Address Mode Transfer (Byte Read) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
Page 311: Figure 7.28 Example Of Single Address Mode Transfer (Byte Write)
In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. Single Address Mode (Write): Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
Page 312: Figure 7.29 Example Of Single Address Mode Transfer (Word Write)
DMA write DMA write DMA write dead Address bus Last transfer release release release cycle release Figure 7.29 Example of Single Address Mode Transfer (Word Write) A byte or word transfer is performed for a single transfer request, and after the transfer, the bus is released.
Page 313: Figure 7.30 Example Of Dreq Pin Falling Edge Activated Single Address Mode Transfer
Bus release DMA single Bus release DMA single Bus release Transfer source/ Transfer source/ Address bus destination destination DMA control Idle Single Idle Single Idle Request clear Request clear Channel Request Request period period Minimum of Minimum of 2 cycles 2 cycles Acceptance resumes Acceptance resumes...
Page 314: Figure 7.31 Example Of Dreq Pin Low Level Activated Single Address Mode Transfer
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level. Bus release DMA single Bus release DMA single release Transfer source/ Transfer source/ Address bus destination destination Single DMA control Idle Idle Single Idle Request clear Request clear...
Page 315: Write Data Buffer Function
7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, external write cycles in dual address transfers or single address transfers are executed in parallel with internal accesses (on-chip memory or internal I/O registers).
Page 316: Multi-Channel Operation
read single read single read Internal address Internal read signal External address Figure 7.33 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer.
Page 317: Relation Between Dmac And External Bus Requests And Refresh Cycles
read DMA read DMA write DMA read DMA write DMA read DMA write Address bus DMA control Idle Read Write Idle Read Write Idle Read Write Read Channel 0A Request clear Request clear Request Selection Channel 0B hold Request clear Request Request Non-...
Page 318: Dmac And Nmi Interrupts
7.5.14 DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are set to 1.
Page 319: Clearing Full Address Mode
[1] Clear the DTE bit in DMABCRL to 0. Forced termination To prevent interrupt generation after forced of DMAC termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 Forced termination Figure 7.36 Example of Procedure for Forcibly Terminating DMAC Operation 7.5.16 Clearing Full Address Mode...
Page 320: Interrupt Sources
[1] Clear both the DTE bit and DTME bit in Clearing full DMABCRL to 0, or wait until the transfer ends address mode and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time.
Page 321: Usage Notes
Enabling or disabling of each interrupt source is set by means of the DTIE bit in DMABCRL for the corresponding channel in DMABCRL, and interrupts from each source are sent to the interrupt controller independently. The priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7.12.
Page 322: Figure 7.39 Dmac Register Update Timing
DMA last transfer cycle DMA transfer cycle dead DMA read DMA read DMA write DMA write DMA Internal Transfer Transfer Transfer Transfer destination source source destination address Read Idle Idle Read DMA control Write Idle Write Dead DMA register [2'] operation [1] Transfer source address register MAR operation (incremented/decremented/fixed) Transfer counter ETCR operation (decremented)
Page 323: Module Stop
7.7.2 Module Stop When the MSTP13 bit in MSTPCRH is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP13 bit if any of the DMAC channels is enabled.
Page 324: Activation By Falling Edge On Dreq Pin
4. CBR refresh cycle Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2 above. If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in synchronization with the bus cycle.
Page 325: Activation Source Acceptance
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed on detection of a low level. 7.7.6 Activation Source Acceptance At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing.
Page 326 Rev. 2.00, 05/03, page 274 of 820...
Page 327: Section 8 Data Transfer Controller (Dtc)
Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. Features • Transfer possible over any number of channels •...
Page 328: Register Descriptions
Internal address bus On-chip Interrupt controller Interrupt request CPU interrupt Internal data bus request Legend MRA, MRB : DTC mode registers A and B CRA, CRB : DTC transfer count registers A and B : DTC source address register : DTC destination address register DTCERA to DTCERG : DTC enable registers A to G DTVECR...
Page 329: Dtc Mode Register A (Mra)
8.2.1 DTC Mode Register A (MRA) MRA selects the DTC operating mode. Bit Name Initial Value Description − Undefined Source Address Mode 1 and 0 − Undefined These bits specify an SAR operation after a data transfer. 0x: SAR is fixed 10: SAR is incremented after a transfer (by +1 when Sz = 0;...
Page 330: Dtc Mode Register B (Mrb)
8.2.2 DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Name Initial Value Description − CHNE Undefined DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 8.5.4, Chain Transfer.
Page 331: Dtc Transfer Count Register B (Crb)
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL).
Page 332: Activation Sources
Bit Name Initial Value Description SWDTE DTC Software Activation Enable Setting this bit to 1 activates DTC. Only 1 can be written to this bit. [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended •...
Page 333: Location Of Register Information And Dtc Vector Table
Table 8.1 Relationship between Activation Sources and DTCER Clearing DISEL = 0 and Specified Number of Transfers Has DISEL = 1 or Specified Number Activation Source Not Ended of Transfers Has Ended • Activation by software SWDTE bit is cleared to 0 SWDTE bit remains set to 1 •...
Page 334: Figure 8.3 Correspondence Between Dtc Vector Address And Register Information
register information from the vector address set for each activation source, and then reads the register information from that start address. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420. The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases.
Page 335: Table 8.2 Interrupt Sources, Dtc Vector Addresses, And Corresponding Dtces
Table 8.2 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Activation Activation Source Source Vector Number Vector Address DTCE* Priority Software Write to DTVECR DTVECR H'0400 + (DTVECR — High [6:0] × 2) External pin IRQ0 H'0420 DTCEA7 IRQ1 H'0422 DTCEA6...
Page 336: Operation
Origin of Activation Activation Source Source Vector Number Vector Address DTCE* Priority TMR_0 CMIA0 H'0490 DTCEE3 High CMIB0 H'0492 DTCEE2 TMR_1 CMIA1 H'0498 DTCEE1 CMIB1 H'049A DTCEE0 DMAC* DMTEND0A H'04A0 DTCEF7 DMTEND0B H'04A2 DTCEF6 DMTEND1A H'04A4 DTCEF5 DMTEND1B H'04A6 DTCEF4 SCI_0 RXI0 H'04B2...
Page 337: Figure 8.5 Flowchart Of Dtc Operation
Figure 8.5 shows a flowchart of DTC operation, and table 8.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted). Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? CHNS = 0? Transfer counter = 0...
Page 338: Normal Mode
Table 8.3 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CHNE CHNS DISEL DTC Transfer — Not 0 — — — — Ends at 1st transfer — — — — — Ends at 1st transfer — — — —...
Page 339: Repeat Mode
Transfer Figure 8.6 Memory Mapping in Normal Mode 8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 8.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 340: Block Transfer Mode
Repeat area Transfer Figure 8.7 Memory Mapping in Repeat Mode 8.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.6 lists the register function in block transfer mode.
Page 341: Chain Transfer
First block Block area Transfer Nth block Figure 8.8 Memory Mapping in Block Transfer Mode 8.5.4 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Page 342: Interrupts
Source Destination Register information CHNE=1 Register information DTC vector start address address Register information CHNE=0 Source Destination Figure 8.9 Operation of Chain Transfer 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1.
Page 343: Operation Timing
8.5.6 Operation Timing φ DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request request Data transfer Vector read Read Write Read Write Address...
Page 344: Number Of Dtc Execution States
8.5.7 Number of DTC Execution States Table 8.7 lists execution status for a single DTC data transfer, and table 8.7 shows the number of states required for each execution status. Table 8.7 DTC Execution Status Register Information Internal Vector Read Read/Write Data Read Data Write...
Page 345: Procedures For Using Dtc
Procedures for Using DTC 8.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. 2. Set the start address of the register information in the DTC vector address. 3.
Page 346: Chain Transfer
3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts.
Page 347: Chain Transfer When Counter = 0
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU.
Page 348: Software Activation
Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data Upper 8 bits transfer register of DAR information Figure 8.13 Chain Transfer when Counter = 0 8.7.4 Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation.
Page 349: Usage Notes
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. 6.
Page 350 Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. Rev. 2.00, 05/03, page 298 of 820...
Page 351: Section 9 I/O Ports
Section 9 I/O Ports Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Page 352: Table 9.1 Port Functions
Table 9.1 Port Functions Mode 7 Input/ Output EXPE = 1 EXPE = 0 Type Port Description Mode 1* Mode 2* Mode 4 Port 1 General I/O port P17/PO15* /TIOCB2/TCLKD Schmitt- also functioning triggered P16/PO14* /TIOCA2 as PPG outputs* input P15/PO13* /TIOCB1/TCLKC/DACK1* TPU I/Os, and...
Page 353 Mode 7 Input/ Output Port Description Mode 1* Mode 2* Mode 4 EXPE = 1 EXPE = 0 Type Port 5 General I/O port P53/ADTRG/IRQ3 Schmitt- also functioning triggered P52/SCK2/IRQ2 as interrupt inputs, input when P51/RxD2/IRQ1 A/D converter used as inputs, and SCI IRQ input P50/TxD2/IRQ0...
Page 354 Mode 7 Input/ Output Port Description Mode 1* Mode 2* Mode 4 EXPE = 1 EXPE = 0 Type Port C General I/O port PC7/A7 PC7/A7 Built-in also functioning MOS input PC6/A6 PC6/A6 as address pull-up PC5/A5 PC5/A5 outputs PC4/A4 PC4/A4 PC3/A3 PC3/A3...
Page 355: Port 1
Mode 7 Input/ Output EXPE = 1 EXPE = 0 Port Description Mode 1* Mode 2* Mode 4 Type Port G General I/O port PG6/BREQ PG6/BREQ also functioning PG5/BACK PG5/BACK as bus control PG4/CS4/BREQO PG4/CS4/ I/Os BREQO PG3/CS3/RAS3* PG3/CS3/ RAS3* PG2/CS2/RAS2* PG2/CS2/ RAS2*...
Page 356: Port 1 Data Register (P1Dr)
9.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Name Initial Value Description P17DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. P16DR P15DR P14DR P13DR...
Page 357: Pin Functions
9.1.4 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os*, and DMAC outputs*. The correspondence between the register specification and the pin functions is shown below. Note: * Not supported by the H8S/2366. • P17/PO15* /TIOCB2/TCLKD The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1...
Page 358 • P16/PO14* /TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14* in NDERH, and bit P16DDR.
Page 359 • P15/PO13* /TIOCB1/TCLKC/DACK1* The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bits TPSC2 to TPSC0 in TCR_0, TCR_2, TCR_4, and TCR_5, bit NDER13* in NDERH, bit SAE1* in DMA BCRH and bit P15DDR.
Page 360 • P14/PO12* /TIOCA1/DACK0* The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12* in NDERH, bit SAE0* in DMABCRH and bit P14DDR.
Page 361 • P13/PO11* /TIOCD0/TCLKB/TEND1* The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_2, bit NDER11* in NDERH, bit TEE1* in DMATCR of DMAC and bit P13DDR.
Page 362 • P12/PO10* /TIOCC0/TCLKA/TEND0* The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10* in NDERH, bit TEE0* in DMATCR of DMAC and bit P12DDR.
Page 363 • P11/PO9* /TIOCB0/DREQ1* The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9* in NDERH, and bit P11DDR.
Page 364 • P10/PO8* /TIOCA0/DREQ0* The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8* in NDERH, and bit P10DDR.
Page 365: Port 2
Port 2 Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers. • Port 2 data direction register (P2DDR) • Port 2 data register (P2DR) • Port 2 register (PORT2) 9.2.1 Port 2 Data Direction Register (P2DDR) The individual bits of P2DDR specify input or output for the pins of port 2.
Page 366: Port 2 Register (Port2)
9.2.3 Port 2 Register (PORT2) PORT2 shows the pin states. PORT2 cannot be modified. Bit Name Initial Value Description If a port 2 read is performed while P2DDR bits are —* set to 1, the P2DR values are read. If a port 2 read is —* performed while P2DDR bits are cleared to 0, the pin —*...
Page 367: Pin Functions
9.2.4 Pin Functions Port 2 pins also function as PPG outputs*, TPU I/Os, and TMR I/Os. The correspondence between the register specification and the pin functions is shown below. Note: * Not supported by the H8S/2366. • P27/PO7* /TIOCB5 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7* in NDERL, and bit P27DDR.
Page 368 • P26/PO6* /TIOCA5 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6* in NDERL, and bit P26DDR.
Page 369 • P25/PO5* /TIOCB4/TMO1 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER5* in NDERL, bit P25DDR, and bits OS3 to USO in TCSRI of TMR.
Page 370 • P24/PO4* /TIOCA4/RxD4/TMO0 The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR4), bit NDER4* in NDERL, bit RE in SCI_4, bit P24DDR, and bit OS3 to OS0 in TCSRO of TMR.
Page 371 • P23/PO3* /TIOCD3/TXD4/TMCI1 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3* in NDERL, bit TE in SCR of SCI_4, and bit P23DDR.
Page 372 • P22/PO2* /TIOCC3/TMCI0 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2* in NDERL, and bit P22DDR.
Page 373 • P21/PO1* /TIOCB3/TMRI1 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1* in NDERL, and bit P21DDR.
Page 374 • P20/PO0* /TIOCA3/TMRI0 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0* in NDERL, and bit P20DDR.
Page 375: Port 3
Port 3 Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers. • Port 3 data direction register (P3DDR) • Port 3 data register (P3DR) • Port 3 register (PORT3) • Port 3 open drain control register (P3ODR) •...
Page 376: Port 3 Data Register (P3Dr)
9.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P35DR Output data for a pin is stored when the pin function is specified to a general purpose I/O.
Page 377: Port 3 Open Drain Control Register (P3Odr)
9.3.4 Port 3 Open Drain Control Register (P3ODR) P3ODR controls the output status for each port 3 pin. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P35ODR Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while P34ODR...
Page 378: Port Function Control Register 2 (Pfcr2)
9.3.5 Port Function Control Register 2 (PFCR2) PFCR2 controls the I/O port. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be modified. AS Output Enable ASOE Selects to enable or disable the AS output pin. 0: PF6 is designated as I/O port 1: PF6 is designated as AS output pin LWR Output Enable...
Page 379: Pin Functions
9.3.6 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I C output, and a bus control signal output. The correspondence between the register specification and the pin functions is shown below. • P35/SCK1/SCL0/(OE)* The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of I C_0, C/A bit in SMR of SCI_1, bits CKE0 and CKE1 in SCR, bits OEE in DRAMCR, bit OES in PFCR2, and bit P35DDR.
Page 380 • P34/SCK0/SCK4/SDA0 The pin function is switched as shown below according to the combination of bit ICE in ICCRA of I C_0, bit C/A in SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 — — — CKE0 —...
Page 381 • P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in SCR of SCI_1 and bit P31DDR. P31DDR — Pin function P31 input P31 output* TxD1 output* Note: * NMOS open-drain output when P31ODR = 1. •...
Page 382: Port 4
Port 4 Port 4 is an 8-bit input-only port. Port 4 has the following register. • Port 4 register (PORT4) 9.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows port 4 pin states. PORT4 cannot be modified. Bit Name Initial Value Description...
Page 383: Pin Functions
9.4.2 Pin Functions Port 4 also functions as the pins for A/D converter analog input and D/A converter analog output. The correspondence between pins are as follows. IRQ7) IRQ7 IRQ7 P47/AN7/(IRQ7 Pin function AN7 input IRQ7 interrupt input* Note: * IRQ7 input when bit ITS7 in ITSR is 1. IRQ6) IRQ6 IRQ6...
Page 384 IRQ2 IRQ2 IRQ2) P42/AN2/(IRQ2 Pin function AN2 input IRQ2 interrupt input* Note: * IRQ2 input when bit ITS2 in ITSR is 1. IRQ1) IRQ1 IRQ1 P41/AN1/(IRQ1 Pin function AN1 input IRQ1 interrupt input* Note: * IRQ1 input when bit ITS1 in ITSR is 1. IRQ0 IRQ0 IRQ0)
Page 385: Port 5
Port 5 Port 5 is a 4-bit I/O port. The port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) • Port 5 register (PORT5) 9.5.1 Port 5 Data Direction Register (P5DDR) The individual bits of P5DDR specify input or output for the pins of port 5.
Page 386: Port 5 Register (Port5)
9.5.3 Port 5 Register (PORT5) PORT5 shows the pin states. PORT5 cannot be modified. Bit Name Initial Value Description — Undefined Reserved Undefined values are read from these bits. —* If bits P53 to P50 are read while P5DDR bits are set to 1, the P5DR values are read.
Page 387 • P52/SCK2/IRQ2 The pin function is switched as shown below according to the combination of bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 — CKE0 — — P52DDR —...
Page 388: Port 8
Port 8 Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) • Port 8 register (PORT8) 9.6.1 Port 8 Data Direction Register (P8DDR) The individual bits of P8DDR specify input or output for the pins of port 8.
Page 389: Port 8 Data Register (P8Dr)
9.6.2 Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Name Initial Value Description — — Reserved These bits are always read as 0 and cannot be — — modified. P85DR Bits 5, 3, and 1 store output data when the pin function is specified to a general purpose I/O.
Page 390: Pin Functions
9.6.4 Pin Functions Port 8 pins also function as interrupt inputs and SCI_3 I/Os. The correspondence between the register specification and the pin functions is shown below. • P85/SCK3 The pin function is switched as shown below according to the combination of bit C/A in SMR in SCI_3, bits CKE0 and CKE1 in SCR, and bit P85DDR.
Page 391: Port 9
Port 9 Port 9 is a 2-bit input-only port. Port 9 has the following register. • Port 9 register (PORT9) 9.7.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows port 4 pin states. PORT9 cannot be modified. Bit Name Initial Value Description...
Page 392: Port A
Port A Port A is an 8-bit I/O port that also has other functions. The port A has the following registers. • Port A data direction register (PADDR) • Port A data register (PADR) • Port A register (PORTA) • Port A MOS zcontrol register (PAPCR) •...
Page 393: Port A Data Direction Register (Paddr)
9.8.1 Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Name Initial Value Description •...
Page 394: Port A Data Register (Padr)
9.8.2 Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Name Initial Value Description PA7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PA6DR PA5DR PA4DR PA3DR...
Page 395: Port A Mos Pull-Up Control Register (Papcr)
9.8.4 Port A MOS Pull-Up Control Register (PAPCR) PAPCR controls the MOS input pull-up function. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Name Initial Value Description PA7PCR When PADDR = 0 (input port), setting the...
Page 396: Port Function Control Register 0 (Pfcr0)
9.8.6 Port Function Control Register 0 (PFCR0) PFCR0 controls the I/O port. Bit Name Initial Value Description CS7 to CS0 enable CS7E Enable/disable corresponding CSn output. CS6E 0: Set as I/O port. CS5E 1: Set as CSn output pin. CS4E (n = 7 to 0) CS3E CS2E...
Page 397: Pin Functions
Bit Name Initial Value Description A19E Address 19 Enable Enables or disables output for address output 19 (A19). 0: DR output when PA3DDR = 1 1: A19 output when PA3DDR = 1 A18E Address 18 Enable Enables or disables output for address output 18 (A18). 0: DR output when PA2DDR = 1 1: A18 output when PA2DDR = 1 A17E...
Page 398 • PA6/A22/IRQ6, PA5/A21/IRQ5 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A22E and A21E, bits IS6 and ITS5 in ITSR, and bit PAnDDR. Operating 1, 2, 4 mode EXPE — AxxE — PADDR Pin function Address...
Page 399: Port A Mos Input Pull-Up States
• PA3/A19, PA2/A18, PA1/A17, PA0/A16 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A19E to A16E, and bit PADDR. Operating 1, 2 mode EXPE — — AxxE — — PAnDDR — Pin function Address Address Address output...
Page 400: Port B
Port B Port B is an 8-bit I/O port that also has other functions. The port B has the following registers. • Port B data direction register (PBDDR) • Port B data register (PBDR) • Port B register (PORTB) • Port B MOS pull-up control register (PBPCR) 9.9.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B.
Page 401: Port B Data Register (Pbdr)
9.9.2 Port B Data Register (PBDR) PBDR is stores output data for the port B pins. Bit Name Initial Value Description PB7DR An output data for a pin is stored when the pin function is specified to a general purpose I/O. PB6DR PB5DR PB4DR...
Page 402: Port B Mos Pull-Up Control Register (Pbpcr)
9.9.4 Port B MOS Pull-Up Control Register (PBPCR) PBPCR controls the on/off state of MOS input pull-up of port B. PBPCR is valid in modes 4 and Bit Name Initial Value Description PB7PCR When PBDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pull-up PB6PCR for that pin.
Page 403: Port B Mos Input Pull-Up States
9.9.6 Port B MOS Input Pull-Up States Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 404: Port C
9.10 Port C Port C is an 8-bit I/O port that also has other functions. The port C has the following registers. • Port C data direction register (PCDDR) • Port C data register (PCDR) • Port C register (PORTC) •...
Page 405: Port C Data Register (Pcdr)
9.10.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Name Initial Value Description PC7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PC6DR PC5DR PC4DR PC3DR...
Page 406: Port C Mos Pull-Up Control Register (Pcpcr)
9.10.4 Port C MOS Pull-Up Control Register (PCPCR) PCPCR controls the on/off state of MOS input pull-up of port C. PCPCR is valid in modes 4 and Bit Name Initial Value Description PC7PCR When PCDDR = 0 (input port), setting the corresponding bit to 1 turns on the MOS input pull-up PC6PCR for that pin.
Page 407: Port C Mos Input Pull-Up States
9.10.6 Port C MOS Input Pull-Up States Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 408: Port D
9.11 Port D Port D is an 8-bit I/O port that also has other functions. The port D has the following registers. • Port D data direction register (PDDDR) • Port D data register (PDDR) • Port D register (PORTD) •...
Page 409: Port D Register (Portd)
9.11.3 Port D Register (PORTD) PORTD shows port D pin states. PORTD cannot be modified. Bit Name Initial Value Description If a port D read is performed while PDDDR bits are —* set to 1, the PDDR values are read. If a port D read —* is performed while PDDDR bits are cleared to 0, the —*...
Page 410: Pin Functions
9.11.5 Pin Functions Port D pins also function as the pins for data I/Os. The correspondence between the register specification and the pin functions is shown below. • PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8 The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PDDDR.
Page 411: Port E
9.12 Port E Port E is an 8-bit I/O port that also has other functions. The port E has the following registers. • Port E data direction register (PEDDR) • Port E data register (PEDR) • Port E register (PORTE) •...
Page 412: Port E Data Register (Pedr)
9.12.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Name Initial Value Description PE7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PE6DR PE5DR PE4DR PE3DR...
Page 413: Port E Pull-Up Control Register (Pepcr)
9.12.4 Port E Pull-up Control Register (PEPCR) PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus mode. Bit Name Initial Value Description PE7PCR When PEDDR = 0 (input port), the input pull-up MOS of the input pin is on when the corresponding PE6PCR bit is set to 1.
Page 414: Port E Mos Input Pull-Up States
9.12.6 Port E MOS Input Pull-Up States Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in 8-bit bus mode. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 415: Port F Data Direction Register (Pfddr)
9.13.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. Bit Name Initial Value Description •...
Page 416: Port F Data Register (Pfdr)
9.13.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Name Initial Value Description PF7DR Output data for a pin is stored when the pin function is specified to a general purpose I/O. PF6DR PF5DR PF4DR PF3DR...
Page 417: Pin Functions
9.13.4 Pin Functions Port F pins also function as the pins for external interrupt inputs, bus control signal I/Os, and system clock outputs (φ). The correspondence between the register specification and the pin functions is shown below. • PF7/φ The pin function is switched as shown below according to bit PF7DDR. Operating 1, 2, 4, 7 mode...
Page 418 • PF4/HWR The pin function is switched as shown below according to the operating mode, bit EXPE, and bit PF4DDR. Operating 1, 2, 4 mode EXPE — PF4DDR — — HWR output HWR output Pin function PF4 input PF4 output •...
Page 419 • PF2/CS6/LCAS* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0* in DRAMCR, bits ABW5 to ABW2 in ABWCR, and bit PF2DDR. Operating 1, 2, 4 3, 7 mode EXPE —...
Page 420: Port G
• PF0/WAIT/OE The pin function is switched as shown below according to the operating mode, bit EXPE, bit WAITE, bit OEE in DRAMCR, bit OES in PFCR2, and bit PF0DDR. Operating 1, 2, 4 mode EXPE — OEE* — OES* —...
Page 421 Bit Name Initial Value Description — — Reserved • PG6DDR Modes 1, 2, 4, and 7 (when EXPE = 1) Pins PG6 and PG5 function as bus control PG5DDR input/output pins (BREQ and BACK) when the PG4DDR appropriate bus controller settings are made. PG3DDR Otherwise, these pins are I/O ports, and their functions can be switched with PGDDR.
Page 422: Port G Data Register
9.14.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Name Initial Value Description — — Reserved This bit is always read as 0, and cannot be modified. PG6DR An output data for a pin is stored when the pin function is specified to a general purpose I/O.
Page 423: Pin Functions
9.14.4 Pin Functions Port G pins also function as the pins for bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below. • PG6/BREQ The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, and bit PG6DDR.
Page 424 • PG4/CS4/BREQO The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, bit BREQO, bit CS4E and bit PG4DDR. • PG3/CS3/RAS3*, PG2/CS2/RAS2* The pin function is switched as shown below according to the operating mode, bit EXPE, bit PGnDDR, bit CSnE, and bits RMTS2 to RMTS0*.
Page 425: Section 10 16-Bit Timer Pulse Unit (Tpu)
Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 and figure 10.1, respectively.
Page 426: Table 10.1 Tpu Functions
Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 φ/1 φ/1 φ/1 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/16 φ/16 φ/16 φ/64 φ/64 φ/64 φ/64 φ/64 φ/64...
Page 427 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture input capture input capture DMAC...
Page 428: Figure 10.1 Block Diagram Of Tpu
Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5 Channel 5: TGI5A TGI5B TCI5V TCI5U Clock input Internal clock: ø/1 ø/4...
Page 429: Input/Output Pins
10.2 Input/Output Pins Table 10.2 Pin Configuration Channel Symbol Function TCLKA Input External clock A input pin (Channels 1 and 5 phase counting mode A phase input) TCLKB Input External clock B input pin (Channels 1 and 5 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 430: Register Descriptions
10.3 Register Descriptions The TPU has the following registers in each channel. • Timer control register_0 (TCR_0) • Timer mode register_0 (TMDR_0) • Timer I/O control register H_0 (TIORH_0) • Timer I/O control register L_0 (TIORL_0) • Timer interrupt enable register_0 (TIER_0) •...
Page 431 • Timer general register A_3 (TGRA_3) • Timer general register B_3 (TGRB_3) • Timer general register C_3 (TGRC_3) • Timer general register D_3 (TGRD_3) • Timer control register_4 (TCR_4) • Timer mode register_4 (TMDR_4) • Timer I/O control register _4 (TIOR_4) •...
Page 432: Timer Control Register (Tcr)
10.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Name Initial Value Description...
Page 433: Table 10.3 Cclr2 To Cclr0 (Channels 0 And 3)
Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* TCNT clearing disabled...
Page 434: Table 10.5 Tpsc2 To Tpsc0 (Channel 0)
Table 10.5 TPSC2 to TPSC0 (Channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 435: Table 10.7 Tpsc2 To Tpsc0 (Channel 2)
Table 10.7 TPSC2 to TPSC0 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024...
Page 436: Table 10.9 Tpsc2 To Tpsc0 (Channel 4)
Table 10.9 TPSC2 to TPSC0 (Channel 4) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024 Counts on TCNT5 overflow/underflow...
Page 437: Timer Mode Register (Tmdr)
10.3.2 Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Name Initial Value Description –...
Page 438: Timer I/O Control Register (Tior)
Table 10.11 MD3 to MD0 Bit 3 Bit 2 Bit 1 Bit 0 MD3* MD2* Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 439 TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 Initial Bit Name Value Description IOB3 I/O Control B3 to B0 IOB2 Specify the function of TGRB. IOB1 For details, see tables 10.12, 10.14, 10.15, 10.16, IOB0 10.18, and 10.19. IOA3 I/O Control A3 to A0 IOA2 Specify the function of TGRA.
Page 440: Table 10.12 Tiorh_0
Table 10.12 TIORH_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOCB0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 441: Table 10.13 Tiorl_0
Table 10.13 TIORL_0 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOCD0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 442: Table 10.14 Tior_1
Table 10.14 TIOR_1 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOCB1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 443: Table 10.15 Tior_2
Table 10.15 TIOR_2 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOCB2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 444: Table 10.16 Tiorh_3
Table 10.16 TIORH_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_3 IOB3 IOB2 IOB1 IOB0 Function TIOCB3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 445: Table 10.17 Tiorl_3
Table 10.17 TIORL_3 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_3 IOD3 IOD2 IOD1 IOD0 Function TIOCD3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 446: Table 10.18 Tior_4
Table 10.18 TIOR_4 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_4 IOB3 IOB2 IOB1 IOB0 Function TIOCB4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 447: Table 10.19 Tior_5
Table 10.19 TIOR_5 Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_5 IOB3 IOB2 IOB1 IOB0 Function TIOCB5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 448: Table 10.20 Tiorh_0
Table 10.20 TIORH_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOCA0 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 449: Table 10.21 Tiorl_0
Table 10.21 TIORL_0 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOCC0 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 450: Table 10.22 Tior_1
Table 10.22 TIOR_1 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOCA1 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 451: Table 10.23 Tior_2
Table 10.23 TIOR_2 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOCA2 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 452: Table 10.24 Tiorh_3
Table 10.24 TIORH_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_3 IOA3 IOA2 IOA1 IOA0 Function TIOCA3 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 453: Table 10.25 Tiorl_3
Table 10.25 TIORL_3 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 IOC3 IOC2 IOC1 IOC0 Function TIOCC3 Pin Function Output Output disabled compare Initial output is 0 output register* 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 454: Table 10.26 Tior_4
Table 10.26 TIOR_4 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_4 IOA3 IOA2 IOA1 IOA0 Function TIOCA4 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 455: Table 10.27 Tior_5
Table 10.27 TIOR_5 Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_5 IOA3 IOA2 IOA1 IOA0 Function TIOCA5 Pin Function Output Output disabled compare Initial output is 0 output register 0 output at compare match Initial output is 0 output 1 output at compare match Initial output is 0 output Toggle output at compare match...
Page 456: Timer Interrupt Enable Register (Tier)
10.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Name Initial value Description TTGE A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
Page 457 Bit Name Initial value Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
Page 458: Timer Status Register (Tsr)
10.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Name Initial value Description TCFD Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5.
Page 459 Bit Name Initial value Description TGFD R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Page 460: Timer Counter (Tcnt)
Bit Name Initial value Description TGFB R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] • When TCNT = TGRB while TGRB is functioning as output compare register •...
Page 461: Timer General Register (Tgr)
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR) The TGR registers are 16-bit readable/writable registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5.
Page 462: Timer Synchronous Register (Tsyr)
10.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Name Initial value Description –...
Page 463: Operation
10.4 Operation 10.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
Page 464: Figure 10.3 Free-Running Counter Operation
2. Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 465: Figure 10.4 Periodic Counter Operation
Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 10.4 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match.
Page 466: Figure 10.6 Example Of 0 Output/1 Output Operation
2. Examples of waveform output operation Figure 10.6 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
Page 467: Figure 10.8 Example Of Setting Procedure For Input Capture Operation
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Page 468: Synchronous Operation
Counter cleared by TIOCB TCNT value input (falling edge) H'0180 H'0160 H'0010 H'0005 Time H'0000 TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.9 Example of Input Capture Operation 10.4.2 Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting).
Page 469: Figure 10.10 Example Of Synchronous Operation Setting Procedure
Synchronous operation selection Set synchronous operation Synchronous presetting Synchronous clearing Set TCNT Clearing source generation channel? Select counter Set synchronous clearing source counter clearing Start count Start count <Synchronous presetting> <Counter clearing> <Synchronous clearing> [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters.
Page 470: Buffer Operation
Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 Time TIOCA_0 TIOCA_1 TIOCA_2 Figure 10.11 Example of Synchronous Operation 10.4.3 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers.
Page 471: Figure 10.12 Compare Match Buffer Operation
Compare match signal Timer general Buffer register Comparator TCNT register Figure 10.12 Compare Match Buffer Operation • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register.
Page 472: Figure 10.14 Example Of Buffer Operation Setting Procedure
[1] Designate TGR as an input capture register or Buffer operation output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits Select TGR function BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Page 473: Figure 10.15 Example Of Buffer Operation (1)
TCNT value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 Time H'0000 H'0200 H'0450 H'0520 TGRC_0 Transfer H'0200 H'0450 TGRA_0 TIOCA Figure 10.15 Example of Buffer Operation (1) 2. When TGR is an input capture register Figure 10.16 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC.
Page 474: Cascaded Operation
TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA H'0532 H'0F07 H'09FB TGRA H'0532 H'0F07 TGRC Figure 10.16 Example of Buffer Operation (2) 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter.
Page 475: Figure 10.17 Cascaded Operation Setting Procedure
Example of Cascaded Operation Setting Procedure: Figure 10.17 shows an example of the setting procedure for cascaded operation. Set bits TPSC2 to TPSC0 in the channel 1 Cascaded operation (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation.
Page 476: Pwm Modes
TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 10.19 Example of Cascaded Operation (2) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR.
Page 477: Table 10.30 Pwm Output Registers And Output Pins
Table 10.30 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOCA0 TIOCA0 TGRB_0 TIOCB0 TGRC_0 TIOCC0 TIOCC0 TGRD_0 TIOCD0 TGRA_1 TIOCA1 TIOCA1 TGRB_1 TIOCB1 TGRA_2 TIOCA2 TIOCA2 TGRB_2 TIOCB2 TGRA_3 TIOCA3 TIOCA3 TGRB_3 TIOCB3...
Page 478: Figure 10.20 Example Of Pwm Mode Setting Procedure
Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 479: Figure 10.21 Example Of Pwm Mode Operation (1)
TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10.21 Example of PWM Mode Operation (1) Figure 10.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
Page 480: Figure 10.23 Example Of Pwm Mode Operation (3)
Figure 10.23 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 481: Phase Counting Mode
10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 482: Figure 10.25 Example Of Phase Counting Mode 1 Operation
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1. Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.32 summarizes the TCNT up/down-count conditions.
Page 483: Figure 10.26 Example Of Phase Counting Mode 2 Operation
2. Phase counting mode 2 Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.33 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count...
Page 484: Figure 10.27 Example Of Phase Counting Mode 3 Operation
3. Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 485: Figure 10.28 Example Of Phase Counting Mode 4 Operation
4. Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 486: Figure 10.29 Phase Counting Mode Application Example
Phase Counting Mode Application Example: Figure 10.29 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Page 487: Interrupts
10.5 Interrupts There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 488: Table 10.36 Tpu Interrupts
Table 10.36 TPU Interrupts Interrupt DMAC* Channel Name Interrupt Source Flag Activation Activation TGI0A TGRA_0 input capture/compare match TGFA_0 Possible Possible TGI0B TGRB_0 input capture/compare match TGFB_0 Possible Not possible TGI0C TGRC_0 input capture/compare match TGFC_0 Possible Not possible TGI0D TGRD_0 input capture/compare match TGFD_0 Possible Not possible...
Page 489: Dtc Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Page 490: Operation Timing
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 10.9 Operation Timing 10.9.1 Input/Output Timing TCNT Count Timing: Figure 10.30 shows TCNT count timing in internal clock operation, and figure 10.31 shows TCNT count timing in external clock operation.
Page 491: Figure 10.32 Output Compare Output Timing
φ TCNT input clock N + 1 TCNT Compare match signal TIOC pin Figure 10.32 Output Compare Output Timing Input Capture Signal Timing: Figure 10.33 shows input capture signal timing. φ Input capture input Input capture signal N + 1 N + 2 TCNT N + 2...
Page 492: Figure 10.34 Counter Clear Timing (Compare Match)
φ Compare match signal Counter clear signal H'0000 TCNT Figure 10.34 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal H'0000 TCNT Figure 10.35 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 10.36 and 10.37 show the timings in buffer operation. φ...
Page 493: Interrupt Signal Timing
φ Input capture signal N + 1 TCNT TGRA, N + 1 TGRB TGRC, TGRD Figure 10.37 Buffer Operation Timing (Input Capture) 10.9.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.38 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing.
Page 494: Figure 10.39 Tgi Interrupt Timing (Input Capture)
φ Input capture signal TCNT TGF flag TGI interrupt Figure 10.39 TGI Interrupt Timing (Input Capture) TCFV Flag/TCFU Flag Setting Timing: Figure 10.40 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 10.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing.
Page 495: Figure 10.41 Tciu Interrupt Setting Timing
φ TCNT input clock TCNT H'0000 H'FFFF (underflow) Underflow signal TCFU flag TCIU interrupt Figure 10.41 TCIU Interrupt Setting Timing Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it.
Page 496: Usage Notes
DTC/DMAC* DTC/DMAC* read cycle write cycle φ Destination Source address Address address Status flag Interrupt request signal Note: * Not supported by the H8S/2366. Figure 10.43 Timing for Status Flag Clearing by DTC/DMAC* Activation 10.10 Usage Notes 10.10.1 Module Stop Mode Setting TPU operation can be disabled or enabled using the module stop control register.
Page 497: 10.10.3 Caution On Cycle Setting
Phase Phase diffe- diffe- Pulse width Pulse width Overlap Overlap rence rence TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode 10.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated).
Page 498: 10.10.5 Contention Between Tcnt Write And Increment Operations
TCNT write cycle φ Address TCNT address Write signal Counter clearing signal H'0000 TCNT Figure 10.45 Contention between TCNT Write and Clear Operations 10.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Page 499: 10.10.6 Contention Between Tgr Write And Compare Match
10.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written.
Page 500: 10.10.8 Contention Between Tgr Read And Input Capture
TGR write cycle φ Buffer register Address address Write signal Compare match signal Buffer register write data Buffer register Figure 10.48 Contention between Buffer Register Write and Compare Match 10.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Page 501: 10.10.9 Contention Between Tgr Write And Input Capture
10.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.50 shows the timing in this case. TGR write cycle φ...
Page 502: 10.10.11 Contention Between Overflow/Underflow And Counter Clearing
Buffer register write cycle φ Buffer register Address address Write signal Input capture signal TCNT Buffer register Figure 10.51 Contention between Buffer Register Write and Input Capture 10.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence.
Page 503: 10.10.12 Contention Between Tcnt Write And Overflow/Underflow
10.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation timing when there is contention between TCNT write and overflow.
Page 504 Rev. 2.00, 05/03, page 452 of 820...
Page 505: Section 11 Programmable Pulse Generator (Ppg)
Section 11 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG)* provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently.
Page 506: Figure 11.1 Block Diagram Of Ppg
Compare match signals NDERH NDERL Control logic PO15 PO14 Pulse output PO13 pins, group 3 Internal PO12 PODRH NDRH PO11 data bus Pulse output PO10 pins, group 2 Pulse output pins, group 1 PODRL NDRL Pulse output pins, group 0 Legend : PPG output mode register : PPG output control register...
Page 507: Input/Output Pins
11.2 Input/Output Pins Table 11.1 summarizes the I/O pins of the PPG. Table 11.1 Pin Configuration Pin Name Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output Group 2 pulse output PO10 Output Output Output Output Group 1 pulse output...
Page 508: Next Data Enable Registers H, L (Nderh, Nderl)
11.3.1 Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1. • NDREH Bit Name Initial Value Description NDER15 Next Data Enable 15 to 8 NDER14 When a bit is set to 1, the value in the...
Page 509: Output Data Registers H, L (Podrh, Podrl)
11.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. • PODRH Bit Name Initial Value Description POD15...
Page 510: Next Data Registers H, L (Ndrh, Ndrl)
11.3.3 Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. • NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Page 511 Bit Name Initial Value Description — — Reserved These bits are always read as 1 and cannot be modified. NDR11 Next Data Register 11 to 8 NDR10 The register contents are transferred to the corresponding PODRH bits by the output trigger NDR9 specified with PCR.
Page 512: Ppg Output Control Register (Pcr)
Bit Name Initial Value Description — — Reserved These bits are always read as 1 and cannot be modified. NDR3 Next Data Register 3 to 0 NDR2 The register contents are transferred to the corresponding PODRL bits by the output trigger NDR1 specified with PCR.
Page 513: Ppg Output Mode Register (Pmr)
Bit Name Initial Value Description G0CMS1 Group 0 Compare Match Select 1 and 0 G0CMS0 Select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3 11.3.5 PPG Output Mode Register (PMR)
Page 514 Bit Name Initial Value Description G3NOV Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel) G2NOV Group 2 Non-Overlap...
Page 515: Operation
11.4 Operation Figure 11.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 516: Output Timing
11.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ...
Page 517: Sample Setup Procedure For Normal Pulse Output
11.4.2 Sample Setup Procedure for Normal Pulse Output Figure 11.4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source with TPU setup...
Page 518: Example Of Normal Pulse Output (Example Of Five-Phase Pulse Output)
11.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 11.5 Normal Pulse Output Example (Five-Phase Pulse Output)
Page 519: Non-Overlapping Pulse Output
11.4.4 Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1.
Page 520: Sample Setup Procedure For Non-Overlapping Pulse Output
Compare match A Compare match B Write to NDR Write to NDR PODR 0 output 0/1 output 0 output 0/1 output Write to NDR Write to NDR here here Do not write Do not write to NDR here to NDR here Figure 11.7 Non-Overlapping Operation and NDR Write Timing 11.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output...
Page 521: Example Of Non-Overlapping Pulse Output (Example Of Four-Phase Complementary Non-Overlapping Output)
[1] Set TIOR to make TGRA and Non-overlapping pulse output TGRB an output compare registers (with output disabled) Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap Set TGR values period in TGRA. TPU setup Set counting operation [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR.
Page 522: Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 Figure 11.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers.
Page 523: Inverted Pulse Output
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU. 11.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the...
Page 524: Pulse Output Triggered By Input Capture
11.4.8 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 525: Section 12 8-Bit Timers (Tmr)
Section 12 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers.
Page 526: Figure 12.1 Block Diagram Of 8-Bit Timer Module
Figure 12.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1). External clock source Internal clock sources TMR_0 TMR_1 φ/8 φ/8 TMCI0 φ/64 φ/64 TMCI1 φ/8192 φ/8192 Clock 1 Clock select Clock 0 TCORA_0 TCORA_1 Compare match A1 Compare match A0 Comparator A_0 Comparator A_1...
Page 527: Input/Output Pins
12.2 Input/Output Pins Table 12.1 summarizes the pins of the 8-bit timer module. Table 12.1 Pin Configuration Channel Name Symbol Function Timer output pin TMO0 Output Outputs at compare match Timer clock input pin TMCI0 Input Inputs external clock for counter Timer reset input pin TMRI0 Input...
Page 528: Time Constant Register A (Tcora)
12.3.2 Time Constant Register A (TCORA) TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1.
Page 529 Bit Name Initial Value Description CMIEB Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled CMIEA Compare Match Interrupt Enable A Selects whether CMFA interrupt requests...
Page 530: Timer Control/Status Register (Tcsr)
Table 12.2 Clock Input to TCNT and Count Condition Channel Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description TMR_0 Clock input disabled Internal clock, counted at falling edge of φ/8 Internal clock, counted at falling edge of φ/64 Internal clock, counted at falling edge of φ/8192 Count at TCNT_1 overflow signal* TMR_1...
Page 531 Bit Name Initial Value Description CMFA R/(W)* Compare Match Flag A [Setting condition] Set when TCNT matches TCORA [Clearing conditions] • Cleared by reading CMFA when CMFA = 1, then writing 0 to CMFA • When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 R/(W)* Timer Overflow Flag...
Page 532 Bit Name Initial Value Description Output Select 1 and 0 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output)
Page 533: Operation
Bit Name Initial Value Description — Reserved This bit is always read as 1 and cannot be modified. Output Select 3 and 2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
Page 534: Operation Timing
TCNT H'FF Counter clear TCORA TCORB H'00 Figure 12.2 Example of Pulse Output 12.5 Operation Timing 12.5.1 TCNT Incrementation Timing Figure 12.3 shows the count timing for internal clock input. Figure 12.4 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges.
Page 535: Timing Of Cmfa And Cmfb Setting When Compare-Match Occurs
φ External clock input pin Clock input to TCNT TCNT N–1 Figure 12.4 Count Timing for External Clock Input 12.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match.
Page 536: Timing Of Compare Match Clear
φ Compare match A signal Timer output pin Figure 12.6 Timing of Timer Output 12.5.4 Timing of Compare Match Clear TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.7 shows the timing of this operation. φ...
Page 537: Timing Of Overflow Flag (Ovf) Setting
φ External reset input pin Clear signal TCNT N–1 H'00 Figure 12.8 Timing of Clearance by External Reset 12.5.6 Timing of Overflow Flag (OVF) Setting The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 12.9 shows the timing of this operation.
Page 538: Compare Match Count Mode
[1] Setting of compare match flags • The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. • The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. [2] Counter clear specification •...
Page 539: A/D Converter Activation
Table 12.3 8-Bit Timer Interrupt Sources Name Interrupt Source Interrupt Flag DTC Activation Priority CMIA0 TCORA_0 compare match CMFA Possible High CMIB0 TCORB_0 compare match CMFB Possible OVI0 TCNT_0 overflow Not possible CMIA1 TCORA_1 compare match CMFA Possible High CMIB1 TCORB_1 compare match CMFB Possible...
Page 540: Usage Notes
12.8 Usage Notes 12.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation.
Page 541: Contention Between Tcor Write And Compare Match
TCNT write cycle by CPU φ Address TCNT address Internal write signal TCNT input clock TCNT Counter write data Figure 12.11 Contention between TCNT Write and Increment 12.8.3 Contention between TCOR Write and Compare Match During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 12.12.
Page 542: Contention Between Compare Matches A And B
TCOR write cycle by CPU φ Address TCOR address Internal write signal TCNT TCOR TCOR write data Compare match signal Inhibited Figure 12.12 Contention between TCOR Write and Compare Match 12.8.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12.4.
Page 543: Switching Of Internal Clocks And Tcnt Operation
12.8.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 12.5 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected.
Page 544: Table 12.5 Switching Of Internal Clock And Tcnt Operation
Table 12.5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from Clock before low to low* switchover Clock after switchover TCNT clock TCNT CKS bit write Switching from Clock before low to high* switchover...
Page 545: Mode Setting With Cascaded Connection
Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high Clock before to high switchover Clock after switchover TCNT clock TCNT CKS bit write Notes: *1 Includes switching from low to stop, and from stop to low. *2 Includes switching from stop to high.
Page 546 Rev. 2.00, 05/03, page 494 of 820...
Page 547: Section 13 Watchdog Timer
Section 13 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
Page 548: Input/Output Pin
Overflow φ/2 φ/64 Interrupt WOVI φ/128 control (interrupt request φ/512 Clock signal) Clock φ/2048 select φ/8192 φ/32768 Reset φ/131072 Internal reset signal* control Internal clock sources RSTCSR TCNT TSCR Module bus interface Legend : Timer control/status register TCSR TCNT : Timer counter : Reset control/status register RSTCSR Note: * An internal reset signal can be generated by the register setting.
Page 549: Register Descriptions
13.3 Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 13.6.1, Notes on Register Access. •...
Page 550 Bit Name Initial Value Description WT/IT Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output.
Page 551: Reset Control/Status Register (Rstcsr)
13.3.3 Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Bit Name Initial Value Description...
Page 552: Operation
13.4 Operation 13.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output.
Page 553: Interval Timer Mode
TCNT count Overflow H'FF Time H'00 WT/ =1 WOVF=1 H'00 written H'00 written WT/ =1 TME=1 to TCNT TME=1 to TCNT internal reset are generated signal 132 states * Internal reset signal * 518 states Legend : Timer mode select bit : Timer enable bit Notes: *1 If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
Page 554: Interrupts
TCNT count Overflow Overflow Overflow Overflow H'FF Time H'00 WOVI WOVI WOVI WOVI WT/ =0 TME=1 Legend WOVI: Interval timer interrupt request generation Figure 13.3 Operation in Interval Timer Mode 13.5 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
Page 555: Contention Between Timer Counter (Tcnt) Write And Increment
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer instruction cannot perform writing to RSTCSR. The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0 to the WOVF bit, satisfy the lower condition shown in figure 13.4.
Page 556: Changing Value Of Cks2 To Cks0
TCNT write cycle Next cycle φ Address Internal write signal TCNT input clock TCNT Counter write data Figure 13.5 Contention between TCNT Write and Increment 13.6.3 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation.
Page 557: System Reset By Wdtovf Signal
System Reset by WDTOVF WDTOVF Signal WDTOVF WDTOVF 13.6.6 If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 13.6.
Page 558 Rev. 2.00, 05/03, page 506 of 820...
Page 559: Section 14 Serial Communication Interface (Sci, Irda)
Section 14 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 560: Figure 14.1 Block Diagram Of Sci
115.152 or 460.606 kbps at 10.667 MHz operation 115.196, 460.784 or 720 kbps at 16 MHz operation 720 kbps at 32 MHz operation Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors detected Smart Card Interface •...
Page 561: Input/Output Pins
14.2 Input/Output Pins Table 14.1 shows the serial pins for each SCI channel. Table 14.1 Pin Configuration Channel Pin Name* Function SCK0 Channel 0 clock input/output RxD0/IrRxD Input Channel 0 receive data input (normal/IrDA) TxD0/IrTxD Output Channel 0 transmit data output (normal/IrDA) SCK1 Channel 1 clock input/output RxD1...
Page 562: Register Descriptions
14.3 Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ. •...
Page 563: Receive Shift Register (Rsr)
• Transmit data register_3 (TDR_3) • Serial mode register_3 (SMR_3) • Serial control register_3 (SCR_3) • Serial status register_3 (SSR_3) • Smart card mode register_3 (SCMR_3) • Bit rate register_3 (BRR_3) • Receive shift register_4 (RSR_4) • Transmit shift register_4 (TSR_4) •...
Page 564: Transmit Shift Register (Tsr)
14.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot be directly accessed by the CPU.
Page 565 Bit Name Initial Value Description STOP Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked regardless of the STOP bit setting. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
Page 566 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of 1 bit), and clock output control mode addition is performed.
Page 567 Bit Name Initial Value Description BCP1 Basic Clock Pulse 1 and 0 BCP0 These bits select the number of basic clock periods in a 1-bit transfer interval on the Smart Card interface. 00: 32 clock (S = 32) 01: 64 clock (S = 64) 10: 372 clock (S = 372) 11: 256 clock (S = 256) For details, refer to section 14.7.4, Receive Data...
Page 568: Serial Control Register (Scr)
14.3.6 Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 14.9, SCI Interrupts. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode.
Page 569 Bit Name Initial Value Description MPIE Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited.
Page 570 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0.
Page 571 Bit Name Initial Value Description TEIE Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. CKE1 Clock Enable 1 and 0 CKE0 Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode.
Page 572: Serial Status Register (Ssr)
14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
Page 573 Bit Name Initial Value Description ORER R/(W) * Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
Page 574 Bit Name Initial Value Description R/(W) * Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set.
Page 575 Smart Card Interface Mode (When SMIF in SCMR is 1) Bit Name Initial Value Description TDRE R/(W) * Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and data writing to TDR is enabled.
Page 576 Bit Name Initial Value Description ORER R/(W) * Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
Page 577 Bit Name Initial Value Description R/(W) * Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set.
Page 578 Bit Name Initial Value Description TEND Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR. [Setting conditions] •...
Page 579: Smart Card Mode Register (Scmr)
14.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit Name Initial Value Description — — Reserved These bits are always read as 1. SDIR Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: LSB-first in transfer 1: MSB-first in transfer The bit setting is valid only when the transfer data...
Page 580: Bit Rate Register (Brr)
14.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 14.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
Page 581: Table 14.3 Brr Settings For Various Bit Rates (Asynchronous Mode)
Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ φ φ φ (MHz) 9.8304 Bit Rate Error Error Error Error (bit/s) 0.03 –0.26 –0.25 0.03 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 0.16 0.00 0.16 0.16 1200 0.16...
Page 582 Operating Frequency φ φ φ φ (MHz) 17.2032 19.6608 Error Error Error Error Bit Rate (bit/s) 0.48 –0.12 0.31 –0.25 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00 0.16 2400 0.00 0.16 0.00 0.16 4800...
Page 583: Table 14.4 Maximum Bit Rate For Each Frequency (Asynchronous Mode)
Table 14.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ φ φ φ (MHz) Maximum Bit Rate (bit/s) 250000 9.8304 307200 312500 375000 12.288 384000 437500 14.7456 460800 500000 17.2032 537600 562500 19.6608 614400 625000 781250 937500 1031250 Rev. 2.00, 05/03, page 531 of 820...
Page 584: Table 14.5 Maximum Bit Rate With External Clock Input (Asynchronous Mode)
Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 2.0000 125000 9.8304 2.4576 153600 2.5000 156250 3.0000 187500 12.288 3.0720 192000 3.5000 218750 14.7456 3.6864 230400 4.0000 250000...
Page 585: Table 14.6 Brr Settings For Various Bit Rates (Clocked Synchronous Mode)
Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ φ φ φ (MHz) Bit Rate (bit/s) — — — — — — — — — — 2.5 k 10 k 25 k 50 k 100 k 250 k 500 k —...
Page 586: Table 14.7 Maximum Bit Rate With External Clock Input (Clocked Synchronous Mode)
Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 4.1667 4166666.7 5.0000 5000000.0...
Page 587: Table 14.8 Examples Of Bit Rate For Various Brr Settings (Smart Card Interface Mode) (When N = 0 And S = 372)
Table 14.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency φ φ φ φ (MHz) 10.00 10.7136 13.00 14.2848 Bit Rate Error Error Error Error (bit/s) 9600 8.99 0.00...
Page 588: Table 14.9 Maximum Bit Rate At Various Frequencies (Smart Card Interface Mode) (When S = 372)
Table 14.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (when S = 372) φ φ φ φ (MHz) Maximum Bit Rate (bit/s) 10.00 13441 10.7136 14400 13.00 17473 14.2848 19200 16.00 21505 18.00 24194 20.00 26882 25.00 33602 30.00 40323...
Page 589: Irda Control Register (Ircr)
14.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Name Initial Value Description IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output. 0: Pins TxD0/IrTxD and RxD0/IrRxD function as TxD0 and RxD0 1: Pins TxD0/IrTxD and RxD0/IrRxD function as IrTxD and IrRxD IrCKS2 IrDA Clock Select 2 to 0...
Page 590: Serial Extension Mode Register (Semr)
14.3.11 Serial Extension Mode Register (SEMR) SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by selecting the average transfer rate. Bit Name Initial Value Description — Undefined — Reserved If these bits are read, an undefined value will be returned.
Page 591 Bit Name Initial Value Description ACS2 Asynchronous clock source selection (valid when ACS1 CKS1 = 1 in asynchronous mode) ACS0 Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS.
Page 592: Operation In Asynchronous Mode
14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
Page 593: Table 14.10 Serial Transfer Formats (Asynchronous Mode)
Table 14.10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
Page 594: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Page 595: Clock
14.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Page 596: Sci Initialization (Asynchronous Mode)
14.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 14.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 597: Data Transmission (Asynchronous Mode)
14.4.5 Data Transmission (Asynchronous Mode) Figure 14.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 598: Figure 14.7 Sample Serial Transmission Flowchart
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is Read TDRE flag in SSR enabled.
Page 599: Serial Data Reception (Asynchronous Mode)
14.4.6 Serial Data Reception (Asynchronous Mode) Figure 14.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
Page 600: Table 14.11 Ssr Status Flags And Receive Data Handling
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.9 shows a sample flowchart for serial data reception. Table 14.11 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER Receive Data Receive Error Type Lost Overrun error Transferred to RDR...
Page 601: Figure 14.9 Sample Serial Reception Data Flowchart (1)
SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
Page 602: Figure 14.9 Sample Serial Reception Data Flowchart (2)
Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14.9 Sample Serial Reception Data Flowchart (2) Rev.
Page 603: Multiprocessor Communication Function
14.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 604: Multiprocessor Serial Data Transmission
Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB= 1) (MPB= 0) ID transmission cycle = Data transmission cycle = receiving station data transmission to...
Page 605: Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart
SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled. SCI status check and transmit TDRE = 1? data write:...
Page 606: Multiprocessor Serial Data Reception
14.5.2 Multiprocessor Serial Data Reception Figure 14.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR.
Page 607: Figure 14.12 Example Of Sci Operation In Reception (Example With 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Start Data (ID1) Stop Start Data (Data1) Stop Idle state (mark state) MPIE RDRF value MPIE = 0 RXI interrupt RDR data read If not this station’s ID, RXI interrupt request is request and RDRF flag MPIE bit is set to 1 not generated, and RDR (multiprocessor cleared to 0 in...
Page 608: Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)
SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. ID reception cycle: Set MPIE bit in SCR to 1 Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR SCI status check, ID reception and comparison: FER ∨...
Page 609: Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)
Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 610: Operation In Clocked Synchronous Mode
14.6 Operation in Clocked Synchronous Mode Figure 14.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Page 611: Sci Initialization (Clocked Synchronous Mode)
14.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 14.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change.
Page 612: Serial Data Transmission (Clocked Synchronous Mode)
14.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 14.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR.
Page 613: Figure 14.16 Sample Sci Transmission Operation In Clocked Synchronous Mode
Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag request generated request generated cleared to 0 in TXI interrupt handling routine 1 frame...
Page 614: Figure 14.17 Sample Serial Transmission Flowchart
[1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start of transmission pin. [2] SCI status check and transmit data Read TDRE flag in SSR write: Read SSR and check that the TDRE flag is set to 1, then write transmit data TDRE = 1? to TDR and clear the TDRE flag to 0.
Page 615: Serial Data Reception (Clocked Synchronous Mode)
14.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR.
Page 616: Figure 14.19 Sample Serial Reception Flowchart
SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. [2] [3] Receive error handling: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to ORER = 1?
Page 617: Simultaneous Serial Data Transmission And Reception (Clocked Synchronous Mode)
14.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Page 618: Figure 14.20 Sample Flowchart Of Simultaneous Serial Transmit And Receive Operations
SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start of transmission/reception receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR SCI status check and transmit data write: Read SSR and check that the...
Page 619: Operation In Smart Card Interface Mode
14.7 Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting.
Page 620: Figure 14.22 Normal Smart Card Interface Data Format
When there is no parity error Transmitting station output When a parity error occurs Transmitting station output Receiving station Legend output : Start bit : Data bits D0 to D7 : Parity bit : Error signal Figure 14.22 Normal Smart Card Interface Data Format Data transfer with the types of IC cards (direct convention and inverse convention) are performed as described in the following.
Page 621: Block Transfer Mode
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1 to invert the parity bit for both transmission and reception. 14.7.3 Block Transfer Mode Operation in block transfer mode is the same as that in normal Smart Card interface, except for the following points.
Page 622: Initialization
372 clocks 186 clocks 371 0 Internal basic clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 14.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate) 14.7.5 Initialization Before transmitting and receiving data, initialize the SCI as described below.
Page 623: Data Transmission (Except For Block Transfer Mode)
14.7.6 Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 14.26 illustrates the retransfer operation when the SCI is in transmit mode.
Page 624: Figure 14.26 Retransfer Operation In Sci Transmit Mode
Transfer nth transfer frame Retransferred frame frame n+1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR Transfer to TSR from TDR Transfer to TSR from TDR from TDR TEND...
Page 625: Figure 14.28 Example Of Transmission Processing Flow
Start Initialization Start transmission ERS = 0? Error processing TEND = 1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted ? ERS = 0? Error processing TEND = 1? Clear TE bit to 0 Figure 14.28 Example of Transmission Processing Flow Rev.
Page 626: Serial Data Reception (Except For Block Transfer Mode)
14.7.7 Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the SCI is in receive mode. 1.
Page 627: Clock Output Control
Start Initialization Start reception ORER = 0 and PER = 0 Error processing RDRF = 1? Read RDR and clear RDRF flag in SSR to 0 All data received? Clear RE bit to 0 Figure 14.30 Example of Reception Processing Flow 14.7.8 Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and...
Page 628: Figure 14.32 Clock Halt And Restart Procedure
When turning on the power or switching between Smart Card interface mode and software standby mode, the following procedures should be followed in order to maintain the clock duty. Powering On: To secure the clock duty from power-on, the following switching procedure should be followed.
Page 629: Irda Operation
14.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system.
Page 630: Figure 14.34 Irda Transmit/Receive Operations
When the serial data is 1, no pulse is output. UART frame Data Stop Start Transmit Receive IR frame Data Stop Start Pulse width 1.6 µs to 3/16 bit cycle cycle Figure 14.34 IrDA Transmit/Receive Operations Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI.
Page 631: Table 14.12 Settings Of Bits Ircks2 To Ircks0
Table 14.12 Settings of Bits IrCKS2 to IrCKS0 Bit Rate (bps) (Above) /Bit Period × × × × 3/16 (µs) (Below) Operating 2400 9600 19200 38400 57600 115200 Frequency φ φ φ φ (MHz) 78.13 19.53 9.77 4.88 3.26 1.63 9.8304 12.288 14.7456...
Page 632: Sci Interrupts
14.9 SCI Interrupts 14.9.1 Interrupts in Normal Serial Communication Interface Mode Table 14.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
Page 633: Interrupts In Smart Card Interface Mode
Table 14.13 SCI Interrupt Sources DMAC* Channel Name Interrupt Source Interrupt Flag Activation Activation Priority ERI0 Receive Error ORER, FER, PER Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empty TDRE Possible Possible TEI0 Transmission End TEND...
Page 634: Table 14.14 Interrupt Sources
Table 14.14 Interrupt Sources DMAC* Channel Name Interrupt Source Interrupt Flag Activation Activation Priority ERI0 Receive Error, detection ORER, PER, ERS Not possible Not possible High RXI0 Receive Data Full RDRF Possible Possible TXI0 Transmit Data Empty TEND Possible Possible ERI1 Receive Error, detection ORER, PER, ERS...
Page 635: Usage Notes
out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC or DMAC*. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DTC or DMAC* is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.
Page 636: 14.10.5 Relation Between Writes To Tdr And The Tdre Flag
14.10.5 Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag.
Page 637 When transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting TE to 1 again, and performing the following sequence: SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization.
Page 638: Figure 14.36 Sample Flowchart For Mode Transition During Transmission
Figure 14.39 shows a sample flowchart for mode transition during reception. <Transmission> [1] Data being transmitted is interrupted. All data transmitted? After exiting software standby mode, normal CPU transmission is possible by setting TE to 1, reading SSR, writing TDR, and clearing TDRE to 0, Read TEND flag in SSR but note that if the DTC has been activated, the remaining data in...
Page 639: Figure 14.37 Port Pin States During Mode Transition (Internal Clock, Asynchronous Transmission)
Transition Exit from End of to software software Start of transmission transmission standby standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 14.37 Port Pin States during Mode Transition (Internal Clock, Asynchronous Transmission)
Page 640: Figure 14.39 Sample Flowchart For Mode Transition During Reception
<Reception> Read RDRF flag in SSR [1] Receive data being received RDRF = 1 becomes invalid. Read receive data in RDR RE = 0 Transition to software [2] Includes module stop mode. standby mode Exit from software standby mode Change operating mode? Initialization RE = 1...
Page 641: Section 15 I C Bus Interface2 (Iic2) (Option)
For the masked ROM version, ‘W’ is added to the model name of the product that uses optional functions. For example: HD6432365WTE For the F-ZTAT version, product model names do not depend on optional functions. When using optional functions, contact the Renesas Technology sales office. This LSI has a two-channel I C bus interface, The I...
Page 642: Figure 15.1 Block Diagram Of I
Transfer clock generation circuit Transmission/ ICCRA reception control circuit Output ICCRB control ICMR Noise canceler ICDRT Output ICDRS control Address Noise canceler comparator ICDRR Bus state decision circuit Arbitration ICSR decision circuit ICEIR Interrupt Interrupt request Legend: generator ICCRA C bus control register A ICCRB C bus control register B ICMR...
Page 643: Input/Output Pins
SCL in SCL out SDA in SDA out (Master) SCL in SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I C bus interface.
Page 644: Register Descriptions
15.3 Register Descriptions The I C bus interface has the following registers. • I C bus control register A_0 (ICCRA_0) • I C bus control register B_0 (ICCRB_0) • I C bus mode register_0 (ICMR_0) • I C bus interrupt enable register_0 (ICIER_0) •...
Page 645: C Bus Control Register A (Iccra)
15.3.1 C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description...
Page 646: C Bus Control Register B (Iccrb)
Table 15.2 Transfer Rate Bit3 Bit2 Bit1 Bit0 Clock Transfer Rate φ φ φ φ =8MHz φ φ φ φ =10MHz φ φ φ φ =20MHz φ φ φ φ =25MHz φ φ φ φ =33MHz CKS3 CKS2 CKS1 CKS0 φ/28 286kHz 357kHz...
Page 647 Bit Bit Name Initial Value R/W Description Start Condition/Stop Condition Prohibit The SCP bit controls the issue of start/stop conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
Page 648: C Bus Mode Register (Icmr)
15.3.3 C Bus Mode Register (ICMR) ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred first, performs master mode wait control, and selects the transfer bit count. Bit Bit Name Initial Value R/W Description ...
Page 649: C Bus Interrupt Enable Register (Icier)
Bit Bit Name Initial Value R/W Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit.
Page 650 Bit Bit Name Initial Value R/W Description Receive interrupt enable This bit enables or disables the receive data full interrupt request (RXI) when a received data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. RXI can be canceled by clearing the RDRF or RIE bit to 0.
Page 651: C Bus Status Register (Icsr)
15.3.5 C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W Description TDRE Transmit Data Register Empty [Setting condition] When data is transferred from ICDRT to ICDRS and ICDRT becomes empty [Clearing conditions] •...
Page 652 Bit Bit Name Initial Value R/W Description STOP Stop condition detection flag [Setting condition] When a stop condition is detected after frame transfer [Clearing condition] When 0 is written in STOP after reading STOP = 1 Arbitration Lost Flag This flag indicates that arbitration was lost in master mode. When two or more master devices attempt to seize the bus at nearly the same time, if the I C bus interface detects data...
Page 653: Slave Address Register (Sar)
15.3.6 Slave Address Register (SAR) SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
Page 654: Operation
15.4 Operation 15.4.1 C Bus Format Figure 15.3 shows the I C bus formats. Figure 15.4 shows the I C bus timing. The first frame following a start condition always consists of 8 bits. (a) I C bus format DATA n: transfer bit count (n = 1 to 8) m: transfer frame count...
Page 655: Master Transmit Operation
Legend Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. Acknowledge.
Page 656: Figure 15.5 Master Transmit Mode Operation Timing 1
(master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 (master output) Slave address (slave output) TDRE TEND ICDRT Address + R/ Data 1 Data 2 ICDRS Address + R/ Data 1 User [4] Write data to ICDRT (second byte).
Page 657: Master Receive Operation
15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown below.
Page 658: Figure 15.7 Master Receive Mode Operation Timing 1
Master transmit mode Master receive mode (master output) (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (slave output) TDRE TEND RDRF ICDRS Data 1 ICDRR Data 1 User [3] Read ICDRR [2] Read ICDRR (dummy read) processing...
Page 659: Slave Transmit Operation
15.4.4 Slave Transmit Operation In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. For slave transmit mode operation timing, refer to figures 15.9 and 15.10. The transmission procedure and operations in slave transmit mode are described below.
Page 660: Figure 15.9 Slave Transmit Mode Operation Timing 1
Slave receive mode Slave transmit mode (master output) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 (slave output) TDRE TEND ICDRT Data 1 Data 2 Data 3 ICDRS Data 1 Data 2...
Page 661: Slave Receive Operation
Slave receive mode Slave transmit mode (master output) (master output) (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (slave output) TDRE TEND ICDRT ICDRS Data n ICDRR User [5] Clear TDRE [4] Read ICDRR (dummy read) processing [3] Clear TEND...
Page 662: Figure 15.11 Slave Receive Mode Operation Timing 1
before clearing RDRF, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR. (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7...
Page 663: Noise Canceler
15.4.6 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
Page 664: Figure 15.14 Sample Flowchart For Master Transmit Mode
Start Initialize Read BBSY in ICCRB Test the status of the SCL and SDA lines. BBSY=0 ? Select master transmit mode. Start condition issuance. Set MST = 1 and TRS = 1 in ICCRA. Select transmit data for the first byte (slave address + R/W), Write BBSY = 1 and clear TDRE to 0.
Page 665: Figure 15.15 Sample Flowchart For Master Receive Mode
Mater receive mode Clear TEND, select master receive mode, and then clear TDRE. Clear TEND in ICSR Set acknowledge to the transmitting device. Set TRS = 0 (ICCRA) Dummy read ICDDR Clear TDRE of ICSR Wait for 1 byte to be received. Set ACKBT = 0 (ICIER) Check if (last receive - 1) Dummy read ICDRR...
Page 666: Figure 15.16 Sample Flowchart For Slave Transmit Mode
[1] Clear the flag AAS. Slave transmit mode Clear AAS in ICSR [2] Set transmit data for ICDRT (except for the last data), and clear TDRE to 0. Write transmit data [3] Wait for ICDRT empty. in ICDRT [4] Set the last byte of the transmit data, and clear TDRE to 0. Read TDRE in ICSR [5] Wait the transmission end of the last byte.
Page 667: Figure 15.17 Sample Flowchart For Slave Receive Mode
Slave receive mode [1] Clear the flag AAS. Clear AAS in ICSR [2] Set the acknowledge for the transmit device. Set ACKBT=0 in ICIER [3] Dummy read ICDRR. Dummy read ICDRR [4] Wait the reception end of 1 byte. [5] Judge the (last receive - 1). Read RDRF in ICSR [6] Read the received data, and clear RDRF to 0.
Page 668: Interrupt Request
15.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost. Table 15.3 shows the contents of each interrupt request. Table 15.3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition Transmit Data Empty...
Page 669: Table 15.4 Time For Monitoring Scl
Table 15.4 Time for monitoring SCL CKS3 CKS2 Time for monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc Rev. 2.00, 05/03, page 617 of 820...
Page 670 Rev. 2.00, 05/03, page 618 of 820...
Page 671: Section 16 A/D Converter
Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to ten analog input channels to be selected. The block diagram of A/D converter is shown in figure 16.1. 16.1 Features • 10-bit resolution •...
Page 672: Figure 16.1 Block Diagram Of A/D Converter
Module data bus Internal data bus AVCC Vref 10-bit A/D AVSS – Comparator Control circuit Sample-and- hold circuit AN12 ADI interrupt signal AN13 Conversion start trigger from 8-bit timer or TPU Legend ADDRD: A/D data register D ADCR: A/D control register ADDRE: A/D data register E ADCSR: A/D control/status register ADDRF: A/D data register F...
Page 673: Input/Output Pins
16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The AV and AV pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The sixteen analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and channel set 1 (AN12 and AN13).
Page 674: Register Descriptions
16.3 Register Descriptions The A/D converter has the following registers. • A/D data register A (ADDRA) • A/D data register B (ADDRB) • A/D data register C (ADDRC) • A/D data register D (ADDRD) • A/D data register E (ADDRE) •...
Page 675: A/D Control/Status Register (Adcsr)
16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Name Initial Value Description R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] • When A/D conversion ends in single mode • When A/D conversion ends on all specified channels in scan mode [Clearing conditions]...
Page 676 Bit Name Initial Value Description Channel select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. Set the input channel when conversion is stopped (ADST = 0). When SCANE = 0 and SCANS = X 0000: AN0 10xx: Cannot be set 0001: AN1...
Page 677: A/D Control Register (Adcr)
16.3.3 A/D Control Register (ADCR) ADCR enables A/D conversion start by an external trigger input. It also sets the A/D converter operating mode and the A/D conversion time. Bit Name Initial Value Description TRGS1 Timer Trigger Select 1 and 0 TRGS0 These bits select enabling or disabling of the start of A/D conversion by a trigger signal.
Page 678: Operation
16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D conversion.
Page 679: Input Sampling And A/D Conversion Time
4. The ADST bit is not cleared automatically, and steps [2] and [3] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group.
Page 680: Table 16.3 A/D Conversion Time (Single Mode)
Table 16.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion —...
Page 681: External Trigger Input Timing
16.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion.
Page 682: A/D Conversion Precision Definitions
16.6 A/D Conversion Precision Definitions This LSI’s A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). •...
Page 683: Figure 16.4 A/D Conversion Precision Definitions
Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 16.4 A/D Conversion Precision Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 16.5 A/D Conversion Precision Definitions Rev.
Page 684: Usage Notes
16.7 Usage Notes 16.7.1 Module Stop Mode Setting Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module stop mode.
Page 685: Influences On Absolute Precision
16.7.3 Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas.
Page 686: Notes On Noise Countermeasures
16.7.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7, AN12, AN13) should be connected between AVcc and AVss as shown in figure 16.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN15 must be connected to AVss.
Page 687: Table 16.6 Analog Pin Specifications
Table 16.6 Analog Pin Specifications Item Unit Analog input capacitance — Permissible signal source impedance — kΩ Rev. 2.00, 05/03, page 635 of 820...
Page 688 Rev. 2.00, 05/03, page 636 of 820...
Page 689: Section 17 D/A Converter
Section 17 D/A Converter 17.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode •...
Page 690: Figure 17.1 Block Diagram Of D/A Converter
Module data bus Internal data bus Vref 8-bit Control circuit Legend DADR2: D/A data register 2 DADR3: D/A data register 3 DADR4: D/A data register 4 DACR23: D/A control register 23 Figure 17.1 Block Diagram of D/A Converter Rev. 2.00, 05/03, page 638 of 820...
Page 691: Input/Output Pins
17.2 Input/Output Pins Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol Function Analog power pin Input Analog power Analog ground pin Input Analog ground Reference voltage pin Vref Input Reference voltage of D/A converter Analog output pin 2 Output...
Page 692: Table 17.2 Control Of D/A Conversion
Bit Name Initial Value Description DAOE3 D/A Output Enable 3 Controls D/A conversion and analog output. 0: Analog output (DA3) is disabled 1: Channel 3 D/A conversion is enabled; analog output (DA3) is enabled DAOE2 D/A Output Enable 2 Controls D/A conversion and analog output. 0: Analog output (DA2) is disabled 1: Channel 2 D/A conversion is enabled;...
Page 693: Operation
17.4 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When DAOE bit in DACR23 is set to 1, D/A conversion is enabled and the conversion result is output. The operation example concerns D/A conversion on channel 2. Figure 17.2 shows the timing of this operation.
Page 694: Usage Notes
DADR2 DACR23 DADR2 DACR23 write cycle write cycle write cycle write cycle Address DADR2 Conversion data 1 Conversion data 2 DAOE0 Conversion Conversion result 2 High-impedance state result 1 DCONV DCONV Legend : D/A conversion time DCONV Figure 17.2 Example of D/A Converter Operation 17.5 Usage Notes 17.5.1...
Page 695: Section 18 Ram
Section 18 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR).
Page 696 Rev. 2.00, 05/03, page 644 of 820...
Page 697: Section 19 Flash Memory (F-Ztat Version)
Section 19 Flash Memory (F-ZTAT Version) The features of the flash memory included in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 19.1. 19.1 Features • Size Product Classification ROM Size ROM Address H8S/2368 Group HD64F2367...
Page 698: Mode Transitions
Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating Bus interface/controller Mode pins mode EBR1 EBR2 RAMER SYSCR Flash memory Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2 RAMER:...
Page 699: Figure 19.2 Flash Memory State Transitions
Reset state User mode (on-chip ROM enabled) SWE = 0 MD0 = 0, MD1 = 0, SWE = 1 MD2 = 0, P50 = 0, Programmer P51 = 0, P52 = 1 mode User program mode Boot mode On-board programming mode Note: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory.
Page 700: Figure 19.3 Boot Mode
1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the chip (originally incorporated in the chip) is programming control program and new started and the programming control program in application program beforehand in the host.
Page 701: Figure 19.4 User Program Mode
1. Initial state 2. Programming/erase control program transfer (1) the program that will transfer the When user program mode is entered, user programming/ erase control program to on-chip software confirms this fact, executes the transfer RAM should be written into the flash memory by program in the flash memory, and transfers the the user beforehand.
Page 702: Block Configuration
19.3 Block Configuration Figure 19.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 384- kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks).
Page 703: Figure 19.5 384-Kbyte Flash Memory Block Configuration (Modes 3, 4, And 7)
Programming unit: 128 bytes H'000000 H'000001 H'000002 H'00007F Erase unit 4 kbytes H'000FFF H'001000 H'001001 H'001002 Programming unit: 128 bytes H'00107F Erase unit 4 kbytes H'001FFF Programming unit: 128 bytes H'00207F H'002000 H'002001 H'002002 Erase unit 4 kbytes H'002FFF H'003000 H'003001 H'003002 Programming unit: 128 bytes...
Page 704: Input/Output Pins
19.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 19.2. Table 19.2 Pin Configuration Pin Name Function Input Reset Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input Sets this LSI’s operating mode Input Sets operating mode in programmer mode Input...
Page 705 Bit Name Initial Value Description This bit is reserved. This bit is always read as 0 in — modes 1 and 2. This bit is always read as 1 in modes 3 to 7. Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled.
Page 706: Flash Memory Control Register 2 (Flmcr2)
Bit Name Initial Value Description Program When this bit is set to 1 while SWE = 1, and PSU = 1, the flash memory transits to program mode. When it is cleared to 0, program mode is cancelled. 19.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing.
Page 707: Erase Block Register 2 (Ebr2)
Bit Name Initial Value Description When this bit is set to 1, 4 kbytes of EB7 are to be erased. When this bit is set to 1, 4 kbytes of EB6 are to be erased. When this bit is set to 1, 4 kbytes of EB5 are to be erased.
Page 708: Ram Emulation Register (Ramer)
Table 19.3 Erase Blocks Address Block (Size) Modes 3, 4, and 7 EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes)
Page 709: On-Board Programming Modes
Bit Name Initial Value Description 7 to — Reserved These bits always read 0. RAMS RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory block are in the program/erase- protect state.
Page 710: Boot Mode
19.6.1 Boot Mode When this LSI enters boot mode, the embedded boot program is started. The boot program transfers the programming control program from the externally connected host to the on-chip RAM via the SCI_1. When the flash memory is all erased, the programming control program is executed.
Page 711 2. Boot mode can be cleared by a reset. Release the reset by setting the MD pins, after waiting at least 20 states since driving the reset pin low. Boot mode is also cleared when the WDT overflow reset occurs. 3.
Page 712: Table 19.5 Boot Mode Operation
Table 19.5 Boot Mode Operation Host Operation Communication Contents LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Boot program initiation H'00, H'00 . . . H'00 Continuously transmits data H'00 • Measures low-level period of receive data H'00. at specified bit rate.
Page 713: User Program Mode
Table 19.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 8 to 25 MHz 9,600 bps 8 to 25 MHz 19.6.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase program.
Page 714: Flash Memory Emulation In Ram
19.7 Flash Memory Emulation in RAM Note: This function is not supported by the H8S/2367 or H8S/2366. Making a setting in the RAM emulation register (RAMER) enables RAM to be overlapped onto the part of flash memory area so that data to be programmed to flash memory can be emulated in the on-chip RAM in real time.
Page 715: Figure 19.8 Example Of Ram Overlap Operation
2. The flash memory area to overlap is selected by RAMER from a 4-kbyte area among one of the EB0 to EB7 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. Notes: 1.
Page 716: Flash Memory Programming/Erasing
19.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory operates in one of the following four modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Page 717: Figure 19.9 Program/Program-Verify Flowchart
Write pulse application subroutine Start of programming Perform programming in the erased state. Write pulse application Start Do not perform additional programming Enable WDT Set SWE bit in FLMCR1 on previously programmed addresses. Wait (x) µs Set PSU bit in FLMCR1 Wait (y) µs Store 128-byte program data in program data area and reprogram data area...
Page 718: Erase/Erase-Verify
19.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block registers (EBR1 and EBR2).
Page 719: Figure 19.10 Erase/Erase-Verify Flowchart
Start Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) µs n ← n + 1 Clear E bit in FLMCR1 Halt erase Wait (α) µs...
Page 720: Program/Erase Protection
19.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or standby mode.
Page 721: Programmer Mode
In programmer mode, a PROM programmer can perform programming/erasing via a socket adapter, just like for a discrete flash memory. Use a PROM programmer which supports the Renesas 512-kbyte flash memory on-chip MCU device type (FZTAT512V3A). A 12-MHz input clock is needed.
Page 722 Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter. 2. Reset the flash memory before turning on/off the power. When applying or disconnecting Vcc power, fix the RES pin low and place the flash memory in the hardware protection state.
Page 723: Figure 19.11 Power-On/Off Timing
Programming/ erasing possible Wait time: 100 µs Wait time: x φ Min 0 µs OSC1 MD2 to MD0 SWE set SWE cleared SWE bit (1) Boot Mode Programming/ erasing Wait time: 100 µs possible Wait time: x φ Min 0 µs OSC1 MD2 to MD0 SWE set...
Page 724: Figure 19.12 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User Program Mode)
Wait time: x Wait time: x Wait time: x Wait time: x Programming/erasing Programming/erasing Programming/erasing Programming/erasing possible possible possible possible φ OSC1 MD2 to MD0 RESW cleared SWE bit User User User User User mode User Mode Boot Mode mode program mode program...
Page 725: Section 20 Mask Rom
Section 20 Mask ROM The LSI of this series has 256 kbytes of mask ROM. The on-chip ROM is connected to the CPU, data transfer controller (DTC), and DMA controller (DMAC)* with a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit units. The data in the on-chip ROM can always be accessed in one state.
Page 726 Rev. 2.00, 05/03, page 674 of 820...
Page 727: Section 21 Clock Pulse Generator
Section 21 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and internal clocks. The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider. Figure 21.1 shows a block diagram of the clock pulse generator. PLLCR SCKCR STC0, STC1...
Page 728 Bit Name Initial Value Description φ Clock Output Disable PSTOP Controls φ output. Normal Operation 0: φ output 1: Fixed high Sleep Mode 0: φ output 1: Fixed high Software Standby Mode 0: Fixed high 1: Fixed high Hardware Standby Mode 0: High impedance 1: High impedance All module clock stop mode...
Page 729: Pll Control Register (Pllcr)
Bit Name Initial Value Description SCK2 System Clock Select 2 to 0 SCK1 Select the division ratio. SCK0 000: 1/1 001: 1/2 010: 1/4 011: Setting prohibited 100: Setting prohibited 101: Setting prohibited 11X: Setting prohibited X: Don’t care 21.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the PLL circuit.
Page 730: Oscillator
21.2 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 21.2.1 Connecting a Crystal Oscillator A crystal oscillator can be connected as shown in the example in figure 21.2. Select the damping resistance R according to table 21.1.
Page 731: External Clock Input
Table 21.2 Crystal Oscillator Characteristics Frequency (MHz) max (Ω) max (pF) 21.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 21.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode.
Page 732: Pll Circuit
Table 21.3 External Clock Input Conditions = 3.0 V to 3.6 V Test Item Symbol Unit Conditions External clock input — Figure 21.5 low pulse width External clock input — high pulse width External clock rise time — External clock fall time —...
Page 733: Frequency Divider
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby mode. 4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid. 5. Software standby mode is cleared, and a transition time is secured in accordance with the setting in STS3 to STS0.
Page 734: Notes On Board Design
21.5.3 Notes on Board Design When using the crystal oscillator, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 21.6. Avoid Signal A Signal B This LSI...
Page 735: Section 22 Power-Down Modes
Section 22 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
Page 736: Table 22.1 Operating Modes And Internal States Of The Lsi
Table 22.1 Operating Modes and Internal States of the LSI High Clock All Module Software Hardware Operating State Speed Division Sleep Module Clock Stop Standby Standby Mode Mode Mode Stop Mode Mode Mode Mode Clock pulse generator Functions Functions Functions Functions Functions Halted...
Page 737: Figure 22.1 Mode Transitions
*1 The active or halted state can be selected by means of the MSTP0 bit in MSTPCR. *2 Not supported by the H8S/2366. *3 TDR, SSR, and RDR are halted (reset) and other registers are halted (retained). *4 BC2 to BC0 are halted (reset) and other registers are halted (retained). pin = low Hardware Reset state...
Page 738: Register Descriptions
22.1 Register Descriptions The registers relating to the power-down mode are shown below. For details on the system clock control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). • System clock control register (SCKCR) • Standby control register (SBYCR) •...
Page 739 Bit Name Initial Value Description — — Reserved — — These bits are always read as 0. The initial value should not be changed. STS3 Standby Timer Select 3 to 0 STS2 These bits select the time the MCU waits for the STS1 clock to stabilize when software standby mode is STS0...
Page 740: Module Stop Control Registers H And L (Mstpcrh, Mstpcrl)
22.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop mode control. Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0 clears the module stop mode. • MSTPCRH Bit Name Initial Value...
Page 741: Extension Module Stop Control Registers H And L (Exmstpcrh, Exmstpcrl)
22.1.3 Extension Module Stop Control Registers H and L (EXMSTPCRH, EXMSTPCRL) EXMSTPCR performs all-module-clocks-stop mode control with MSTPCR. When entering all-module-clocks-stop mode, set EXMSTPCR to H’FFFF. Otherwise, set EXMSTPCR to H’FFFD. • EXMSTPCRH Bit Name Initial Value Module — Reserved Read/write is enabled.
Page 742: Operation
22.2 Operation 22.2.1 Clock Division Mode When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and on-chip peripheral functions all operate on the operating clock (1/2 or 1/4) specified by bits SCK2 to SCK0.
Page 743: Software Standby Mode
22.2.3 Software Standby Mode Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O ports, are retained.
Page 744: Table 22.2 Oscillation Stabilization Time Settings
Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 22.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0.
Page 745: Hardware Standby Mode
In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
Page 746: Module Stop Mode
Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (for details on the oscillation stabilization time, refer to table 22.2).
Page 747: All-Module-Clocks-Stop Mode
After reset clearance, all modules other than the DMAC*, and DTC are in module stop mode. The module registers which are set in module stop mode cannot be read or written to. Note: * Not supported by the H8S/2366. 22.2.6 All-Module-Clocks-Stop Mode When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip peripheral functions controlled by MSTPCR or EXMSTPCR (MSTPCR = H'FFFF, EXMSTPCR...
Page 748: Usage Notes
22.4 Usage Notes 22.4.1 I/O Port Status In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 22.4.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period.
Page 749: Notes On Clock Division Mode
22.4.6 Notes on Clock Division Mode The following points should be noted in clock division mode. • Select the clock division ratio specified by the SCK2 to SCK0 bits so that the frequency of φ is within the operation guaranteed range of clock cycle time (t ) shown in the Electrical Characteristics.
Page 750 Rev. 2.00, 05/03, page 698 of 820...
Page 751: Section 23 List Of Registers
Section 23 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) •...
Page 752: Register Addresses (Address Order)
23.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock. Abbrevia- Data Access Register Name tion Bit No.
Page 753 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Interrupt priority register F IPRF H'FE0A Interrupt priority register G IPRG H'FE0C Interrupt priority register H IPRH H'FE0E Interrupt priority register I IPRI H'FE10 Interrupt priority register J IPRJ H'FE12 Interrupt priority register K...
Page 754 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Port 3 open drain control register P3ODR H'FE3C PORT Port A open drain control register PAODR H'FE3D PORT Serial mode register_3 SMR_3 H'FE40 SCI_3 Bit rate register_3 BRR_3 H'FE41 SCI_3 Serial control register_3...
Page 755 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Timer general register A_4 TGRA_4 H'FE98 TPU_4 Timer general register B_4 TGRB_4 H'FE9A TPU_4 Timer control register_5 TCR_5 H'FEA0 TPU_5 Timer mode register_5 TMDR_5 H'FEA1 TPU_5 Timer I/O control register_5 TIOR_5 H'FEA2 TPU_5...
Page 756 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Memory address register_0AH MAR_0AH H'FEE0 DMAC* Memory address register_0AL MAR_0AL H'FEE2 DMAC* I/O address register_0A IOAR_0A H'FEE4 DMAC* Transfer count register_0A ETCR_0A H'FEE6 DMAC* Memory address register_0BH MAR_0BH H'FEE8 DMAC* Memory address register_0BL...
Page 757 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Interrupt control register INTCR H'FF31 IRQ enable register H'FF32 IRQ status register H'FF34 Standby control register SBYCR H'FF3A SYSTEM System clock control register SCKCR H'FF3B SYSTEM System control register SYSCR H'FF3D SYSTEM...
Page 758 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Port A register PORTA H'FF59 PORT Port B register PORTB H'FF5A PORT Port C register PORTC H'FF5B PORT Port D register PORTD H'FF5C PORT Port E register PORTE H'FF5D PORT Port F register...
Page 759 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Serial mode register_2 SMR_2 H'FF88 SCI_2 Bit rate register_2 BRR_2 H'FF89 SCI_2 Serial control register_2 SCR_2 H'FF8A SCI_2 Transmit data register_2 TDR_2 H'FF8B SCI_2 Serial status register_2 SSR_2 H'FF8C SCI_2 Receive data register_2...
Page 760 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Timer control/status register TCSR_0 H'FFBC* (Write) H'FFBC (Read) Timer counter TCNT H'FFBC* (Write) H'FFBD (Read) Reset control/status register RSTCSR H'FFBE* (Write) H'FFBF (Read) Timer start register TSTR H'FFC0 Timer synchronous register TSYR H'FFC1...
Page 761 Abbrevia- Data Access Register Name tion Bit No. Address Module Width States Timer control register_1 TCR_1 H'FFE0 TPU_1 Timer mode register_1 TMDR_1 H'FFE1 TPU_1 Timer I/O control register_1 TIOR_1 H'FFE2 TPU_1 Timer interrupt enable register_1 TIER_1 H'FFE4 TPU_1 Timer status register_1 TSR_1 H'FFE5 TPU_1...
Page 762: Register Bits
23.2 Register Bits Register bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16- or 32-bit registers are shown as 2 or 4 lines. Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 763 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module IPRA — IPRA14 IPRA13 IPRA12 — IPRA10 IPRA9 IPRA8 — IPRA6 IPRA5 IPRA4 — IPRA2 IPRA1 IPRA0 IPRB — IPRB14 IPRB13 IPRB12 —...
Page 764 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module P3DDR — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR PORT P5DDR — — — — P53DDR P52DDR P51DDR P50DDR P8DDR — —...
Page 765 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SMR_4* STOP CKS1 CKS0 SCI_4 Smart card SMR_4* BCP1 BCP0 CKS1 CKS0 interface 4 BRR_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_4...
Page 766 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCNT_4 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_4 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRA_4 Bit15 Bit14 Bit13 Bit12 Bit11...
Page 767 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module BRLE BREQ0E — IDLC ICIS1 ICIS0 WDBE WAITE — — — — — ICIS2 — — RAMER — — — — RAMS RAM2 RAM1...
Page 768 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ETCR_1A Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DMAC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MAR_1BH — — —...
Page 769 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 INTCR — — INTM1 INTM0 NMIEG — — — — — — —...
Page 770 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORTA PORT PORTB PORTC PORTD PORTE PORTF PORTG — P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR P2DR P27DR P26DR P25DR P24DR P23DR...
Page 771 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SMR_1* STOP CKS1 CKS0 SCI_1, SMR_1* BCP1 BCP0 OKS1 OKS0 Smart card interface_1 BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SCR_1 MPIE...
Page 772 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ADCSR ADIE ADST — ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 — — DADR2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DADR3 Bit7...
Page 773 Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TGRB_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TGRC_0 Bit15 Bit14 Bit13 Bit12 Bit11...
Page 774 Notes: *1 Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. *2 For short address mode *3 For full address mode *4 For normal mode *5 For smart card interface mode *6 If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Page 775: Register States In Each Operating Mode
23.3 Register States in Each Operating Mode Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module Initialized — — — — — — Initialized Initialized — — — — — —...
Page 776 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module IPRE Initialized — — — — — — Initialized IPRF Initialized — — — — — — Initialized IPRG Initialized — —...
Page 777 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module PEPCR Initialized — — — — — — Initialized PORT P3ODR Initialized — — — — — — Initialized PAODR Initialized —...
Page 778 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TCNT_4 Initialized — — — — — — Initialized TPU_4 TGRA_4 Initialized — — — — — — Initialized TGRB_4 Initialized —...
Page 779 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module ETCR_0A Initialized — — — — — — Initialized DMAC* MAR_0BH Initialized — — — — — — Initialized MAR_0BL Initialized —...
Page 780 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module SBYCR Initialized — — — — — — Initialized SYSTEM SCKCR Initialized — — — — — — Initialized SYSCR Initialized —...
Page 781 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module P1DR Initialized — — — — — — Initialized PORT P2DR Initialized — — — — — — Initialized P3DR Initialized —...
Page 782 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module ADDRA Initialized — — — — — — Initialized ADDRB Initialized — — — — — — Initialized ADDRC Initialized — —...
Page 783 Register High- Clock Module All Module Software Hardware Name Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TCR_0 Initialized — — — — — — Initialized TPU_0 TMDR_0 Initialized — — — — — — Initialized TIORH_0 Initialized —...
Page 784 Rev. 2.00, 05/03, page 732 of 820...
Page 785: Section 24 Electrical Characteristics
Section 24 Electrical Characteristics 24.1 Electrical Characteristics of Masked ROM and ROMless Versions 24.1.1 Absolute Maximum Ratings Table 24.1 lists the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.0 PLLV Input voltage (except ports 4, 9) –0.3 to V +0.3...
Page 786: Dc Characteristics
24.1.2 DC Characteristics Table 24.2 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item...
Page 787: Table 24.3 Dc Characteristics (2)
Table 24.3 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 788: Table 24.4 Permissible Output Currents
Test Item Symbol Unit Conditions Reference During A/D and — power D/A conversion (3.0 V) supply µA Idle — 0.01 current RAM standby voltage — — Notes: *1 When the A/D and D/A converters are not used, do not leave the AV , and AV pins open.
Page 789: Ac Characteristics
24.1.3 AC Characteristics C = 50 pF: ports A to G C = 30 pF: ports 1 to 3, LSI output pin P50 to P53, port 8 RL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (V = 3.0 V to 3.6 V) Figure 24.1 Output Load Circuit Rev.
Page 790: Figure 24.2 System Clock Timing
(1) Clock Timing Table 24.5 Clock Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 791: Figure 24.3 Oscillation Stabilization Timing (1)
EXTAL DEXT DEXT OSC1 OSC1 Figure 24.3 Oscillation Stabilization Timing (1) Oscillator NMIEG SSBY NMI exception handling Software standby mode NMI exception (power-down mode) handling Oscillation NMIEG = 1 stabilization time SSBY = 1 OSC2 SLEEP instruction Figure 24.3 Oscillation Stabilization Timing (2) Rev.
Page 792: Figure 24.4 Reset Input Timing
(2) Control Signal Timing Table 24.6 Control Signal Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 793: Figure 24.5 Interrupt Input Timing
NMIS NMIH NMIW IRQW (i = 0 to 7)* IRQS IRQH (edge input) IRQS (level input) Note: * Necessary for SSIER setting to clear software standby mode. Figure 24.5 Interrupt Input Timing Rev. 2.00, 05/03, page 741 of 820...
Page 794: Table 24.7 Bus Timing (1)
(3) Bus Timing Table 24.7 Bus Timing (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 795: Table 24.8 Bus Timing (2)
Table 24.8 Bus Timing (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 796 Item Symbol Unit Test Conditions WAIT setup time — Figures 24.8 and 24.14 WAIT hold time — BREQ setup time — Figure 24.22 BREQS BACK delay time — BACD Bus floating time — BREQO delay time — Figure 24.23 BRQOD Rev.
Page 797: Figure 24.6 Basic Bus Timing: Two-State Access
A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD2 Write WDH1 WSW1 D15 to D0 DACD1 DACD2 Figure 24.6 Basic Bus Timing: Two-State Access Rev.
Page 798: Figure 24.7 Basic Bus Timing: Three-State Access
A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD1 WDS1 Write WDH1 WSW2 D15 to D0 DACD1 DACD2 Figure 24.7 Basic Bus Timing: Three-State Access Rev.
Page 799: Figure 24.8 Basic Bus Timing: Three-State Access, One Wait
A23 to A0 Read (RDNn = 1) D15 to D0 Read (RDNn = 0) D15 to D0 Write D15 to D0 Figure 24.8 Basic Bus Timing: Three-State Access, One Wait Rev. 2.00, 05/03, page 747 of 820...
Page 800: Figure 24.9 Basic Bus Timing: Two-State Access (Cs Assertion Period Extended)
A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD2 Write WDS2 WSW1 WDH3 D15 to D0 DACD1 DACD2 CS Assertion Period Extended) Figure 24.9 Basic Bus Timing: Two-State Access (CS Rev.
Page 801: Figure 24.10 Basic Bus Timing: Three-State Access (Cs Assertion Period Extended)
A23 to A0 CSD1 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD2 RSD1 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD1 WDS3 Write WSW2 WDH3 D15 to D0 DACD1 DACD2 CS Assertion Period Extended) Figure 24.10 Basic Bus Timing: Three-State Access (CS Rev.
Page 802: Figure 24.11 Burst Rom Access Timing: One-State Burst Access
A23 to A6, A5 to A1 RSD2 Read RDS2 RDH2 D15 to D0 Figure 24.11 Burst ROM Access Timing: One-State Burst Access Rev. 2.00, 05/03, page 750 of 820...
Page 803: Figure 24.12 Burst Rom Access Timing: Two-State Burst Access
A23 to A6, A5 to A1 RSD2 RDS2 RDH2 Read D15 to D0 Figure 24.12 Burst ROM Access Timing: Two-State Burst Access Rev. 2.00, 05/03, page 751 of 820...
Page 804: Figure 24.13 Dram Access Timing: Two-State Access
A23 to A0 CSD3 CSD2 PCH2 CASD1 CASD1 CASW1 OED1 OED1 Read RDS2 RDH2 D15 to D0 WCS1 WCH1 WRD2 WRD2 Write WDS1 WDH2 D15 to D0 DACD1 DACD2 Notes: timing: when DDS = 0 timing: when RAST = 0 Figure 24.13 DRAM Access Timing: Two-State Access Rev.
Page 805: Figure 24.14 Dram Access Timing: Two-State Access, One Wait
A23 to A0 Read D15 to D0 Write D15 to D0 Notes: timing: when DDS = 0 timing: when RAST = 0 Tcw : Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 24.14 DRAM Access Timing: Two-State Access, One Wait Rev.
Page 806: Figure 24.15 Dram Access Timing: Two-State Burst Access
A23 to A0 CPW1 Read D15 to D0 Write RCS1 D15 to D0 DACD1 DACD2 Notes: timing: when DDS = 1 timing: when RAST = 1 Figure 24.15 DRAM Access Timing: Two-State Burst Access Rev. 2.00, 05/03, page 754 of 820...
Page 807: Figure 24.16 Dram Access Timing: Three-State Access (Rast = 1)
A23 to A0 CSD3 CSD2 PCH1 CASD1 CASD2 CASW2 OED2 OED1 Read RDS2 RDH2 D15 to D0 WCS2 WCH2 WRD2 WRD2 Write WDS2 WDH3 D15 to D0 DACD1 DACD2 Notes: timing: when DDS = 0 timing: when RAST = 1 Figure 24.16 DRAM Access Timing: Three-State Access (RAST = 1) Rev.
Page 808: Figure 24.17 Dram Access Timing: Three-State Burst Access
A23 to A0 CPW2 Read D15 to D0 Write RCS2 D15 to D0 Notes: timing: when DDS = 1 timing: when RAST = 1 Figure 24.17 DRAM Access Timing: Three-State Burst Access Rev. 2.00, 05/03, page 756 of 820...
Page 809: Figure 24.18 Cas-Before-Ras Refresh Timing
CSD1 CSD2 CSR1 CASD1 CASD1 Figure 24.18 CAS-Before-RAS Refresh Timing CSD1 CSD2 CSR2 CASD1 CASD1 Figure 24.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Self-refresh DRAM access CSD2 CSD2 RPS2 CASD1 CASD1 Figure 24.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Rev.
Page 810: Figure 24.21 Self-Refresh Timing (Return From Software Standby Mode: Rast = 1)
Self-refresh DRAM access CSD2 CSD2 RPS1 CASD1 CASD1 Figure 24.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) BREQS BREQS BACD BACD A23 to A0 D15 to D0 Figure 24.22 External Bus Release Timing Rev. 2.00, 05/03, page 758 of 820...
Page 811: Figure 24.23 External Bus Request Output Timing
BRQOD BRQOD Figure 24.23 External Bus Request Output Timing (4) DMAC Timing Table 24.9 DMAC Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ...
Page 812: Figure 24.24 Dmac Single Address Transfer Timing: Two-State Access
A23 to A0 (read) D15 to D0 (read) (write) D15 to D0 (write) DACD1 DACD2 Figure 24.24 DMAC Single Address Transfer Timing: Two-State Access Rev. 2.00, 05/03, page 760 of 820...
Page 813: Figure 24.25 Dmac Single Address Transfer Timing: Three-State Access
A23 to A0 (read) D15 to D0 (read) (write) D15 to D0 (write) DACD1 DACD2 Figure 24.25 DMAC Single Address Transfer Timing: Three-State Access or T Figure 24.26 DMAC TEND TEND Output Timing TEND TEND Rev. 2.00, 05/03, page 761 of 820...
Page 814: Figure 24.27 Dmac Dreq Input Timing
DRQS DRQH Figure 24.27 DMAC DREQ DREQ Input Timing DREQ DREQ (5) Timing of On-Chip Peripheral Modules Table 24.10 Timing of On-Chip Peripheral Modules Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V,...
Page 815 Item Symbol Min Unit Test Conditions Overflow output delay time — Figure 24.35 WOVD Input clock Asynchronous — Figure 24.36 Scyc cycle Synchronous — Input clock pulse width SCKW Scyc Input clock rise time — SCKr Input clock fall time —...
Page 816: Figure 24.28 I/O Port Input/Output Timing
Ports 1 to 6, 8 and 9, A to G (read) Ports 1 to 3, 6, 8, P53 to P50, ports A to G (write) Figure 24.28 I/O Port Input/Output Timing PO15 to PO0 Figure 24.29 PPG Output Timing TOCD Output compare output* TICS...
Page 817: Figure 24.31 Tpu Clock Input Timing
TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 24.31 TPU Clock Input Timing TMOD TMO0, TMO1 Figure 24.32 8-Bit Timer Output Timing TMCS TMCS TMCI0, TMCI1 TMCWL TMCWH Figure 24.33 8-Bit Timer Clock Input Timing TMRS TMRI0, TMRI1 Figure 24.34 8-Bit Timer Reset Input Timing Rev.
Page 818: Figure 24.35 Wdt Output Timing
WOVD WOVD Figure 24.35 WDT Output Timing SCKW SCKr SCKf SCK0 to SCK4 Scyc Figure 24.36 SCK Clock Input Timing SCK0 to SCK4 TxD0 to TxD4 (transmit data) RxD0 to RxD4 (receive data) Figure 24.37 SCI Input/Output Timing: Synchronous Mode TRGS Figure 24.38 A/D Converter External Trigger Input Timing Rev.
Page 819: Figure 24.39 I C Bus Interface Input/Output Timing (Option)
SDA0 SDA1 SCLH STOS STAH STAS SCL0 SCL1 SCLL SDAS SDAH Note: * S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 24.39 I C Bus Interface Input/Output Timing (Option) Rev.
Page 820: A/D Conversion Characteristics
24.1.4 A/D Conversion Characteristics Table 24.11 A/D Conversion Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 821: Electrical Characteristics Of F-Ztat Version
24.2 Electrical Characteristics of F-ZTAT Version 24.2.1 Absolute Maximum Ratings Table 24.13 lists the absolute maximum ratings. Table 24.13 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.0 PLLV Input voltage (except ports 4, 9) –0.3 to V +0.3 Input voltage (ports 4, 9) –0.3 to AV...
Page 822: Dc Characteristics
24.2.2 DC Characteristics Table 24.14 DC Characteristics (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item...
Page 823: Table 24.15 Dc Characteristics (2)
Table 24.15 DC Characteristics (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 824: Table 24.16 Permissible Output Currents
Test Item Symbol Unit Conditions Reference During A/D and — power D/A conversion (3.0 V) supply µA Idle — 0.01 current RAM standby voltage — — Notes: *1 When the A/D and D/A converters are not used, do not leave the AV , and AV pins open.
Page 825: Table 24.17 Clock Timing
(1) Clock Timing Table 24.17 Clock Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 826: Table 24.18 Control Signal Timing
(2) Control Signal Timing Table 24.18 Control Signal Timing Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 827: Table 24.19 Bus Timing (1)
(3) Bus Timing Table 24.19 Bus Timing (1) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 828: Table 24.20 Bus Timing (2)
Table 24.20 Bus Timing (2) Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item Symbol...
Page 829: Table 24.21 Dmac Timing
Item Symbol Unit Test Conditions WAIT setup time — Figure 24.14 WAIT hold time — BREQ setup time — Figure 24.22 BREQS BACK delay time — BACD Bus floating time — BREQO delay time — Figure 24.23 BRQOD Note: * Not supported by the H8S/2366. (4) DMAC Timing Note: The DMAC is not supported by the H8S/2366.
Page 830: Table 24.22 Timing Of On-Chip Peripheral Modules
(5) Timing of On-Chip Peripheral Modules Table 24.22 Timing of On-Chip Peripheral Modules Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 831 Item Symbol Min Unit Test Conditions Overflow output delay time — Figure 24.35 WOVD Input clock Asynchronous — Figure 24.36 Scyc cycle Synchronous — Input clock pulse width SCKW Scyc Input clock rise time — SCKr Input clock fall time —...
Page 832: A/D Conversion Characteristics
24.2.3 A/D Conversion Characteristics Table 24.23 A/D Conversion Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, φ = 8 MHz to 33 MHz, T = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Item...
Page 833: Flash Memory Characteristics
24.3 Flash Memory Characteristics Table 24.25 Flash Memory Characteristics Conditions: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV = 0 V, T = 0°C to 75°C (program/erase operating temperature range: regular specifications), T = 0°C to 85°C (program/erase operating temperature range: wide-range specifications)
Page 834 Test Item Symbol Min Unit Conditions µs Erasing Wait time after — — SWE bit setting* µs Wait time after — — ESU bit setting* µs Wait time after — — Erase time E bit setting* wait α µs Wait time after —...
Page 835: Usage Note
24.4 Usage Note The F-ZTAT and masked ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on.
Page 836 Rev. 2.00, 05/03, page 784 of 820...
Page 837: Appendix
Appendix I/O Port States in Each Pin State Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode Port 1 1, 2. 4, 7 Keep Keep I/O port Port 2 1, 2. 4, 7 Keep Keep I/O port...
Page 838 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode [OPE = 0, CS PA7/A23/ 1, 2. 4, 7 [Address output] [CS output] output] [Other than the [Address [OPE = 1, CS above] output] output]...
Page 839 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode Port B 1, 2 [OPE = 0] Address output [OPE = 1] A15 to A8 Keep [OPE = 0, [Address output] [Address address output] output]...
Page 840 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode Port C 3, 7 [OPE = 0, [Address output] [Address address output] output] A7 to A0 [Other than the [OPE = 1, above] [Other than address output]...
Page 841 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode RD, HWR PF5/RD 1, 2, 4 [OPE = 0] PF4/HWR [OPE = 1] [OPE = 0, RD, [RD, HWR [RD, HWR 3, 7 HWR output] output]...
Page 842 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode PF1/UCAS*/ 1, 2, 4, 7 [OPE = 0, [UCAS (DQMU) [UCAS UCAS (DQMU) output] (DQMU) output] output] UCAS [CS output] [OPE = 1, [CS output] UCAS (DQMU) [Other than the...
Page 843 Program Hardware Execution Operating Standby Software Bus Release State Sleep Port Name Mode Reset Mode Standby Mode State Mode PG4/ 1, 2, 4, 7 [BREQO [BREQO output] [BREQO BREQO/ BREQO output] output] BREQO BREQO [CS output] [OPE = 0, CS [CS output] output] [Other than the...
Page 844: Product Lineup
Note: The above products include those under development or being planned. For the status of each product, contact a Renesas sales office. When using the optional functions for the F- ZTAT version, which has the common type name, contact a Renesas sales office.
Page 845: Package Dimensions
Package Dimensions For package dimensions, dimensions described in Renesas Technology Packages have priority. Unit: mm 16.0 ± 0.2 *0.17 ± 0.05 0.07 0.15 ± 0.04 0˚ – 8˚ 0.5 ± 0.1 0.10 Package Code TFP-120 (TFP-120V JEDEC — EIAJ Conforms...
Page 846: Figure C.2 Package Dimensions (Fp-128B)
Unit: mm 22.0 ± 0.2 *0.22 ± 0.05 0.10 M 0.20 ± 0.04 0.75 0.75 0° − 8° 0.5 ± 0.2 0.10 Package Code FP-128B (FP-128BV JEDEC — EIAJ Conforms Dimension including the plating thickness Base material dimension Mass (reference value) 1.7 g *: Pb free version Figure C.2 Package Dimensions (FP-128B)
Page 847: Bus State During Execution Of Instructions
Bus State during Execution of Instructions Table D.1 shows the execution state of each instruction in this LSI. [Explanation of Table Contents] Order of execution Instruction 1 state of inter- R:W 2nd R:W EA nal operation End of instruction Read the effective address in words. Read/write is not performed.
Page 848: Figure D.1 Timing Of Address Bus, Rd, Hwr, And Lwr (8-Bit Bus, 3-State Access, No Wait)
Address bus High Internal R: W 2nd R: W EA operation Fetch of 3rd byte of Fetch of 4th byte of Fetch of 1st byte of Fetch of 2nd byte of instruction being instruction being brunch destination brunch destination executed executed instruction instruction...
Page 849: Table D.1 Execution State Of Instructions
Table D.1 Execution State of Instructions Instruction ADD.B #xx:8,Rd NEXT ADD.B Rs,Rd R:W NEXT ADD.W R:W 2nd R:W #xx:16,Rd NEXT ADD.W Rs,Rd R:W NEXT ADD.L R:W 2nd R:W 3rd R:W #xx:32,ERd NEXT ADD.L ERs,ERd NEXT ADDS #1/2/4,ERd NEXT ADDX #xx:8,Rd NEXT ADDX Rs,Rd R:W NEXT...
Page 850 Instruction BAND R:W 2nd R:B EA R:W #xx:3,@aa:8 NEXT BAND R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BAND R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BRA d:8 R:W EA (BT d:8) NEXT BRN d:8 R:W EA (BF d:8) NEXT...
Page 851 Instruction BRA d:16 R:W 2nd R:W EA 1 state of (BT d:16) internal operation BRN d:16 R:W 2nd R:W EA 1 state of (BF d:16) internal operation BHI d:16 R:W 2nd R:W EA 1 state of internal operation BLS d:16 R:W 2nd R:W EA 1 state of...
Page 852 Instruction BGT d:16 R:W 2nd R:W EA 1 state of internal operation BLE d:16 R:W 2nd R:W EA 1 state of internal operation BCLR #xx:3,Rd NEXT BCLR R:W 2nd R:B:M R:W:M W:B EA #xx:3,@ERd NEXT BCLR R:W 2nd R:B:M R:W:M W:B EA #xx:3,@aa:8 NEXT...
Page 853 Instruction BILD R:W 2nd R:B EA R:W #xx:3,@ERd NEXT BILD R:W 2nd R:B EA R:W #xx:3,@aa:8 NEXT BILD R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BILD R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BIOR #xx:3,Rd R:W NEXT BIOR R:W 2nd R:B EA R:W...
Page 854 Instruction BLD #xx:3,Rd R:W NEXT R:W 2nd R:B EA R:W #xx:3,@ERd NEXT R:W 2nd R:B EA R:W #xx:3,@aa:8 NEXT R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BNOT #xx:3,Rd NEXT BNOT...
Page 855 Instruction BSET #xx:3,Rd NEXT BSET R:W 2nd R:B:M R:W:M W:B EA #xx:3,@ERd NEXT BSET R:W 2nd R:B:M R:W:M W:B EA #xx:3,@aa:8 NEXT BSET R:W 2nd R:W 3rd R:B:M R:W:M W:B EA #xx:3,@aa:16 NEXT BSET R:W 2nd R:W 3rd R:W 4th R:B:M R:W:M W:B EA #xx:3,@aa:32...
Page 856 Instruction BTST R:W 2nd R:B EA R:W #xx:3,@aa:8 NEXT BTST R:W 2nd R:W 3rd R:B EA R:W #xx:3,@aa:16 NEXT BTST R:W 2nd R:W 3rd R:W 4th R:B EA R:W #xx:3,@aa:32 NEXT BTST Rn,Rd NEXT BTST R:W 2nd R:B EA R:W Rn,@ERd NEXT BTST...
Page 857 Instruction CMP.L R:W 2nd R:W 3rd R:W #xx:32,ERd NEXT CMP.L ERs,ERd NEXT DAA Rd NEXT DAS Rd NEXT DEC.B Rd NEXT DEC.W #1/2,Rd NEXT DEC.L #1/2,ERd NEXT DIVXS.B R:W 2nd R:W 11 states of internal Rs,Rd NEXT operation DIVXS.W R:W 2nd R:W 19 states of internal Rs,ERd NEXT...
Page 858 Instruction INC.L #1/2,ERd NEXT JMP @ERn R:W EA NEXT JMP @aa:24 R:W 2nd R:W EA 1 state of internal operation R:W:M R:W EA 1 state of Advanced @@aa NEXT aa:8 aa:8 internal operation R:W EA W:W:M Advanced @ERn NEXT Stack Stack (L) R:W 2nd R:W EA W:W:M...
Page 859 Instruction R:W 2nd R:W R:W EA 1 state of @ERs+,CCR NEXT internal operation R:W 2nd R:W R:W EA 1 state of @ERs+,EXR NEXT internal operation R:W 2nd R:W 3rd R:W R:W EA @aa:16,CCR NEXT R:W 2nd R:W 3rd R:W R:W EA @aa:16,EXR NEXT R:W 2nd R:W 3rd R:W 4th R:W...
Page 860 Instruction MOV.B R:W 2nd R:W 3rd R:W 4th R:W R:B EA @(d:32,ERs), NEXT MOV.B R:B EA 1 state of @ERs+,Rd NEXT internal operation MOV.B R:B EA @aa:8,Rd NEXT MOV.B R:W 2nd R:W R:B EA @aa:16,Rd NEXT MOV.B R:W 2nd R:W 3rd R:W R:B EA @aa:32,Rd NEXT...
Page 861 Instruction MOV.W R:W EA 1 state of @ERs+,Rd NEXT internal operation MOV.W R:W 2nd R:W R:W EA @aa:16,Rd NEXT MOV.W R:W 2nd R:W 3rd R:W R:B EA @aa:32,Rd NEXT MOV.W W:W EA Rs,@ERd NEXT MOV.W Rs, R:W 2nd R:W W:W EA @(d:16,ERd) NEXT MOV.W Rs,...
Page 862 Instruction MOV.L ERs, R:W 2nd R:W 3rd R:W W:W:M @(d:16,ERd) NEXT EA+2 MOV.L ERs, R:W 2nd R:W 3rd R:W 4th R:W 5th R:W W:W:M @(d:32,ERd) NEXT EA+2 MOV.L R:W 2nd R:W W:W:M 1 state of ERs,@-ERd NEXT EA+2 internal operation MOV.L R:W 2nd R:W 3rd R:W W:W:M...
Page 863 Instruction OR.B Rs,Rd NEXT OR.W R:W 2nd R:W #xx:16,Rd NEXT OR.W Rs,Rd NEXT OR.L R:W 2nd R:W 3rd R:W #xx:32,ERd NEXT OR.L R:W 2nd R:W ERs,ERd NEXT #xx:8,CCR NEXT R:W 2nd R:W #xx:8,EXR NEXT POP.W Rn R:W EA 1 state of NEXT internal operation...
Page 864 Instruction ROTR.W Rd NEXT ROTR.W #2,Rd NEXT ROTR.L ERd R:W NEXT ROTR.L #2,ERd NEXT ROTXL.B Rd R:W NEXT ROTXL.B #2,Rd NEXT ROTXL.W Rd R:W NEXT ROTXL.W #2,Rd NEXT ROTXL.L ERd R:W NEXT ROTXL.L #2,ERd NEXT ROTXR.B Rd R:W NEXT ROTXR.B #2,Rd NEXT ROTXR.W Rd R:W...
Page 865 Instruction SHAL.B #2,Rd R:W NEXT SHAL.W Rd NEXT SHAL.W #2,Rd NEXT SHAL.L ERd NEXT SHAL.L #2,ERd NEXT SHAR.B Rd NEXT SHAR.B #2,Rd R:W NEXT SHAR.W Rd NEXT SHAR.W #2,Rd NEXT SHAR.L ERd R:W NEXT SHAR.L #2,ERd NEXT SHLL.B Rd NEXT SHLL.B #2,Rd R:W NEXT SHLL.W Rd...
Page 866 Instruction SHLR.W #2,Rd NEXT SHLR.L ERd NEXT SHLR.L #2,ERd NEXT SLEEP Internal NEXT operation: STC CCR,Rd R:W NEXT STC EXR,Rd R:W NEXT R:W 2nd R:W W:W EA CCR,@ERd NEXT R:W 2nd R:W W:W EA EXR,@ERd NEXT STC CCR, R:W 2nd R:W 3rd R:W W:W EA @(d:16,ERd) NEXT...
Page 867 Instruction STM.L (ERn- R:W 2nd R:W W:W:M 1 state of ERn+1), NEXT Stack Stack (L) internal @-SP * (H) * operation STM.L (ERn- R:W 2nd R:W W:W:M 1 state of ERn+2), NEXT Stack Stack (L) internal @-SP * (H) * operation STM.L (ERn- R:W 2nd R:W...
Page 868 Instruction XOR.W Rs,Rd R:W NEXT XOR.L R:W 2nd R:W 3rd R:W #xx:32,ERd NEXT XOR.L R:W 2nd R:W ERs,ERd NEXT XORC #xx:8,CCR NEXT XORC R:W 2nd R:W #xx:8,EXR NEXT R:W:M R:W * 1 state of Reset Advanced VEC+2 internal exception operation handling R:W * R:W:M...
Page 869: Index
Index 16-Bit Timer Pulse Unit......373 BusController Buffer Operation ......... 418 DRAM Interface .........152 Cascaded Operation ......422 Valid Strobes........139 Input Capture Function ....... 415 Phase Counting Mode......429 Clock Pulse Generator ......675 PWM Modes........424 PLL Circuit .........680 Synchronous Operation....... 416 Condition Field .........47 Condition-Code Register......32 8-Bit Timer...
Page 870 Reset exception handling ...... 71 OVI ............. 487 Stack Status after Exception Handling . 76 RXI............581 Traces ........... 74 TCI1U ..........436 Trap Instruction ........75 TCI1V ..........436 Extended Control Register (EXR) .... 31 TCI2U ..........436 TCI2V ..........436 Flash Memory.........
Page 871 ADCSR ....... 623, 707, 720, 730 P3DDR......323, 701, 712, 724 ADDR ......622, 707, 719, 730 P3DR......324, 706, 718, 729 ASTCR ....... 111, 703, 714, 726 P3ODR......325, 702, 712, 725 BCR ......121, 703, 715, 726 P5DDR......333, 701, 712, 724 BROMCR ....
Page 872: Section 13 Watchdog Timer
PORTC ....... 353, 706, 718, 728 TIER ......404, 708, 720, 731 PORTD ....... 357, 706, 718, 728 TIOR ......386, 708, 720, 731 PORTE ....... 360, 706, 718, 728 TMDR......385, 708, 720, 731 PORTF......364, 706, 718, 728 TSR .....
Page 873 Publication Date: 1st Edition, March 2002 Rev.2.00, May 23, 2003 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. ©2002, 2003 Renesas Technology Corp. All rights reserved. Printed in Japan.
Page 874 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com Colophon 0.0...
Page 875 H8S/2368 Group Hardware Manual REJ09B0050-0200O...

This manual is also suitable for:

H8s series H8s/2300 series

Renesas H8S/2368 Series Hardware Manual

Quick Links

Related Manuals for Renesas H8S/2368 Series

Summary of Contents for Renesas H8S/2368 Series