Contention Between Tcor Write And Input Capture - Renesas H8/3067 Series User Manual

Section 10 8-Bit Timers
10.7.6

Contention between TCOR Write and Input Capture

If an input capture signal occurs in the T
and the write to TCOR is not performed. Figure 10.23 shows the timing in this case.
Address bus
Internal write signal
Input capture signal
TCNT
TCOR
Figure 10.23 Contention between TCOR Write and Input Capture
Rev. 4.00 Jan 26, 2006 page 430 of 938
REJ09B0276-0400
state of a TCOR write cycle, input capture takes priority
3
T
1
φ
TCOR write cycle
T
2
TCOR address
M
X
T
3
M