10.10.9 Contention Between Tgr Write And Input Capture; 10.10.10 Contention Between Buffer Register Write And Input Capture; Figure 10.50 Contention Between Tgr Write And Input Capture - Renesas H8S/2368 Series Hardware Manual

10.10.9 Contention between TGR Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR

Figure 10.50 Contention between TGR Write and Input Capture

10.10.10 Contention between Buffer Register Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
state of a TGR write cycle, the input capture
2
TGR write cycle
T T
1 2
TGR address
M
M
state of a buffer register write cycle, the buffer
2
Rev. 2.00, 05/03, page 449 of 820