Contention Between Tgr Write And Input Capture; Contention Between Buffer Register Write And Input Capture - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.10

Contention between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence
and the write to TGR is not performed.
Figure 10.105 shows the timing in this case.
Figure 10.105 Contention between TGR Write and Input Capture
10.7.11

Contention between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes
precedence and the write to the buffer register is not performed.
Figure 10.106 shows the timing in this case.
Figure 10.106 Contention between Buffer Register Write and Input Capture
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
P0φ
Address
Write signal
Input capture
signal
TCNT
TGR
P0φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer register
TGR write cycle
T1 T2
TGR address
M
M
Buffer register write cycle
T1 T2
Buffer register
address
N
M N
M
10. Multi-Function Timer Pulse Unit 2
10-146