Conflict Between Tgr Write And Input Capture; Conflict Between Buffer Register Write And Input Capture - Renesas H8S/2100 Series Hardware Manual

10.8.8

Conflict between TGR Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to TGR is not performed. Figure 10.49 shows the timing
in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Figure 10.49 Conflict between TGR Write and Input Capture
10.8.9

Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T
operation takes precedence and the write to the buffer register is not performed. Figure 10.50
shows the timing in this case.
Section 10 16-Bit Timer Pulse Unit (TPU)
state of a TGR write cycle, the input capture
2
TGR write cycle
T1 T2
TGR address
M
M
state of a buffer register write cycle, the buffer
2
Rev. 1.00 Apr. 28, 2008 Page 301 of 994
REJ09B0452-0100