Interrupt Sources; Usage Notes; Conflict Between Frc Write And Clear; Figure 9.17 Frc Write-Clear Conflict - Renesas H8S/2111B Hardware Manual

9.6

Interrupt Sources

The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts.
Table 9.2 FRT Interrupt Sources
Interrupt Interrupt Source
ICIA Input capture of ICRA
ICIB Input capture of ICRB
ICIC Input capture of ICRC
ICID Input capture of ICRD
OCIA Compare match of OCRA
OCIB Compare match of OCRB
FOVI Overflow of FRC
9.7

Usage Notes

9.7.1

Conflict between FRC Write and Clear

If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 9.17 shows the timing for this type of
conflict.
Write cycle of FRC
T
1
φ
Address FRC address
Internal write
signal
Counter clear
signal
FRC

Figure 9.17 FRC Write-Clear Conflict

Interrupt Flag
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
T
2
N H'0000
Rev. 1.00, 05/04, page 177 of 544
Priority
High
Low