Conflict Between Tgr Write And Input Capture; Conflict Between Buffer Register Write And Input Capture; Figure 9.52 Conflict Between Tgr Write And Input Capture; Figure 9.53 Conflict Between Buffer Register Write And Input Capture - Renesas H8SX/1520 Series Hardware Manual

9.9.9

Conflict between TGR Write and Input Capture

If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 9.52 shows the timing in this case.
9.9.10

Conflict between Buffer Register Write and Input Capture

If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 9.53 shows the timing in this case.

Figure 9.53 Conflict between Buffer Register Write and Input Capture

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Pφ
Address
Write
Input capture
signal
TCNT
TGR

Figure 9.52 Conflict between TGR Write and Input Capture

Pφ
Address
Write
Input capture
signal
TCNT
TGR
Buffer register
Section 9 16-Bit Timer Pulse Unit (TPU)
TGR write cycle
T1 T2
TGR address
M
M
Buffer register write cycle
T1 T2
Buffer register
address
N
M N
M
Rev. 3.00 Mar. 14, 2006 Page 341 of 804
REJ09B0104-0300