Conflict Between Tgr Write And Input Capture - Renesas H8SX/1650 Hardware Manual

P
Address
Read
Input capture signal
TGR
Internal data bus
Figure 9.50 Conflict between TGR Read and Input Capture
9.9.9

Conflict between TGR Write and Input Capture

If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 9.51 shows the timing in this case.
P
Address
Write
Input capture
signal
TCNT
TGR
Figure 9.51 Conflict between TGR Write and Input Capture
Section 9 16-Bit Timer Pulse Unit (TPU)
TGR read cycle
T T
1 2
TGR address
X M
M
TGR write cycle
T T
1 2
TGR address
M
M
Rev.2.00 Jun. 28, 2007 Page 385 of 666
REJ09B0311-0200