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Section 10 16-Bit Timer Pulse Unit (TPU)
10.8.7
Conflict between TGR Read and Input Capture
If the input capture signal is generated in the T
be the data after input capture transfer. Figure 10.48 shows the timing in this case.
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 10.48 Conflict between TGR Read and Input Capture
10.8.8
Conflict between TGR Write and Input Capture
If the input capture signal is generated in the T
operation takes precedence and the write to TGR is not performed. Figure 10.49 shows the timing
in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Figure 10.49 Conflict between TGR Write and Input Capture
Rev. 1.00 May 09, 2008 Page 286 of 954
REJ09B0462-0100
state of a TGR read cycle, the data that is read will
1
TGR read cycle
T1
T2
TGR address
X
M
M
state of a TGR write cycle, the input capture
2
TGR write cycle
T1
T2
TGR address
M
M
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