Conflict Between Tgr Write And Input Capture; Figure 18.77 Conflict Between Tgr Write And Input Capture - Renesas HD6417641 Hardware Manual

18.7.9

Conflict between TGR Write and Input Capture

If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 18.77 shows the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR

Figure 18.77 Conflict between TGR Write and Input Capture

Section 18 Multi-Function Timer Pulse Unit (MTU)
TGR write cycle
T1 T2
TGR address
M
M
Rev. 4.00 Sep. 14, 2005 Page 633 of 982
REJ09B0023-0400