Contention Between Tgr Write And Input Capture; Figure 10.50 Contention Between Tgr Write And Input Capture - Renesas H8S Series Hardware Manual

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.9

Contention between TGR Write and Input Capture

If an input capture signal is generated in the T
operation takes precedence and the write to TGR is not performed.
Figure 10.50 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR

Figure 10.50 Contention between TGR Write and Input Capture

Rev. 6.00 Mar 15, 2006 page 240 of 570
REJ09B0211-0600
state of a TGR write cycle, the input capture
2
TGR write cycle
T T
1 2
TGR address
M
M