Usage Notes; Conflict Between Frc Write And Clear; Figure 12.17 Frc Write-Clear Conflict - Renesas H8S/2158 User Manual

12.7

Usage Notes

12.7.1

Conflict between FRC Write and Clear

If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 12.17 shows the timing for this type of
conflict.
Write cycle of FRC
T 1
φ
Address FRC address
Internal write
signal
Counter clear
signal
FRC

Figure 12.17 FRC Write-Clear Conflict

Section 12 16-Bit Free-Running Timer (FRT)
T 2
N H'0000
Rev. 3.00 Jan 25, 2006 page 309 of 872
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