A6.2 Tlb Organization - ARM Cortex-A35 Technical Reference Manual

A6.2 TLB Organization
This section describes the organization of the TLB.
Micro TLB
Main TLB
IPA cache RAM
Walk cache RAM
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The first level of caching for the translation table information is a micro TLB of ten entries that
is implemented on each of the instruction and data sides. All main TLB related maintenance
operations result in flushing both the instruction and data micro TLB.
A unified main TLB handles misses from the micro TLBs. It has a 512-entry, 2-way, set-
associative structure and supports all VMSAv8 block sizes, except 1GB. If it fetches a 1GB
block, the TLB splits it into 512MB blocks and stores the appropriate block for the lookup.
Accesses to the main TLB take a variable number of cycles. The number of cycles depends on
the following criteria:
• Competing requests from each of the micro TLBs.
• The TLB maintenance operations in flight.
• The different page size mappings in use.
The Intermediate Physical Address (IPA) cache RAM holds mappings between intermediate
physical addresses and physical addresses. Only Non-secure EL1 and EL0 stage 2 translations
use this cache. When a stage 2 translation is completed, it is updated and checked whenever a
stage 2 translation is required.
Similarly to the main TLB, the IPA cache RAM can hold entries for different sizes.
The walk cache RAM holds the result of a stage 1 translation up to but not including the last
level. If the stage 1 translation results in a section or larger mapping then nothing is placed in the
walk cache.
The walk cache holds entries fetched from Secure and Non-secure state.
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A6 L1 Memory System

A6.2 TLB Organization

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