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STM32F078CB/RB/VB Errata sheet STM32F078CB/RB/VB device limitations Silicon identification This document applies to the STM32F078CB/RB/VB devices and their silicon revisions shown in Table Section 1 gives a summary and Section 2 a description of device limitations, with respect to the device datasheet and reference manual RM0091.
Summary of device limitations STM32F078CB/RB/VB Summary of device limitations The following table gives a quick references to all documented device limitations of STM32F078CB/RB/VB and their status: A = workaround available N = no workaround available P = partial workaround available “-”...
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STM32F078CB/RB/VB Summary of device limitations Table 2. Summary of device limitations (continued) Status Function Section Limitation Rev. ‘Y’, ‘1’ 2.4.1 BSY bit may stay high when SPI is disabled 2.4.2 BSY bit may stay high at the end of a data transfer in slave mode 2.4.3...
Description of device limitations STM32F078CB/RB/VB Description of device limitations The following sections describe device limitations and provide workarounds if available. They are grouped by device functions. USART 2.1.1 Start bit detected too soon when sampling for NACK signal from the smartcard...
STM32F078CB/RB/VB Description of device limitations Workaround Configure the I/O used for nRTS as alternate function after setting the UE and RE bits. 2.1.4 Receiver timeout counter starting in case of 2 stops bit configuration Description In the case of 2 stop bits configuration, the receiver timeout counter starts counting from the end of the second stop bit of the last character instead of the end of the first stop bit.
Description of device limitations STM32F078CB/RB/VB Workaround The only way to lock GPIOx_OTYPER[i] with i=15..8 is to lock also GPIOx_OTYPER[i-8]. 2.3.1 Wrong data sampling when data set-up time (t ) is shorter than SU;DAT one I2CCLK period Description The I²C-bus specification and user manual specify a minimum data set-up time (t ) as: SU;DAT...
STM32F078CB/RB/VB Description of device limitations To see the limitation, all the following conditions have to be fulfilled: • C has to be configured in 10-bit addressing mode (OA1MODE is set in the I2C_OAR1 register). • The high LSBs of the I C slave address are equal to the 10-bit addressing Read header value (i.e.
Description of device limitations STM32F078CB/RB/VB Workaround None. If several slave addresses are enabled, mixing 10-bit and 7-bit addresses, the 10-bit Slave address OA1 [7:1] must not be equal to the 7-bit slave address. 2.3.5 Wakeup frames may not wakeup the MCU mode when STOP mode...
STM32F078CB/RB/VB Description of device limitations 2.3.7 Wrong behavior in Stop mode when wakeup from Stop mode is disabled in I Description When wakeup from Stop mode is disabled in I C (WUPEN = 0) and the MCU enters Stop mode while a transfer is on going on the bus, some wrong behaviors may happen: BUSY flag can be wrongly set when the MCU exits Stop mode.
Description of device limitations STM32F078CB/RB/VB 2.4.1 BSY bit may stay high when SPI is disabled Description The BSY flag may remain high upon disabling the SPI while operating in: • a master transmit mode and the TXE flag is low (data register full).
STM32F078CB/RB/VB Description of device limitations 2.4.3 Wrong CRC transmitted in master mode with delayed SCK feedback Description In transmit transaction of the SPI/I S interface in SPI master mode with CRC enabled, the CRC data transmission may be corrupted if the delay of an internal feedback signal derived from the SCK output (further feedback clock) is greater than one APB clock period.
Description of device limitations STM32F078CB/RB/VB Workaround If possible, do not use the DMA channel, on which the SPI is mapped, by any other peripheral. If possible, remap SPI2 to a DMA channel not used by another peripheral. 2.4.6 In I...
STM32F078CB/RB/VB Description of device limitations 2.6.1 Spurious tamper detection when disabling the tamper channel Description If the tamper detection is configured for detecting on falling-edge event (TAMPFLT[1:0]=00 and TAMPxTRG=1) and if the tamper event detection is disabled when the tamper pin is at high level, a false detection of a tamper event occurs, which may result in the erasure of backup registers.
Description of device limitations STM32F078CB/RB/VB 2.7.1 Overrun flag not set if EOC reset coincides with new conversion end Description If the EOC flag is cleared by ADC_DR register read operation or by software during the same APB cycle in which the data from a new conversion are written in the ADC_DR register, the overrun event duly occurs (which results in the loss of either current or new data) but the overrun flag (OVR) may stay low.
STM32F078CB/RB/VB Description of device limitations 2.9.1 Transmission blocked when transmitted start bit is corrupted Description When the HDMI-CEC communication start bit transmitted by the device is corrupted by another device on the CEC line, the CEC transmission is stalled. This failure is unlikely to happen as the CEC start bit corruption by another device can only occur if that device does not respect the CEC communication protocol.
Description of device limitations STM32F078CB/RB/VB Workaround Do not use the following TSC control register configurations: • PGPSC[2:0] bits set to 000 and CTPL[3:0] bits set to 0000 or 0001 in TSC_CR register • PGPSC[2:0] bits set to 001 and bits CTPL[3:0] set to 0000 in TSC_CR register 2.11...
STM32F078CB/RB/VB Revision history Revision history Table 3. Document revision history Date Revision Changes 12-Jun-2014 Initial release. Added: USART: – Section 2.1.1: Start bit detected too soon when sampling for NACK signal from the smartcard – Section 2.1.2: Break request can prevent the Transmission Complete flag (TC) from being set –...
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Revision history STM32F078CB/RB/VB Table 3. Document revision history (continued) Date Revision Changes ADC: – Section 2.7.1: Overrun flag not set if EOC reset coincides with new conversion end – Section 2.7.2: ADEN bit cannot be set immediately after the ADC calibration COMP: –...
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