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Section 12 Watchdog Timer (WDT)
(2)
Reading from TCNT, TCSR, and RSTCSR
These registers can be read from in the same way as other registers. For reading, TCSR is assigned
to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7.
12.6.2
Conflict between Timer Counter (TCNT) Write and Increment
If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes
priority and the timer counter is not incremented. Figure 12.5 shows this operation.
Pφ
Address
Internal write signal
TCNT input clock
TCNT
Figure 12.5 Conflict between TCNT Write and Increment
12.6.3
Changing Values of Bits CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the
values of bits CKS2 to CKS0 are changed.
12.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode
If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is
operating, errors could occur in the incrementation. The watchdog timer must be stopped (by
clearing the TME bit to 0) before switching the timer mode.
Rev.2.00 Jun. 28, 2007 Page 446 of 666
REJ09B0311-0200
TCNT write cycle
T
T
1
2
N
Counter write data
M
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