Timing Of Watchdog Timer Overflow Flag (Wovf) Setting; Usage Notes; Contention Between Timer Counter (Tcnt) Write And Increment - Renesas H8S/2319 series Hardware Manual

11.3.4

Timing of Watchdog Timer Overflow Flag (WOVF) Setting

The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time,
the WDTOVF signal * goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an
internal reset signal is generated for the entire chip. Figure 11-7 shows the timing in this case.
Note: * The WDTOVF output function is not available in the F-ZTAT versions.
φ
TCNT
Overflow signal
(internal signal)
WOVF
WDTOVF signal*
Internal reset
signal
Note: * The WDTOVF output function is not available in the F-ZTAT versions.
11.4 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
11.5

Usage Notes

11.5.1

Contention between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T
takes priority and the timer counter is not incremented. Figure 11-8 shows this operation.
Rev. 5.00, 12/03, page 418 of 1088
H'FF
Figure 11-7 Timing of WOVF Setting
H'00
132 states
518 states
state of a TCNT write cycle, the write
2