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Section 13 Watchdog Timer (WDT)
13.6.2
Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T
takes priority and the timer counter is not incremented. Figure 13.6 shows this operation.
φ
Address
Internal write signal
TCNT input clock
TCNT
Figure 13.6 Conflict between TCNT Write and Increment
13.6.3
Changing Values of CKS2 to CKS0 Bits
If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of CKS2 to CKS0 bits.
13.6.4
Changing Value of PSS Bit
If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the
operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of
PSS bit.
13.6.5
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from/to watchdog timer to/from interval timer, while the WDT is
operating, errors could occur in the operation. Software must stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
Rev. 1.00 May 09, 2008 Page 360 of 954
REJ09B0462-0100
state of a TCNT write cycle, the write
2
TCNT write cycle
T 1
T 2
N
Counter write data
M
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