RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.7.5
Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not
incremented.
Figure 10.100 shows the timing in this case.
Figure 10.100
Contention between TCNT Write and Increment Operations
10.7.6
Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal
is also generated.
Figure 10.101 shows the timing in this case.
Figure 10.101
Contention between TGR Write and Compare Match
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
P0φ
Address
Write signal
TCNT input
clock
TCNT
P0φ
Address
Write signal
Compare
match signal
TCNT
TGR
TCNT write cycle
T1
T2
TCNT address
N
M
TCNT write data
TGR write cycle
T1
T2
TGR address
N
N + 1
N
M
TGR write data
10. Multi-Function Timer Pulse Unit 2
10-143