Conflict Between Timer Counter (Tcnt) Write And Increment; Changing Values Of Bits Cks2 To Cks0; Switching Between Watchdog Timer Mode And Interval Timer Mode; Figure 11.5 Conflict Between Tcnt Write And Increment - Renesas H8SX/1520 Series Hardware Manual

(2)
Reading from TCNT, TCSR, and RSTCSR
These registers can be read from in the same way as other registers. For reading, TCSR is assigned
to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7.
11.5.2

Conflict between Timer Counter (TCNT) Write and Increment

If a TCNT clock pulse is generated during the T2 state of a TCNT write cycle, the write takes
priority and the timer counter is not incremented. Figure 11.5 shows this operation.
Pφ
Address
Internal
write signal
TCNT
input clock
TCNT
11.5.3

Changing Values of Bits CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the
values of bits CKS2 to CKS0 are changed.
11.5.4

Switching between Watchdog Timer Mode and Interval Timer Mode

If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is
operating, errors could occur in the incrementation. The watchdog timer must be stopped (by
clearing the TME bit to 0) before switching the timer mode.
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TCNT write cycle
T
1

Figure 11.5 Conflict between TCNT Write and Increment

Section 11 Watchdog Timer (WDT)
T
2
N
Counter write data
Rev. 3.00 Mar. 14, 2006 Page 375 of 804
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