Conflict Between Tcnt Write And Increment Operations; Figure 18.72 Conflict Between Tcnt Write And Increment Operations - Renesas HD6417641 Hardware Manual

18.7.5

Conflict between TCNT Write and Increment Operations

If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 18.72 shows the timing in this case.
Pφ
Address
Write signal
TCNT input
clock
TCNT

Figure 18.72 Conflict between TCNT Write and Increment Operations

Section 18 Multi-Function Timer Pulse Unit (MTU)
TCNT write cycle
T1 T2
TCNT address
N M
TCNT write data
Rev. 4.00 Sep. 14, 2005 Page 629 of 982
REJ09B0023-0400