Renesas H8S/2319 series Manuals

Manuals and User Guides for Renesas H8S/2319 series. We have 1 Renesas H8S/2319 series manual available for free PDF download: Hardware Manual

Renesas H8S/2319 series Hardware Manual (1121 pages)

Renesas 16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 6.77 MB

Instruction Execution
10
Table of Contents
13
Section 1 Overview

31
- Overview
  31
- Block Diagram
  38
- Pin Description
  39
  - Pin Arrangement
    39
  - Pin Functions in each Operating Mode
    43
  - Pin Functions
    47
Section 2 CPU

55
- Overview
  55
- CPU Operating Modes
  58
- Address Space
  61
- Register Configuration
  62
  - Overview
    62
  - General Registers
    63
  - Control Registers
    64
  - Initial Register Values
    65
- Data Formats
  66
  - General Register Data Formats
    66
  - Memory Data Formats
    68
- Instruction Set
  69
- Addressing Modes and Effective Address Calculation
  82
  - Addressing Mode
    82
  - Effective Address Calculation
    85
- Processing States
  89
  - Overview
    89
  - Reset State
    90
  - Exception-Handling State
    91
  - Program Execution State
    93
  - Bus-Released State
    93
  - Power-Down State
    93
- Basic Timing
  94
- Usage Note
  97
  - TAS Instruction
    97
Section 3 MCU Operating Modes

99
Section 4 Exception Handling

129
- Overview
  129
  - Exception Handling Types and Priority
    129
  - Exception Handling Operation
    129
  - Exception Vector Table
    130
- Reset
  132
  - Overview
    132
  - Reset Sequence
    132
  - Interrupts after Reset
    133
  - State of On-Chip Supporting Modules after Reset Release
    133
- Traces
  134
- Interrupts
  135
- Trap Instruction
  136
- Stack Status after Exception Handling
  136
- Notes on Use of the Stack
  137
Section 5 Interrupt Controller

139
- Overview
  139
  - Features
    139
  - Block Diagram
    140
  - Pin Configuration
    141
  - Register Configuration
    141
- Register Descriptions
  142
- Interrupt Sources
  147
  - External Interrupts
    147
  - Internal Interrupts
    148
  - Interrupt Exception Vector Table
    148
- Interrupt Operation
  154
  - Interrupt Control Modes and Interrupt Operation
    154
  - Interrupt Control Mode 0
    157
  - Interrupt Control Mode 2
    159
  - Interrupt Exception Handling Sequence
    161
  - Interrupt Response Times
    163
- Usage Notes
  164
- DTC Activation by Interrupt
  166
  - Overview
    166
  - Block Diagram
    166
  - Operation
    167
Section 6 Bus Controller

169
- Overview
  169
  - Features
    169
  - Block Diagram
    170
  - Pin Configuration
    171
  - Register Configuration
    172
- Register Descriptions
  173
- Overview of Bus Control
  182
  - Area Partitioning
    182
  - Bus Specifications
    183
  - Memory Interfaces
    184
  - Advanced Mode
    185
  - Chip Select Signals
    186
- Basic Bus Interface
  187
  - Overview
    187
  - Data Size and Data Alignment
    187
  - Valid Strobes
    189
  - Basic Timing
    190
  - Wait Control
    198
- Burst ROM Interface
  200
  - Overview
    200
  - Basic Timing
    200
  - Wait Control
    202
- Idle Cycle
  203
  - Operation
    203
  - Pin States in Idle Cycle
    206
- Bus Release
  207
  - Overview
    207
  - Operation
    207
  - Pin States in External Bus Released State
    208
  - Transition Timing
    209
  - Usage Note
    210
- Bus Arbitration
  210
  - Overview
    210
  - Operation
    210
  - Bus Transfer Timing
    211
  - External Bus Release Usage Note
    211
- Resets and the Bus Controller
  211
Section 7 Data Transfer Controller

213
- Overview
  213
  - Features
    213
  - Block Diagram
    214
  - Register Configuration
    215
- Register Descriptions
  216
  - DTC Mode Register a (MRA)
    216
  - DTC Mode Register B (MRB)
    217
  - DTC Source Address Register (SAR)
    219
  - DTC Destination Address Register (DAR)
    219
  - DTC Transfer Count Register a (CRA)
    219
  - DTC Transfer Count Register B (CRB)
    220
  - DTC Enable Registers (DTCER)
    220
  - DTC Vector Register (DTVECR)
    221
  - Module Stop Control Register (MSTPCR)
    222
- Operation
  222
  - Overview
    222
  - Activation Sources
    226
  - DTC Vector Table
    227
  - Location of Register Information in Address Space
    230
  - Normal Mode
    231
  - Repeat Mode
    232
  - Block Transfer Mode
    233
  - Chain Transfer
    235
  - Operation Timing
    236
  - Number of DTC Execution States
    237
  - Procedures for Using DTC
    239
  - Examples of Use of the DTC
    240
- Interrupts
  244
- Usage Notes
  244
Section 8 I/O Ports

245
- Overview
  245
- Port 1
  250
  - Overview
    250
  - Register Configuration
    251
  - Pin Functions
    253
- Port 2
  262
  - Overview
    262
  - Register Configuration
    262
  - Pin Functions
    264
- Port 3
  272
  - Overview
    272
  - Register Configuration
    272
  - Pin Functions
    275
- Port 4
  277
  - Overview
    277
  - Register Configuration
    277
  - Pin Functions
    278
- Port a
  278
  - Overview
    278
  - Register Configuration
    279
  - Pin Functions
    282
  - MOS Input Pull-Up Function
    283
- Port B
  284
  - Overview
    284
  - Register Configuration
    285
  - Pin Functions
    287
  - MOS Input Pull-Up Function
    289
- Port C
  290
  - Overview
    290
  - Register Configuration
    291
  - Pin Functions
    293
  - MOS Input Pull-Up Function
    295
- Port D
  296
  - Overview
    296
  - Register Configuration
    297
  - Pin Functions
    299
  - MOS Input Pull-Up Function
    300
- Port E
  302
  - Overview
    302
  - Register Configuration
    303
  - Pin Functions
    305
  - MOS Input Pull-Up Function
    306
- Port F
  308
  - Overview
    308
  - Register Configuration
    309
  - Pin Functions
    314
- Port G
  317
  - Overview
    317
    
    Register Configuration
    318
    
    Pin Functions
    322
  - Features
    325
Section 9 16-Bit Timer Pulse Unit (TPU)

325
- Block Diagram
  329
- Pin Configuration
  330
- Register Configuration
  332
- Register Descriptions
  334
  - Timer Mode Registers (TMDR)
    339
  - Timer I/O Control Registers (TIOR)
    341
  - Timer Interrupt Enable Registers (TIER)
    354
  - Timer Status Registers (TSR)
    356
  - Timer Counters (TCNT)
    360
  - Timer Start Register (TSTR)
    361
    
    Module Stop Control Register (MSTPCR)
    362
    
    Interface to Bus Master
    363
    
    Operation
    365
  - Basic Functions
    366
  - Synchronous Operation
    372
  - Buffer Operation
    374
  - Cascaded Operation
    378
  - PWM Modes
    380
  - Phase Counting Mode
    385
- Interrupts
  392
  - A/D Converter Activation
    394
  - DTC Activation
    394
  - Operation Timing
    395
  - Interrupt Signal Timing
    399
  - Usage Notes
    403
Section 10 8-Bit Timers

413
- Block Diagram
  414
- Pin Configuration
  415
- Register Descriptions
  416
- Module Stop Control Register (MSTPCR)
  422
- Operation
  423
- Operation with Cascaded Connection
  427
- Interrupts
  428
- Sample Application
  429
- Usage Notes
  430
Section 11 Watchdog Timer

437
- Features
  437
- Block Diagram
  438
- Pin Configuration
  439
- Register Configuration
  439
- Timer Control/Status Register (TCSR)
  439
- Reset Control/Status Register (RSTCSR)
  439
- Notes on Register Access
  440
- Register Descriptions
  440
- Operation in Watchdog Timer Mode
  445
- Operation in Interval Timer Mode
  447
- Timing of Overflow Flag (OVF) Setting
  447
- Timing of Watchdog Timer Overflow Flag (WOVF) Setting
  448
- Usage Notes
  448
- Overview
  451
Section 12 Serial Communication Interface (SCI)

451
- Block Diagram
  453
- Pin Configuration
  454
- Bit Rate Register (BRR)
  455
- Register Configuration
  455
- Serial Control Register (SCR)
  455
- Serial Mode Register (SMR)
  455
- Serial Status Register (SSR)
  455
- Smart Card Mode Register (SCMR)
  455
- Transmit Data Register (TDR)
  455
  - Module Stop Control Register (MSTPCR)
    478
  - Operation
    479
- Overview
  479
- Operation in Asynchronous Mode
  481
- Multiprocessor Communication Function
  492
- Operation in Synchronous Mode
  500
- SCI Interrupts
  509
- Usage Notes
  510
Section 13 Smart Card Interface

517
- Overview
  517
  - Features
    517
  - Block Diagram
    518
  - Pin Configuration
    519
  - Register Configuration
    520
- Register Descriptions
  521
  - Smart Card Mode Register (SCMR)
    521
  - Serial Status Register (SSR)
    522
  - Serial Mode Register (SMR)
    523
  - Serial Control Register (SCR)
    525
  - Overview
    526
  - Pin Connections
    526
  - Operation
    526
  - Data Format
    528
  - Register Settings
    530
  - Clock
    532
  - Data Transfer Operations
    534
  - Operation in GSM Mode
    541
  - Operation in Block Transfer Mode
    542
- Usage Notes
  543
Section 14 A/D Converter (8 Analog Input Channel Version)

547
- Overview
  547
  - Block Diagram
    548
  - Pin Configuration
    549
  - Register Configuration
    550
  - A/D Control Register (ADCR)
    550
  - Register Descriptions
    551
  - Module Stop Control Register (MSTPCR)
    555
- Interface to Bus Master
  556
- Operation
  557
  - Single Mode (SCAN = 0)
    557
  - Scan Mode (SCAN = 1)
    559
  - Input Sampling and A/D Conversion Time
    561
  - External Trigger Input Timing
    562
- Interrupts
  563
- Usage Notes
  564
Section 15 D/A Converter

569
- Overview
  569
  - Block Diagram
    570
  - Pin Configuration
    571
  - Register Configuration
    571
- Register Descriptions
  572
- Operation
  575
Section 16 RAM

577
- Overview
  577
  - Block Diagram
    577
  - Register Configuration
    578
- Operation
  579
- Usage Note
  579
Section 17 ROM

581
- Overview
  581
  - Block Diagram
    581
  - Register Configuration
    582
- Register Descriptions
  582
  - Mode Control Register (MDCR)
    582
  - Bus Control Register L (BCRL)
    583
- Operation
  583
- Overview of Flash Memory (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT)
  587
  - Overview
    588
- Flash Memory Operating Modes
  589
  - On-Board Programming Modes
    590
  - Flash Memory Emulation in RAM
    592
  - Differences between Boot Mode and User Program Mode
    593
  - Block Configuration
    594
  - Pin Configuration
    595
  - Register Configuration
    596
- Register Descriptions
  597
- Programming/Erasing Flash Memory
  613
  - Program-Verify Mode
    614
  - Erase Mode
    616
  - Flash Memory Protection
    618
  - Error Protection
    619
  - Flash Memory Emulation in RAM
    621
    
    RAM Overlap
    622
    
    Interrupt Handling When Programming/Erasing Flash Memory
    623
    
    Flash Memory Programmer Mode
    624
  - Socket Adapters and Memory Map
    625
    
    Programmer Mode Operation
    627
    
    Memory Read Mode
    628
- Auto-Program Mode
  631
- Auto-Erase Mode
  633
- Status Read Mode
  634
- Overview
  643
  - Flash Memory Operating Modes
    644
  - On-Board Programming Modes
    645
- Flash Memory Emulation in RAM
  647
- Register Descriptions
  652
- On-Board Programming Modes
  661
- Flash Memory Protection
  673
  - 17.17.1 Hardware Protection
    673
  - Software Protection
    674
  - 17.17.3 Error Protection
    675
- Flash Memory Emulation in RAM
  677
  - 17.18.1 Emulation in RAM
    677
  - 17.18.2 RAM Overlap
    678
- Interrupt Handling When Programming/Erasing Flash Memory
  679
- Flash Memory Programmer Mode
  680
  - 17.20.1 Programmer Mode Setting
    680
  - 17.20.2 Socket Adapters and Memory Map
    680
  - 17.20.3 Programmer Mode Operation
    682
  - 17.20.4 Memory Read Mode
    683
  - Auto-Program Mode
    683
  - Auto-Erase Mode
    683
  - Status Read Mode
    683
    
    Auto-Program Mode
    686
    
    Auto-Erase Mode
    688
    
    Status Read Mode
    689
  - 17.20.8 Status Polling
    690
  - 17.20.9 Programmer Mode Transition Time
    691
  - 17.20.10 Notes on Memory Programming
    691
- Flash Memory Programming and Erasing Precautions
  692
- Overview of Flash Memory (H8S/2319C 0.18ΜM F-ZTAT)
  694
  - 17.22.1 Features
    694
  - 17.22.2 Overview
    696
  - 17.22.3 Operating Mode of Flash Memory
    697
  - 17.22.4 Mode Comparison
    698
  - 17.22.5 Flash MAT Configuration
    699
  - 17.22.6 Block Division
    699
  - 17.22.7 Programming/Erasing Interface
    700
  - Pin Configuration
    703
  - Register Configuration
    704
- Register Description of Flash Memory
  705
- On-Board Programming Mode
  726
  - Boot Mode
    726
  - 17.24.2 User Program Mode
    729
  - 17.24.3 User Boot Mode
    740
- Protection
  743
  - Hardware Protection
    744
  - Software Protection
    744
  - Software Protection
    745
  - 17.25.3 Error Protection
    745
- Flash Memory Emulation in RAM
  747
- Switching between User MAT and User Boot MAT
  750
  - 17.27.1 Usage Notes
    751
- PROM Mode
  753
  - 17.28.1 Pin Arrangement of the Socket Adapter
    753
  - 17.28.2 PROM Mode Operation
    756
  - 17.28.3 Memory-Read Mode
    757
  - 17.28.4 Auto-Program Mode
    757
  - 17.28.5 Auto-Erase Mode
    758
  - 17.28.6 Status-Read Mode
    758
  - 17.28.7 Status Polling
    759
  - 17.28.8 Time Taken in Transition to PROM Mode
    759
  - 17.28.9 Notes on Using PROM Mode
    759
- Further Information
  761
Section 18 Clock Pulse Generator

799
- Overview
  799
  - Block Diagram
    799
  - Register Configuration
    800
- Register Descriptions
  800
- System Clock Control Register (SCKCR)
  800
- Oscillator
  802
  - Connecting a Crystal Resonator
    802
  - External Clock Input
    804
- Duty Adjustment Circuit
  806
- Medium-Speed Clock Divider
  806
- Bus Master Clock Selection Circuit
  806
Section 19 Power-Down Modes

807
- Register Configuration
  808
- Register Descriptions
  809
- System Clock Control Register (SCKCR)
  811
- Module Stop Control Register (MSTPCR)
  813
- Medium-Speed Mode
  814
- Sleep Mode
  815
- Usage Notes
  816
- Software Standby Mode
  817
  - Setting Oscillation Stabilization Time after Clearing Software Standby Mode
    818
  - Usage Notes
    819
- Hardware Standby Mode
  820
- Φ Clock Output Disabling Function
  821
Section 20 Electrical Characteristics

823
- DC Characteristics
  824
- AC Characteristics
  826
- A/D Conversion Characteristics
  844
- D/A Conversion Characteristics
  845
- Absolute Maximum Ratings
  854
  - DC Characteristics
    855
  - AC Characteristics
    858
  - A/D Conversion Characteristics
    862
- Flash Memory Characteristics
  863
- Electrical Characteristics of F-ZTAT Version (H8S/2319C F-ZTAT) (in Planning)
  865
  - DC Characteristics
    866
  - AC Characteristics
    869
  - A/D Conversion Characteristics
    873
  - D/A Conversion Characteristics
    873
  - Flash Memory Characteristics
    874
  - Usage Note (Internal Voltage Step down for the H8S/2319C F-ZTAT)
    874
- Usage Note
  875
Appendix A Instruction Set

877
- Instruction List
  877
- Instruction Codes
  901
- A.2 Instruction Codes
  901
- Operation Code Map
  916
- Number of States Required for Instruction Execution
  920
- Bus States During Instruction Execution
  934
- Condition Code Modification
  948
Appendix B Internal I/O Registers

954
- List of Registers (Address Order)
  954
- List of Registers (by Module)
  963
- Functions
  972
  - B.3 Functions
    972
  - Bus Controller
    999
Appendix C I/O Port Block Diagrams

1081
- Port 1
  1081
- Port 2
  1081
- Port 3
  1085
- Port 4
  1085
  - C.2 Port
    1085
  - C.3 Port
    1086
  - C.4 Port
    1089
- Port a
  1090
- Port B
  1091
- Port C
  1092
- Port D
  1093
- Port E
  1094
- Port F
  1095
- Port G
  1103
Appendix D Pin States

1108
- Port States in each Mode
  1108
Appendix E Product Lineup

1114
Appendix F Package Dimensions

1116

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Renesas H8S/2319 series Hardware Manual (1121 pages)

Table of Contents

Section 1 Overview

Section 2 CPU

Section 3 MCU Operating Modes

Section 4 Exception Handling

Section 5 Interrupt Controller

Section 6 Bus Controller

Section 7 Data Transfer Controller

Section 8 I/O Ports

Section 9 16-Bit Timer Pulse Unit (TPU)

Section 10 8-Bit Timers

Section 11 Watchdog Timer

Section 12 Serial Communication Interface (SCI)

Section 13 Smart Card Interface

Section 14 A/D Converter (8 Analog Input Channel Version)

Section 15 D/A Converter

Section 16 RAM

Section 17 ROM

Section 18 Clock Pulse Generator

Section 19 Power-Down Modes

Section 20 Electrical Characteristics

Appendix A Instruction Set

Appendix B Internal I/O Registers

Appendix C I/O Port Block Diagrams

Appendix D Pin States

Appendix E Product Lineup

Appendix F Package Dimensions

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