Conflict Between Timer Counter (Tcnt) Write And Increment - Renesas H8S/2100 Series Hardware Manual

<TCNT write>
Address : H'FFA8
<TCSR write>
Address : H'FFA8
(2) Reading from TCNT and TCSR (Example of WDT_0)
These registers are read in the same way as other registers. The read address is H'FFA8 for TCSR
and H'FFA9 for TCNT.
14.6.2

Conflict between Timer Counter (TCNT) Write and Increment

If a timer counter clock pulse is generated during the T
takes priority and the timer counter is not incremented. Figure 14.6 shows this operation.
φ
Address
Internal write signal
TCNT input clock
TCNT
Figure 14.6 Conflict between TCNT Write and Increment
15
15
Figure 14.5 Writing to TCNT and TCSR (WDT_0)
8 7
H'5A
8 7
H'A5
state of a TCNT write cycle, the write
2
TCNT write cycle
T 1 T 2
N
Counter write data
Rev. 1.00 Apr. 28, 2008 Page 401 of 994
Section 14 Watchdog Timer (WDT)
0
Write data
0
Write data
M
REJ09B0452-0100