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Hitachi H8S/2194 Series
Renesas Hitachi H8S/2194 Series Manuals
Manuals and User Guides for Renesas Hitachi H8S/2194 Series. We have
1
Renesas Hitachi H8S/2194 Series manual available for free PDF download: Hardware Manual
Renesas Hitachi H8S/2194 Series Hardware Manual (1065 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 5.46 MB
Table of Contents
Table of Contents
10
Section 1 Overview
28
Overview
28
Internal Block Diagram
33
Pin Arrangement and Functions
34
Pin Arrangement
34
Pin Functions
35
Differences between H8S/2194C Series and H8S/2194 Series
41
Section 2 CPU
42
Overview
42
Features
42
Differences between H8S/2600 CPU and H8S/2000 CPU
43
Differences from H8/300 CPU
43
Differences from H8/300H CPU
44
CPU Operating Modes
45
Address Space
50
Register Configuration
51
Overview
51
General Registers
52
Control Registers
53
Initial Register Values
54
Data Formats
55
General Register Data Formats
55
Memory Data Formats
57
Instruction Set
58
Overview
58
Instructions and Addressing Modes
59
Table of Instructions Classified by Function
60
Basic Instruction Formats
70
Notes on Use of Bit-Manipulation Instructions
71
Addressing Modes and Effective Address Calculation
72
Addressing Mode
72
Effective Address Calculation
75
Processing States
79
Overview
79
Reset State
80
Exception-Handling State
81
Program Execution State
82
Power-Down State
83
Basic Timing
84
Overview
84
On-Chip Memory (ROM, RAM)
84
On-Chip Supporting Module Access Timing
85
Usage Note
85
Section 3 MCU Operating Modes
86
Overview
86
Operating Mode Selection
86
Register Configuration
86
Register Descriptions
87
Mode Control Register (MDCR)
87
System Control Register (SYSCR)
87
Operating Mode Descriptions
89
Mode 1
89
Address Map
90
Section 4 Power-Down State
94
Overview
94
Register Configuration
98
Register Descriptions
99
Standby Control Register (SBYCR)
99
Low-Power Control Register (LPWRCR)
101
Timer Register a (TMA)
103
Module Stop Control Register (MSTPCR)
104
Medium-Speed Mode
105
Sleep Mode
106
Clearing Sleep Mode
106
Module Stop Mode
107
Standby Mode
108
Clearing Standby Mode
108
Setting Oscillation Settling Time after Clearing Standby Mode
108
Watch Mode
110
Clearing Watch Mode
110
Subsleep Mode
111
Clearing Subsleep Mode
111
Subactive Mode
112
Clearing Subactive Mode
112
Direct Transition
113
Overview of Direct Transition
113
Section 5 Exception Handling
114
Overview
114
Exception Handling Types and Priority
114
Exception Handling Operation
115
Exception Sources and Vector Table
115
Reset
117
Overview
117
Reset Sequence
117
Interrupts after Reset
118
Interrupts
119
Trap Instruction
120
Stack Status after Exception Handling
121
Notes on Use of the Stack
122
Section 6 Interrupt Controller
124
Overview
124
Features
124
Block Diagram
125
Pin Configuration
126
Register Configuration
126
Register Descriptions
127
System Control Register (SYSCR)
127
Interrupt Control Registers a to D (ICRA to ICRD)
128
IRQ Enable Register (IENR)
129
IRQ Edge Select Registers (IEGR)
130
IRQ Status Register (IRQR)
131
Port Mode Register (PMR1)
132
Interrupt Sources
133
External Interrupts
133
Internal Interrupts
135
Interrupt Exception Vector Table
135
Interrupt Operation
138
Interrupt Control Modes and Interrupt Operation
138
Interrupt Control Mode 0
140
Interrupt Control Mode 1
142
Interrupt Exception Handling Sequence
145
Interrupt Response Times
146
Usage Notes
147
Contention between Interrupt Generation and Disabling
147
Instructions that Disable Interrupts
148
Interrupts During Execution of EEPMOV Instruction
148
When NMI Is Disabled
148
Section 7 ROM (H8S/2194 Series)
150
Overview
150
Block Diagram
150
Overview of Flash Memory
151
Features
151
Block Diagram
152
Flash Memory Operating Modes
153
Pin Configuration
157
Register Configuration
157
Flash Memory Register Descriptions
158
Flash Memory Control Register 1 (FLMCR1)
158
Flash Memory Control Register 2 (FLMCR2)
161
Erase Block Registers 1 and 2 (EBR1, EBR2)
163
Serial/Timer Control Register (STCR)
164
On-Board Programming Modes
165
Boot Mode
166
User Program Mode
171
Programming/Erasing Flash Memory
172
Program Mode
172
Program-Verify Mode
173
Erase Mode
175
Erase-Verify Mode
175
Flash Memory Protection
177
Hardware Protection
177
Software Protection
178
Error Protection
179
Interrupt Handling When Programming/Erasing Flash Memory
180
Flash Memory Programmer Mode
181
Programmer Mode Setting
181
Socket Adapters and Memory Map
181
Programmer Mode Operation
182
Memory Read Mode
184
Auto-Program Mode
187
Auto-Erase Mode
189
Status Read Mode
190
Status Polling
192
Programmer Mode Transition Time
193
Notes on Memory Programming
193
Flash Memory Programming and Erasing Precautions
194
Note on Switching from F-ZTAT Version to Mask ROM Version
196
Section 8 ROM (H8S/2194C Series)
198
Overview
198
Block Diagram
198
Overview of Flash Memory
199
Features
199
Block Diagram
200
Flash Memory Operating Modes
201
Pin Configuration
205
Register Configuration
205
Flash Memory Register Descriptions
206
Flash Memory Control Register 1 (FLMCR1)
206
Flash Memory Control Register 2 (FLMCR2)
209
Erase Block Registers 1 (EBR1)
212
Erase Block Registers 2 (EBR2)
212
Serial/Timer Control Register (STCR)
214
On-Board Programming Modes
215
Boot Mode
216
User Program Mode
221
Programming/Erasing Flash Memory
222
Program Mode (N = 1 for Addresses H'0000 to H'1FFFF and N= 2 for Addresses H'20000 to H'3FFFF)
222
Program-Verify Mode (N =1 for Addresses H'00000 to H'1FFFF and N = 2 for Addresses H'20000 to H'3FFFF)
223
Erase Mode (N = 1 for Addresses H'00000 to H'1FFFF and N = 2 for Address H'20000 to H'3FFFF)
225
Erase-Verify Mode (N = 1 for Addresses H'00000 to H'1FFFF and N = 2 for Address H'20000 to H'3FFFF)
225
Flash Memory Protection
227
Hardware Protection
227
Software Protection
228
Error Protection
229
Interrupt Handling When Programming/Erasing Flash Memory
230
Flash Memory Programmer Mode
231
Programmer Mode Setting
231
Socket Adapters and Memory Map
231
Programmer Mode Operation
232
Memory Read Mode
234
Auto-Program Mode
237
Auto-Erase Mode
239
Status Read Mode
240
Status Polling
242
Programmer Mode Transition Time
243
Notes on Memory Programming
243
Flash Memory Programming and Erasing Precautions
244
Note on Switching from F-ZTAT Version to Mask ROM Version
246
Section 9 RAM
248
Overview
248
Block Diagram
248
Section 10 Clock Pulse Generator
250
Overview
250
Block Diagram
250
Register Configuration
250
Register Descriptions
251
Standby Control Register (SBYCR)
251
Low-Power Control Register (LPWRCR)
252
Oscillator
253
Connecting a Crystal Resonator
253
External Clock Input
255
Duty Adjustment Circuit
258
Medium-Speed Clock Divider
258
Bus Master Clock Selection Circuit
258
Subclock Oscillator Circuit
259
Connecting 32.768 Khz Crystal Resonator
259
External Clock Input
260
When Subclock Is Not Needed
260
Subclock Waveform Shaping Circuit
261
Notes on the Resonator
261
Section 11 I/O Port
262
Overview
262
Port Functions
262
Port Input
262
MOS Pull-Up Transistors
264
Port 0
265
Overview
265
Register Configuration
266
Pin Functions
267
Pin States
267
Port 1
268
Overview
268
Register Configuration
268
Pin Functions
272
Pin States
273
Port 2
274
Overview
274
Register Configuration
274
Pin Functions
278
Pin States
280
Port 3
281
Overview
281
Register Configuration
281
Pin Functions
285
Pin States
287
Port 4
288
Overview
288
Register Configuration
288
Pin Functions
291
Pin States
293
Port 5
294
Overview
294
Register Configuration
294
Pin Functions
298
Pin States
299
Port 6
300
Overview
300
Register Configuration
301
Pin Functions
304
Operation
305
Pin States
306
Port 7
307
Overview
307
Register Configuration
307
Pin Functions
309
Pin States
309
Port 8
310
11.10.1 Overview
310
Register Configuration
310
11.10.3 Pin Functions
313
11.10.4 Pin States
315
Section 12 Timer a
316
Overview
316
Features
316
Block Diagram
317
Register Configuration
317
Descriptions of Respective Registers
318
Timer Mode Register a (TMA)
318
Timer Counter a (TCA)
320
Module Stop Control Register (MSTPCR)
320
Operation
321
Operation as the Interval Timer
321
Operation of the Timer for Clocks
321
Initializing the Counts
321
Section 13 Timer B
322
Overview
322
Features
322
Block Diagram
322
Pin Configuration
323
Register Configuration
323
Descriptions of Respective Registers
324
Timer Mode Register B (TMB)
324
Timer Counter B (TCB)
326
Timer Load Register B (TLB)
326
Port Mode Register 5 (PMR5)
327
Module Stop Control Register (MSTPCR)
327
Operation
329
Operation as the Interval Timer
329
Operation as the Auto Reload Timer
329
Event Counter
329
Section 14 Timer J
330
Overview
330
Features
330
Block Diagram
330
Pin Configuration
332
Register Configuration
332
Descriptions of Respective Registers
333
Timer Mode Register J (TMJ)
333
Timer J Control Register (TMJC)
337
Timer J Status Register (TMJS)
339
Timer Counter J (TCJ)
340
Timer Counter K (TCK)
340
Timer Load Register J (TLJ)
341
Timer Load Register K (TLK)
341
Module Stop Control Register (MSTPCR)
342
Operation
343
8-Bit Reload Timer (TMJ-1)
343
8-Bit Reload Timer (TMJ-2)
343
Remote Controlled Data Transmission
344
Section 15 Timer L
348
Overview
348
Features
348
Block Diagram
349
Register Configuration
350
Descriptions of Respective Registers
351
Timer L Mode Register (LMR)
351
Linear Time Counter (LTC)
353
Reload/Compare Match Register (RCR)
353
Module Stop Control Register (MSTPCR)
354
Operation
355
Compare Match Clear Operation
355
Section 16 Timer R
358
Overview
358
Features
358
Block Diagram
358
Pin Configuration
360
Register Configuration
360
Descriptions of Respective Registers
361
Timer R Mode Register 1 (TMRM1)
361
Timer R Mode Register 2 (TMRM2)
363
Timer R Control/Status Register (TMRCS)
366
Timer R Capture Register 1 (TMRCP1)
368
Timer R Capture Register 2 (TMRCP2)
369
Timer R Load Register 1 (TMRL1)
369
Timer R Load Register 2 (TMRL2)
370
Timer R Load Register 3 (TMRL3)
370
Module Stop Control Register (MSTPCR)
371
Operation
372
Reload Timer Counter Equipped with Capturing Function TMRU-1
372
Reload Timer Counter Equipped with Capturing Function TMRU-2
373
Reload Counter Timer TMRU-3
373
Mode Identification
374
Reeling Controls
374
Acceleration and Braking Processes of the Capstan Motor
374
Slow Tracking Mono-Multi Function
375
Interrupt Cause
377
Exemplary Settings for Respective Functions
378
Mode Identification
378
Reeling Controls
379
Slow Tracking Mono-Multi Function
379
Acceleration and Braking Processes of the Capstan Motor
380
Section 17 Timer X1
382
Overview
382
Features
382
Block Diagram
383
Pin Configuration
384
Register Configuration
385
Descriptions of Respective Registers
386
Free Running Counter (FRC)
386
Output Comparing Register a and B (OCRA and OCRB)
387
Input Capture Register a through D (ICRA through ICRD)
388
Timer Interrupt Enabling Register (TIER)
390
Timer Control/Status Register X (TCSRX)
393
Timer Control Register X (TCRX)
397
Timer Output Comparing Control Register (TOCR)
399
Module Stop Control Register (MSTPCR)
402
Operation
403
Operation of the Timer X1
403
Counting Timing of the FRC
404
Output Comparing Signal Outputting Timing
405
FRC Clearing Timing
405
Input Capture Signal Inputting Timing
406
Input Capture Flag (ICFA through ICFD) Setting up Timing
407
Output Comparing Flag (OCFA and OCFB) Setting up Timing
408
Overflow Flag (CVF) Setting up Timing
408
Operation Mode of the Timer X1
409
Interrupt Causes
410
Exemplary Uses of the Timer X1
411
Precautions When Using the Timer X1
412
Competition between Writing and Clearing with the FRC
412
Competition between Writing and Counting up with the FRC
413
Competition between Writing and Comparing Match with the OCR
414
Changing over the Internal Clocks and Counter Operations
415
Section 18 Watchdog Timer (WDT)
418
Overview
418
Features
418
Block Diagram
419
Register Configuration
420
Register Descriptions
421
Watchdog Timer Counter (WTCNT)
421
Watchdog Timer Control/Status Register (WTCSR)
421
System Control Register (SYSCR)
424
Notes on Register Access
424
Operation
426
Watchdog Timer Operation
426
Interval Timer Operation
427
Timing of Setting of Overflow Flag (OVF)
428
Interrupts
429
Usage Notes
429
Contention between Watchdog Timer Counter (WTCNT) Write and Increment
429
Changing Value of CKS2 to CKS0
430
Switching between Watchdog Timer Mode and Interval Timer Mode
430
Section 19 8-Bit PWM
432
Overview
432
Features
432
Block Diagram
432
Pin Configuration
433
Register Configuration
433
Register Descriptions
434
Bit PWM Data Registers 0, 1, 2 and 3 (PWR0, PWR1, PWR2, PWR3)
434
8-Bit PWM Control Register (PW8CR)
435
Port Mode Register 3 (PMR3)
436
Module Stop Control Register (MSTPCR)
437
8-Bit PWM Operation
438
Section 20 12-Bit PWM
440
Overview
440
Features
440
Block Diagram
441
Pin Configuration
442
Register Configuration
442
Register Descriptions
443
12-Bit PWM Control Registers (CPWCR, DPWCR)
443
12-Bit PWM Data Registers (CPWDR, DPWDR)
446
Module Stop Control Register (MSTPCR)
447
Operation
448
Output Waveform
448
Section 21 14-Bit PWM
450
Overview
450
Features
450
Block Diagram
451
Pin Configuration
451
Register Configuration
452
Register Descriptions
453
PWM Control Register (PWCR)
453
PWM Data Registers U and L (PWDRU, PWDRL)
454
Module Stop Control Register (MSTPCR)
455
14-Bit PWM Operation
456
Section 22 Prescalar Unit
458
Overview
458
Features
458
Block Diagram
459
Pin Configuration
460
Register Configuration
460
Registers
461
Input Capture Register 1 (ICR1)
461
Prescalar Unit Control/Status Register (PCSR)
461
Port Mode Register 1 (PMR1)
464
Noise Cancel Circuit
464
Operation
465
Prescalar S (PSS)
465
Prescalar W (PSW)
466
Stable Oscillation Wait Time Count
466
8-Bit PWM
467
8-Bit Input Capture Using IC Pin
467
Frequency Division Clock Output
467
Section 23 Serial Communication Interface 1 (SCI1)
468
Overview
468
Features
468
Block Diagram
470
Pin Configuration
471
Register Configuration
471
Register Descriptions
472
Receive Shift Register (RSR)
472
Receive Data Register (RDR1)
472
Transmit Shift Register (TSR)
473
Transmit Data Register (TDR1)
473
Serial Mode Register (SMR1)
474
Serial Control Register (SCR1)
477
Serial Status Register (SSR1)
480
Bit Rate Register (BRR1)
484
Serial Interface Mode Register (SCMR1)
491
Module Stop Control Register (MSTPCR)
492
Operation
493
Overview
493
Operation in Asynchronous Mode
495
Multiprocessor Communication Function
505
Operation in Clock Synchronous Mode
513
SCI1 Interrupts
521
Usage Notes
522
Section 24 Serial Communication Interface 2 (SCI2)
526
Overview
526
Features
526
Block Diagram
527
Pin Configuration
528
Register Configuration
528
Register Descriptions
529
Starting Address Register (STAR)
529
Ending Address Register (EDAR)
529
Serial Control Register 2 (SCR2)
530
Serial Control Status Register 2 (SCSR2)
531
Module Stop Control Register (MSTPCR)
534
Operation
535
Clock
535
Data Transfer Format
535
Data Transfer Operations
538
Interrupt Sources
542
Section 25 I C Bus Interface (IIC)
544
Overview
544
Features
544
Block Diagram
545
Pin Configuration
546
Register Configuration
547
Register Descriptions
548
C Bus Data Register (ICDR)
548
Slave Address Register (SAR)
551
Second Slave Address Register (SARX)
553
C Bus Mode Register (ICMR)
554
C Bus Control Register (ICCR)
558
C Bus Status Register (ICSR)
565
Serial/Timer Control Register (STCR)
570
Module Stop Control Register (MSTPCR)
572
Operation
573
C Bus Data Format
573
Master Transmit Operation
574
Master Receive Operation
577
Slave Receive Operation
580
Slave Transmit Operation
583
IRIC Setting Timing and SCL Control
585
Noise Canceler
587
Sample Flowcharts
587
Initialization of Internal State
592
Usage Notes
594
Section 26 A/D Converter
600
Overview
600
Features
600
Block Diagram
601
Pin Configuration
602
Register Configuration
603
Register Descriptions
604
Software-Triggered A/D Result Register (ADR)
604
Hardware-Triggered A/D Result Register (AHR)
604
A/D Control Register (ADCR)
606
A/D Control/Status Register (ADCSR)
609
Trigger Select Register (ADTSR)
612
Port Mode Register 0 (PMR0)
612
Module Stop Control Register (MSTPCR)
613
Interface to Bus Master
614
Operation
615
Software-Triggered A/D Conversion
615
Hardware- or External-Triggered A/D Conversion
616
Interrupt Sources
617
Section 27 Address Trap Controller (ATC)
618
Overview
618
Features
618
Block Diagram
618
Register Configuration
619
Register Descriptions
619
Address Trap Control Register (ATCR)
619
Trap Address Register 2 to 0 (TAR2 to TAR0)
620
Precautions in Usage
622
Basic Operations
622
Enable
624
Bcc Instruction
624
BSR Instruction
628
JSR Instruction
629
JMP Instruction
630
RTS Instruction
631
SLEEP Instruction
631
Competing Interrupt
634
Section 28 Servo Circuits
638
Overview
638
Functions
638
Block Diagram
639
Servo Port
641
Overview
641
Block Diagram
641
Pin Configuration
644
Register Configuration
645
Register Descriptions
645
DFG/DPG Input Signals
652
Reference Signal Generators
653
Overview
653
Block Diagram
653
Register Configuration
655
Register Descriptions
656
Description of Operation
662
HSW (Head-Switch) Timing Generator
677
Overview
677
Block Diagram
677
Composition
679
Register Configuration
680
Register Descriptions
680
Description of Operation
696
Interrupt
702
Cautions
703
Four-Head High-Speed Switching Circuit for Special Playback
704
Overview
704
Block Diagram
704
Pin Configuration
705
Register Description
705
Drum Speed Error Detector
708
Overview
708
Block Diagram
708
Register Configuration
710
Register Descriptions
711
Description of Operation
716
Correction in Trick Play Mode
718
Drum Phase Error Detector
719
Overview
719
Block Diagram
719
Register Configuration
721
Register Descriptions
722
Description of Operation
725
Phase Comparison
727
Capstan Speed Error Detector
728
Overview
728
Block Diagram
728
Register Configuration
730
Register Descriptions
731
Description of Operation
735
Capstan Phase Error Detector
737
Overview
737
Block Diagram
737
Register Configuration
739
Register Descriptions
740
Description of Operation
743
X-Value and Tracking Adjustment Circuit
745
28.10.1 Overview
745
Block Diagram
745
Register Descriptions
747
Digital Filters
750
28.11.1 Overview
750
Block Diagram
751
28.11.3 Arithmetic Buffer
753
Register Configuration
754
Register Descriptions
755
28.11.6 Filter Characteristics
763
28.11.7 Operations in Case of Transient Response
765
28.11.8 Initialization of Z
765
Additional V Signal Generator
767
28.12.1 Overview
767
Pin Configuration
768
Register Configuration
768
Register Description
768
28.12.5 Additional V Pulse Signal
770
CTL Circuit
773
28.13.1 Overview
773
Block Diagram
774
Pin Configuration
775
Register Configuration
775
Register Descriptions
776
Operation
790
28.13.7 CTL Input Section
793
Duty Discriminator
796
28.13.9 CTL Output Section
802
28.13.10 Trapezoid Waveform Circuit
805
28.13.11 Note on CTL Interrupt
806
Frequency Dividers
807
28.14.1 Overview
807
CTL Frequency Divider
807
28.14.3 CFG Frequency Divider
811
28.14.4 DFG Noise Removal Circuit
820
Sync Signal Detector
822
28.15.1 Overview
822
Block Diagram
823
Pin Configuration
824
Register Configuration
824
Register Descriptions
825
28.15.6 Noise Detection
833
28.15.7 Sync Signal Detector Activation
836
Servo Interrupt
837
28.16.1 Overview
837
Register Configuration
837
Register Description
837
Module Stop Control Reigster (MSTPCR)
844
Section 29 Electrical Characteristics
846
Absolute Maximum Ratings
846
Electrical Characteristics of HD64F2194
847
DC Characteristics of HD64F2194
847
Allowable Output Currents of HD64F2194, HD64F2194C
853
AC Characteristics of HD64F2194, HD64F2194C
854
Serial Interface Timing of HD64F2194, HD64F2194C
857
A/D Converter Characteristics of HD64F2194, HD64F2194C
862
Servo Section Electrical Characteristics of HD64F2194, HD64F2194C
863
FLASH Memory Characteristics
866
Usage Note
867
Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
868
DC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
868
Allowable Output Currents of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
874
AC Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
875
Serial Interface Timing of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
879
A/D Converter Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
884
Servo Section Electrical Characteristics of HD6432194, HD6432193, HD6432192, HD6432191, HD6432194C, HD6432194B, and HD6432194A
885
Appendix A Instruction Set
888
Instructions
888
Instruction Codes
899
Operation Code Map
909
Number of Execution States
913
Bus Status During Instruction Execution
923
Change of Condition Codes
932
Appendix B Internal I/O Registers
937
Addresses
937
Function List
944
Appendix C Pin Circuit Diagrams
1045
Pin Circuit Diagrams
1045
Appendix D Port States in the Difference Processing States
1059
Pin Circuit Diagrams
1059
Appendix E Usage Notes
1060
Power Supply Rise and Fall Order
1060
Pin Handling When the High-Speed Switching Circuit for Four-Head Special Playback Is Not Used
1061
Sample External Circuits
1062
Appendix F List of Product Codes
1063
Appendix G External Dimensions
1064
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