Contention Between Tcor Write And Compare Match - Renesas H8/3067 Series User Manual

10.7.3

Contention between TCOR Write and Compare Match

If a compare match occurs in the T
compare match signal is inhibited. Figure 10.20 shows the timing in this case.
φ
Address bus
Internal write signal
TCNT
TCOR
Compare match signal
Figure 10.20 Contention between TCOR Write and Compare Match
state of a TCOR write cycle, writing takes priority and the
3
TCOR write cycle
T T
1 2
TCOR address
N
N
Section 10 8-Bit Timers
T
3
N+1
M
TCOR write data
Rev. 4.00 Jan 26, 2006 page 427 of 938
Inhibited
REJ09B0276-0400