Conflict Between Tcnt Write And Increment; Conflict Between Tcor Write And Compare Match - Renesas H8SX/1650 Hardware Manual

11.8.3

Conflict between TCNT Write and Increment

If a TCNT input clock pulse is generated during the T
priority and the counter is not incremented as shown in figure 11.14.
P
Address
Internal write signal
TCNT input clock
TCNT
Figure 11.14 Conflict between TCNT Write and Increment
11.8.4

Conflict between TCOR Write and Compare Match

If a compare match event occurs during the T
priority and the compare match signal is inhibited as shown in figure 11.15.
P
Address
Internal write signal
TCNT
TCOR
Compare match signal
Figure 11.15 Conflict between TCOR Write and Compare Match
state of a TCNT write cycle, the write takes
2
TCNT write cycle by CPU
T T
1 2
TCNT address
N
Counter write data
state of a TCOR write cycle, the TCOR write takes
2
TCOR write cycle by CPU
T T
1 2
TCOR address
N
N
TCOR write data
Rev.2.00 Jun. 28, 2007 Page 433 of 666
Section 11 8-Bit Timers (TMR)
M
N + 1
M
Inhibited
REJ09B0311-0200