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Section 13 8-Bit Timer (TMR)
13.9.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T
TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR input
capture conflicts with a compare-match in the same way as with a write to TCORC. In this case
also, the input capture takes priority and the compare-match signal is disabled.
φ
Address
Internal write signal
TCNT
TCOR
Compare-match signal
Figure 13.15 Conflict between TCOR Write and Compare-Match
13.9.4
Conflict between Compare-Matches A and B
If compare-matches A and B occur at the same time, the operation follows the output status that is
defined for compare-match A or B, according to the priority of the timer output shown in table
13.7.
Table 13.7 Timer Output Priorities
Output Setting
Toggle output
1 output
0 output
No change
Rev. 1.00 Apr. 28, 2008 Page 386 of 994
REJ09B0452-0100
state of a TCOR write cycle as shown in figure 13.15, the
2
TCOR write cycle by CPU
T
T
1
2
TCOR address
N
N
TCOR write data
N + 1
M
Disabled
Priority
High
Low
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