Conflict Between Tcor Write And Compare-Match; Figure 13.16 Conflict Between Tcor Write And Compare-Match - Renesas H8S/2158 User Manual

13.9.3

Conflict between TCOR Write and Compare-Match

If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 13.16,
the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, a TICR
input capture conflicts with a compare-match in the same way as with a write to TCORC. In this
case also, the input capture takes priority and the compare-match signal is disabled.
φ
Address
Internal write signal
TCNT
TCOR
Compare-match signal

Figure 13.16 Conflict between TCOR Write and Compare-Match

TCOR write cycle by CPU
T 1 T 2
TCOR address
N
N
Rev. 3.00 Jan 25, 2006 page 341 of 872
Section 13 8-Bit Timer (TMR)
N + 1
M
TCOR write data
Disabled
REJ09B0286-0300