Renesas H8S/2319 series Hardware Manual
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Renesas H8S/2319 series Hardware Manual

Renesas H8S/2319 series Hardware Manual

Renesas 16-bit single-chip microcomputer
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Table of Contents

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H8S/2319
16
Rev.5.00
2003.12.15
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Renesas 16-Bit Single-Chip Microcomputer
, H8S/2318
Group
H8S Family/H8S/2300 Series
Group
Hardware Manual

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Summary of Contents for Renesas H8S/2319 series

  • Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2319 , H8S/2318 Group Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series Rev.5.00 2003.12.15...
  • Page 3 Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series H8S/2319 Group, H8S/2318 Group Hardware Manual REJ09B0089-0500O...
  • Page 4 Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp.
  • Page 5 General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
  • Page 6 Rev. 5.00, 12/03, page of xxx...
  • Page 7 This is particularly applicable to application devices with specifications that will most probably change. Note: * F-ZTAT is a trademark of Renesas Technology Corp. Target Users: This manual was written for users who will be using the H8S/2319 Group, H8S/2318 Group in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
  • Page 8 H8S/2319 Group, H8S/2318 Group manuals: Manual Title ADE No. H8S/2319 Group, H8S/2318 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 Users manuals for development tools: Manual Title ADE No. C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 Simulator Debugger (for Windows) Users Manual ADE-702-037...
  • Page 9 Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 1.3.1 Pin Arrangement Figure title amended Figure 1-2 Pin Arrangement (TFP- 100B, TFP-100G: Top View) 1.3.2 Pin Functions in 13 to 16 Table amended Each Operating Mode Pin No.

  • Page 10: Instruction Execution

    Item Page Revision (See Manual for Details) A.4 Number of States 895, 897, “Advanced” deleted from Mnemonic column Required for Instruction 901, 902 Instruc- Branch Stack Byte Word Internal tion Address Opera- Data Data Opera- Execution Fetch Read tion Access Access tion Instruction Mnemonic...
  • Page 11 Item Page Revision (See Manual for Details) Appendix E Product 1084 Table amended Lineup Product Type Model Marking Package (Package Code) Table E-1 H8S/2319 HD6432318 * H8S/2318 Mask ROM HD6432318TE 100-pin TQFP (TFP-100B) Series, H8S/2318 version Series Product Lineup HD6432318F 100-pin QFP (FP-100A) F-ZTAT HD64F2318...
  • Page 12 Rev. 5.00, 12/03, page xii of xxx...

  • Page 13: Table Of Contents

    Contents Section 1 Overview ......................Overview........................... Block Diagram ........................Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions in Each Operating Mode ............... 13 1.3.3 Pin Functions ....................... 17 Section 2 CPU ........................25 Overview........................... 25 2.1.1 Features........................ 25 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU ........
  • Page 14 Basic Timing........................64 2.9.1 Overview......................64 2.9.2 On-Chip Memory (ROM, RAM) ................. 64 2.9.3 On-Chip Supporting Module Access Timing............66 2.9.4 External Address Space Access Timing .............. 67 2.10 Usage Note........................67 2.10.1 TAS Instruction....................67 Section 3 MCU Operating Modes ..................
  • Page 15 Section 4 Exception Handling ..................99 Overview........................... 99 4.1.1 Exception Handling Types and Priority............... 99 4.1.2 Exception Handling Operation................99 4.1.3 Exception Vector Table ..................100 Reset ..........................102 4.2.1 Overview......................102 4.2.2 Reset Sequence ....................102 4.2.3 Interrupts after Reset.................... 103 4.2.4 State of On-Chip Supporting Modules after Reset Release .........
  • Page 16 DTC Activation by Interrupt..................... 136 5.6.1 Overview......................136 5.6.2 Block Diagram..................... 136 5.6.3 Operation ......................137 Section 6 Bus Controller ....................139 Overview........................... 139 6.1.1 Features........................ 139 6.1.2 Block Diagram..................... 140 6.1.3 Pin Configuration....................141 6.1.4 Register Configuration..................142 Register Descriptions ......................143 6.2.1 Bus Width Control Register (ABWCR)...............
  • Page 17 6.8.1 Overview......................180 6.8.2 Operation ......................180 6.8.3 Bus Transfer Timing .................... 181 6.8.4 External Bus Release Usage Note................ 181 Resets and the Bus Controller ................... 181 Section 7 Data Transfer Controller ................. 183 Overview........................... 183 7.1.1 Features........................ 183 7.1.2 Block Diagram.....................
  • Page 18 Port 2..........................232 8.3.1 Overview......................232 8.3.2 Register Configuration..................232 8.3.3 Pin Functions ....................... 234 Port 3..........................242 8.4.1 Overview......................242 8.4.2 Register Configuration..................242 8.4.3 Pin Functions ....................... 245 Port 4..........................247 8.5.1 Overview......................247 8.5.2 Register Configuration..................247 8.5.3 Pin Functions .......................
  • Page 19 8.12.2 Register Configuration..................288 8.12.3 Pin Functions ....................... 292 Section 9 16-Bit Timer Pulse Unit (TPU) ..............295 Overview........................... 295 9.1.1 Features........................ 295 9.1.2 Block Diagram..................... 299 9.1.3 Pin Configuration....................300 9.1.4 Register Configuration..................302 Register Descriptions ......................304 9.2.1 Timer Control Registers (TCR) ................
  • Page 20 Section 10 8-Bit Timers ..................... 383 10.1 Overview........................... 383 10.1.1 Features........................ 383 10.1.2 Block Diagram..................... 384 10.1.3 Pin Configuration....................385 10.1.4 Register Configuration..................385 10.2 Register Descriptions ......................386 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ............386 10.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ....... 386 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) ........
  • Page 21 11.3.1 Operation in Watchdog Timer Mode ..............415 11.3.2 Operation in Interval Timer Mode ............... 417 11.3.3 Timing of Overflow Flag (OVF) Setting ............. 417 11.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting......418 11.4 Interrupts ........................... 418 11.5 Usage Notes ........................418 11.5.1 Contention between Timer Counter (TCNT) Write and Increment .....
  • Page 22 13.2 Register Descriptions ......................491 13.2.1 Smart Card Mode Register (SCMR) ..............491 13.2.2 Serial Status Register (SSR) ................492 13.2.3 Serial Mode Register (SMR)................493 13.2.4 Serial Control Register (SCR)................495 13.3 Operation .......................... 496 13.3.1 Overview......................496 13.3.2 Pin Connections ....................496 13.3.3 Data Format ......................
  • Page 23 15.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) ............542 15.2.2 D/A Control Registers 01 (DACR01) ..............542 15.2.3 Module Stop Control Register (MSTPCR) ............544 15.3 Operation .......................... 545 Section 16 RAM ........................547 16.1 Overview........................... 547 16.1.1 Block Diagram..................... 547 16.1.2 Register Configuration..................
  • Page 24 17.7 Programming/Erasing Flash Memory ................583 17.7.1 Program Mode ..................... 583 17.7.2 Program-Verify Mode..................584 17.7.3 Erase Mode ......................586 17.7.4 Erase-Verify Mode....................586 17.8 Flash Memory Protection....................588 17.8.1 Hardware Protection .................... 588 17.8.2 Software Protection....................588 17.8.3 Error Protection....................589 17.9 Flash Memory Emulation in RAM ...................
  • Page 25 17.15.1 Boot Mode ......................631 17.15.2 User Program Mode..................... 636 17.16 Programming/Erasing Flash Memory ................638 17.16.1 Program Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for addresses H'040000 to H'07FFFF) ..........638 17.16.2 Program-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for addresses H'040000 to H'07FFFF) ..........
  • Page 26 17.23.2 Programming/Erasing Interface Parameter ............681 17.23.3 System Control Register 2 (SYSCR2) ..............693 17.23.4 RAM Emulation Register (RAMER)..............694 17.24 On-Board Programming Mode ..................696 17.24.1 Boot Mode ......................696 17.24.2 User Program Mode..................... 699 17.24.3 User Boot Mode....................710 17.25 Protection ..........................
  • Page 27 Section 19 Power-Down Modes ..................777 19.1 Overview........................... 777 19.1.1 Register Configuration..................778 19.2 Register Descriptions ......................779 19.2.1 Standby Control Register (SBYCR) ..............779 19.2.2 System Clock Control Register (SCKCR) ............781 19.2.3 Module Stop Control Register (MSTPCR) ............783 19.3 Medium-Speed Mode......................
  • Page 28 20.3.2 DC Characteristics ....................825 20.3.3 AC Characteristics ....................828 20.3.4 A/D Conversion Characteristics................832 20.3.5 D/A Conversion Characteristics................832 20.3.6 Flash Memory Characteristics ................833 20.4 Electrical Characteristics of F-ZTAT Version (H8S/2319C F-ZTAT) (In planning)........................835 20.4.1 Absolute Maximum Ratings ................835 20.4.2 DC Characteristics ....................
  • Page 29 Appendix D Pin States ..................... 1078 Port States in Each Mode ....................1078 Appendix E Product Lineup ................... 1084 Appendix F Package Dimensions ................. 1086 Rev. 5.00, 12/03, page xxix of xxx...
  • Page 30 Rev. 5.00, 12/03, page xxx of xxx...

  • Page 31: Section 1 Overview

    Overview The H8S/2319 Group and H8S/2318 Group are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas's proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
  • Page 32 Table 1-1 Overview Item Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 25 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 40 ns (at 25 MHz operation) 16 ×...
  • Page 33 Item Specification • 8-bit timer, 8-bit up-counter (external event count capability) 2 channels • Two time constant registers • Two-channel connection possible • Watchdog timer Watchdog timer or interval timer selectable • Serial Asynchronous mode or synchronous mode selectable communication •...
  • Page 34 Item Specification • Power-down state Medium-speed mode • Sleep mode • Module stop mode • Software standby mode • Hardware standby mode • Variable clock division ratio • Operating modes Eight MCU operating modes (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) External Data Bus Operating On-Chip...
  • Page 35 Item Specification • Operating modes Four MCU operating modes (ROMless, mask ROM versions, H8S/2319 F- ZTAT, and H8S/2319C F-ZTAT) External Data Bus Operating On-Chip Initial Maximum Mode Mode Description Value Value — — — — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode...
  • Page 36 Item Specification Condition C * Product lineup Condition A Condition B Operating power supply 2.7 to 3.6 V 3.0 to 3.6 V 2.4 to 3.6 V voltage Operating frequency 2 to 20 MHz 2 to 25 MHz 2 to 14 MHz Model HD64F2319 —...
  • Page 37 Item Specification • Other features Differences between H8S/2319 F-ZTAT and H8S/2319C F-ZTAT  On-chip RAM H8S/2319 F-ZTAT: 8 kbytes (H'FFDC00 to H'FFFBFF) H8S/2319C F-ZTAT: 16 kbytes (H'FFBC00 to H'FFFBFF)  On-chip flash memory The H8S/2319 F-ZTAT and H8S/2319C F-ZTAT both have 512 kbytes of on-chip flash memory.

  • Page 38: Block Diagram

    Block Diagram Port D Port E PA3/A19 PA2/A18 Port EXTAL PA1/A17 XTAL PA0/A16 STBY H8S/2000 CPU WDTOVF (FWE, EMLE, V PB7/A15 PB6/A14 PB5/A13 PB4/A12 Port Interrupt controller PB3/ A11 PB2/A10 PB1/A9 PF7/φ PB0/A8 PF6/AS ROM * PC7/A7 PF5/RD PC6/A6 PF4/HWR Port PC5/A5 PF3/LWR/IRQ3...

  • Page 39: Pin Description

    Pin Description 1.3.1 Pin Arrangement PF0/BREQ/IRQ0/CS4 PA0/A16 PB7/A15 P40/AN0 PB6/A14 P41/AN1 PB5/A13 P42/AN2 PB4/A12 P43/AN3 PB3/A11 P44/AN4 PB2/A10 P45/AN5 PB1/A9 P46/AN6/DA0 PB0/A8 P47/AN7/DA1 PC7/A7 PC6/A6 P24/TIOCA4/TMRI1 PC5/A5 P25/TIOCB4/TMCI1 PC4/A4 P26/TIOCA5/TMO0 PC3/A3 P27/TIOCB5/TMO1 PC2/A2 PG0/ADTRG/IRQ6 PC1/A1 PG1/CS3/IRQ7/CS6 PC0/A0 PG2/CS2 PG3/CS1/CS7 PD7/D15 PG4/CS0 PD6/D14 PD5/D13...
  • Page 40 P40/AN0 PB7/A15 P41/AN1 PB6/A14 P42/AN2 PB5/A13 P43/AN3 PB4/A12 P44/AN4 PB3/A11 P45/AN5 PB2/A10 P46/AN6/DA0 PB1/A9 P47/AN7/DA1 PB0/A8 PC7/A7 P24/TIOCA4/TMRI1 PC6/A6 P25/TIOCB4/TMCI1 PC5/A5 P26/TIOCA5/TMO0 PC4/A4 P27/TIOCB5/TMO1 PC3/A3 PG0/ADTRG/IRQ6 PC2/A2 PG1/CS3/IRQ7/CS6 PC1/A1 PG2/CS2 PC0/A0 PG3/CS1/CS7 PG4/CS0 PD7/D15 PD6/D14 Note: * The FWE pin function is only available in the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT.
  • Page 41 E10-A compatible version PF0/BREQ/IRQ0/CS4 PA0/A16 PB7/A15 P40/AN0 PB6/A14 P41/AN1 PB5/A13 P42/AN2 PB4/A12 P43/AN3 PB3/A11 P44/AN4 PB2/A10 P45/AN5 PB1/A9 P46/AN6/DA0 PB0/A8 P47/AN7/DA1 PC7/A7 PC6/A6 P24/TIOCA4/TMRI1 PC5/A5 P25/TIOCB4/TMCI1 PC4/A4 P26/TIOCA5/TMO0 PC3/A3 P27/TIOCB5/TMO1 PC2/A2 PG0/ADTRG/IRQ6 PC1/A1 PG1/CS3/IRQ7/CS6 PC0/A0 PG2/CS2 PG3/CS1/CS7 PD7/D15 PG4/CS0 PD6/D14 PD5/D13 P10/TIOCA0/A20 PD4/D12...
  • Page 42 E10-A compatible version P40/AN0 PB7/A15 P41/AN1 PB6/A14 P42/AN2 PB5/A13 P43/AN3 PB4/A12 P44/AN4 PB3/A11 P45/AN5 PB2/A10 P46/AN6/DA0 PB1/A9 P47/AN7/DA1 PB0/A8 PC7/A7 P24/TIOCA4/TMRI1 PC6/A6 P25/TIOCB4/TMCI1 PC5/A5 P26/TIOCA5/TMO0 PC4/A4 P27/TIOCB5/TMO1 PC3/A3 PG0/ADTRG/IRQ6 PC2/A2 PG1/CS3/IRQ7/CS6 PC1/A1 PG2/CS2 PC0/A0 PG3/CS1/CS7 PG4/CS0 PD7/D15 PD6/D14 Note: * If an E10-A emulator is used, the TDO, TDI, TDK, TMS, and TRST pins are used exclusively for the H-UDI and the functions and function modules associated with these pins are not available.

  • Page 43: Pin Functions In Each Operating Mode

    1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions in each of the operating modes. Table 1-2 Pin Functions in Each Operating Mode Pin No. Pin Name TFP-100B, Mode Mode Mode Mode Flash Memory TFP-100G FP-100A Programmer Mode P12/TIOCC0/ P12/TIOCC0/...
  • Page 44 Pin No. Pin Name TFP-100B, Mode Mode Mode Mode Flash Memory TFP-100G FP-100A Programmer Mode I/O3 I/O4 I/O5 I/O6 I/O7 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 P20/TIOCA3 P20/TIOCA3 P20/TIOCA3...
  • Page 45 Pin No. Pin Name TFP-100B, Mode Mode Mode Mode Flash Memory TFP-100G FP-100A Programmer Mode STBY STBY STBY STBY XTAL XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL EXTAL PF7/φ PF7/φ PF7/φ PF7/φ PF6/AS PF6/AS PF6/AS PF3/LWR/IRQ3 PF3/LWR/IRQ3 PF3/LWR/IRQ3 PF3/IRQ3 PF2/WAIT/ PF2/WAIT/ PF2/WAIT/...
  • Page 46 Pin No. Pin Name TFP-100B, Mode Mode Mode Mode Flash Memory TFP-100G FP-100A Programmer Mode P26/TIOCA5/ P26/TIOCA5/ P26/TIOCA5/ P26/TIOCA5/ TMO0 TMO0 TMO0 TMO0 P27/TIOCB5/ P27/TIOCB5/ P27/TIOCB5/ P27/TIOCB5/ TMO1 TMO1 TMO1 TMO1 PG0/IRQ6/ PG0/IRQ6/ PG0/IRQ6/ PG0/IRQ6/ ADTRG ADTRG ADTRG ADTRG PG1/CS3/ PG1/CS3/ PG1/CS3/ PG1/IRQ7...

  • Page 47: Pin Functions

    1.3.3 Pin Functions Table 1-3 Pin Functions Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function Power 40, 65, 42, 67, Input Power supply: For connection to the power supply. All V pins should be connected to the system power supply.
  • Page 48 Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function Operating mode MD2 to 61, 58, 63, 60, Input Mode pins: These pins set the control operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below.
  • Page 49 Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function • Operating mode MD2 to 61, 58, 63, 60, Input Mask ROM and ROMless control versions, H8S/2319 F-ZTAT, and H8S/2319C F-ZTAT Operating Mode Mode 1 * Mode 2 * Mode 2 * Mode 4 * Mode 5 *...
  • Page 50 Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function Interrupts Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. IRQ7 to 94, 93, 96, 95, Input Interrupt request 7 to 0: These pins IRQ0 13, 12, 15, 14,...
  • Page 51 Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function 16-bit timer- TCLKD to 6, 4, 2, 1 8, 6, 4, 3 Input Clock input D to A: These pins input pulse unit TCLKA an external clock. (TPU) TIOCA0, 99, 100, 1 to 4 Input capture/ output compare match...
  • Page 52 Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function Serial TxD1, 9, 8 11, 10 Output Transmit data (channel 0, 1): communication TxD0 Data output pins. interface (SCI) RxD1, 11, 10 13, 12 Input Receive data (channel 0, 1): Smart Card RxD0 Data input pins.
  • Page 53 Pin No. TFP-100B, Type Symbol TFP-100G FP-100A I/O Name and Function I/O ports P35 to 13 to 8 15 to 10 Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR).
  • Page 54 Rev. 5.00, 12/03, page 24 of 1088...

  • Page 55: Section 2 Cpu

    Section 2 CPU Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (4-Gbyte architecturally) linear address space, and is ideal for realtime control.

  • Page 56: Differences Between H8S/2600 Cpu And H8S/2000 Cpu

    • High-speed operation  All frequently-used instructions execute in one or two states  Maximum clock rate : 25 MHz  8/16/32-bit register-register add/subtract : 40 ns  8 × 8-bit register-register multiply : 480 ns  16 ÷ 8-bit register-register divide : 480 ns ...

  • Page 57: Differences From H8/300 Cpu

    2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers  Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded address space ...

  • Page 58: Cpu Operating Modes

    CPU Operating Modes The H8S/2319 Group and H8S/2318 Group CPUs have advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller.
  • Page 59 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-1). For details of the exception vector table, see section 4, Exception Handling.
  • Page 60 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-2. When EXR is invalid, it is not pushed onto the stack.

  • Page 61: Address Space

    Address Space Figure 2-3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (4-Gbyte architecturally) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2319 and H8S/2318 Groups...

  • Page 62: Register Configuration

    Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2-4. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) ER7 (SP) Control Registers (CR) 7 6 5 4 3 2 1 0 T ...

  • Page 63: General Registers

    2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

  • Page 64: Control Registers

    Free area SP (ER7) Stack area Figure 2-6 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute.

  • Page 65: Initial Register Values

    Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exception- handling sequence. For details, refer to section 5, Interrupt Controller. Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

  • Page 66: Data Formats

    The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data.
  • Page 67 Data Type Register Number Data Format Word data Word data Longword data Legend: ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-7 General Register Data Formats (cont) Rev.

  • Page 68: Memory Data Formats

    2.5.2 Memory Data Formats Figure 2-8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.

  • Page 69: Instruction Set

    Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Instruction Classification Function Instructions Size Types Data transfer POP * , PUSH * LDM, STM MOVFPE, MOVTPE * Arithmetic ADD, SUB, CMP, NEG operations...

  • Page 70: Instructions And Addressing Modes

    2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes Addressing Modes Function Instruction      Data transfer ...

  • Page 71: Table Of Instructions Classified By Function

    2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination) * General register (source) * General register * General register (32-bit register) (EAd) Destination operand (EAs)
  • Page 72 Table 2-3 Instructions Classified by Function Size * Type Instruction Function (EAs) → Rd, Rs → (Ead) Data transfer B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2357 Series.
  • Page 73 Size * Type Instruction Function Rd ± Rs → Rd, Rd ± #IMM → Rd Arithmetic B/W/L operations Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
  • Page 74 Size * Type Instruction Function Rd ÷ Rs → Rd Arithmetic DIVXS operations Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.
  • Page 75 Size * Type Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Logic B/W/L operations Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
  • Page 76 Size * Type Instruction Function 1 → (<bit-No.> of <EAd>) Bit- BSET manipulation Sets a specified bit in a general register or memory instructions operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
  • Page 77 Size * Type Instruction Function C ⊕ (<bit-No.> of <EAd>) → C Bit- BXOR manipulation Exclusive-ORs the carry flag with a specified bit in a instructions general register or memory operand and stores the result in the carry flag. C ⊕ ¬ (<bit-No.> of <EAd>) → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand...
  • Page 78 Type Instruction Size Function Branch — Branches to a specified relative address if a specified instructions condition is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
  • Page 79 Size * Type Instruction Function System control TRAPA — Starts trap-instruction exception handling. instructions — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR.
  • Page 80 Type Instruction Size Function if R4L ≠ 0 then Block data EEPMOV.B — Repeat @ER5+ → @ER6+ transfer R4L–1 → R4L instruction Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next;...

  • Page 81: Basic Instruction Formats

    2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2-9 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc.

  • Page 82: Addressing Modes And Effective Address Calculation

    Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
  • Page 83 (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register.
  • Page 84 (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number.

  • Page 85: Effective Address Calculation

    If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address (For further information, see section 2.5.2, Memory Data Formats).
  • Page 86 Table 2-6 Effective Address Calculation Rev. 5.00, 12/03, page 56 of 1088...
  • Page 87 Rev. 5.00, 12/03, page 57 of 1088...
  • Page 88 Rev. 5.00, 12/03, page 58 of 1088...

  • Page 89: Processing States

    Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-11 shows a diagram of the processing states. Figure 2-12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.

  • Page 90: Reset State

    End of bus request Bus request Program execution state End of bus SLEEP request instruction with request SLEEP SSBY = 0 instruction with SSBY = 1 Bus-released state Request for End of exception exception handling Sleep mode handling Interrupt request Exception-handling state External interrupt Software standby mode...

  • Page 91: Exception-Handling State

    2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions.
  • Page 92 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends.

  • Page 93: Program Execution State

    Advanced mode Reserved* (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Note: * Ignored when returning. Figure 2-13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master...

  • Page 94: Basic Timing

    (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained.
  • Page 95 Bus cycle φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2-14 On-Chip Memory Access Cycle Bus cycle φ Address bus Unchanged High High HWR, LWR High...

  • Page 96: On-Chip Supporting Module Access Timing

    2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-16 shows the access timing for the on-chip supporting modules. Figure 2-17 shows the pin states. Bus cycle φ...

  • Page 97: External Address Space Access Timing

    Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
  • Page 98 Rev. 5.00, 12/03, page 68 of 1088...

  • Page 99: Section 3 Mcu Operating Modes

    Section 3 MCU Operating Modes Overview 3.1.1 Operating Mode Selection (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT) The H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT have eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings.

  • Page 100: Operating Mode Selection (Mask Rom, Romless, H8S/2319 F-Ztat, And H8S/2319C F-Ztat)

    The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT actually access a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices.
  • Page 101 Table 3-2 MCU Operating Mode Selection (Mask ROM, ROMless versions, H8S/2319 F- ZTAT, and H8S/2319C F-ZTAT) External Data Bus Operating Operating On-Chip Initial Max. Mode MD2 MD1 MD0 Mode Description Value Value — — — — — Advanced Expanded mode with Disabled 16 bits 16 bits on-chip ROM disabled...

  • Page 102: Register Configuration

    Do not change the inputs at the mode pins during operation. 3.1.3 Register Configuration The H8S/2319 and H8S/2318 Groups have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and system control register 2 (SYSCR2) * that control the operation of the chip.

  • Page 103: System Control Register (Syscr)

    3.2.2 System Control Register (SYSCR) — — INTM1 INTM0 NMIEG LWROD — RAME Initial value : — Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller.

  • Page 104: System Control Register 2 (Syscr2) (F-Ztat Versions Only)

    Bit 0 RAME Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Versions Only) — — — — FLSHE — — — Initial value : — (R/W) * — — — —...

  • Page 105: Operating Mode Descriptions

    Bits 2 and 1—Reserved: These bits are always read as 0, and cannot be modified. Bit 0—Reserved: In the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT, this bit is always read as 0 and cannot be modified. In the H8S/2319 F-ZTAT or H8S/2319C F-ZTAT, this bit is reserved and should only be written with 0.

  • Page 106: Mode 5 (Expanded Mode With On-Chip Rom Disabled)

    3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins P13 to P10, ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals.

  • Page 107: Mode 10 (H8S/2318 F-Ztat, H8S/2317 F-Ztat, H8S/2315 F-Ztat, And H8S/2314 F-Ztat Only)

    3.3.9 Mode 10 (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT Only) This is a flash memory boot mode. For details, see section 17, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced expanded mode with on-chip ROM enabled.

  • Page 108: Memory Map In Each Operating Mode

    Table 3-4 Pin Functions in Each Mode Mode 1 * Mode 2 * Mode 3 * Mode 7 * Mode 6 * Mode 10 * Mode 11 * Mode 14 * Mode 15 * Port Mode 4 Mode 5 Port 1 P13 to P10 /T/A /T/A...
  • Page 109 Mode 2 Boot Mode Mode 3 Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *4 space area H'07FFFF H'080000 External address space H'FF7400 H'FF7400...
  • Page 110 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 External address On-chip ROM/ On-chip ROM/ space external address reserved...
  • Page 111 Mode 1 User Boot Mode Mode 2 Boot Mode Mode 3 Boot Mode (advanced single-chip (advanced expanded mode (advanced single-chip mode) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ On-chip ROM/ reserved external address...
  • Page 112 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ External address external address reserved *2 *4...
  • Page 113 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address H'010000 H'010000 space On-chip ROM/ On-chip ROM/ external address reserved *3 *5...
  • Page 114 Mode 10 Boot Mode Mode 11 Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *4 space area H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00...
  • Page 115 Mode 14 User Program Mode Mode 15 User Program Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *4 space area H'03FFFF H'040000 External address space...
  • Page 116 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address H'010000 H'010000 space On-chip ROM/ On-chip ROM/ external address reserved *2 *4...
  • Page 117 Mode 10 Boot Mode Mode 11 Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *4 space area H'020000 H'020000 Reserved area Reserved external address area...
  • Page 118 Mode 14 Boot Mode Mode 15 Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *4 space area H'020000 H'020000 Reserved area Reserved external address area...
  • Page 119 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address H'010000 H'010000 space Reserved area Reserved area external address space H'03FFFF...
  • Page 120 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 External address On-chip ROM/ On-chip ROM/ space external address reserved...
  • Page 121 Mode 10 Boot Mode Mode 11 Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *5 space area H'060000 H'060000 Reserved area Reserved area H'07FFFF H'080000...
  • Page 122 Mode 14 User Program Mode Mode 15 User Program Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *5 space area H'060000 H'060000 Reserved area Reserved area...
  • Page 123 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 External address On-chip ROM/ On-chip ROM/ space external address reserved...
  • Page 124 Mode 10 Boot Mode Mode 11 Boot Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *5 space area H'060000 H'060000 Reserved area Reserved area H'07FFFF H'080000...
  • Page 125 Mode 14 User Program Mode Mode 15 User Program Mode (advanced expanded mode (advanced single-chip with on-chip ROM enabled) mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ On-chip ROM/ external address reserved *2 *5 space area H'060000 H'060000 Reserved area Reserved area...
  • Page 126 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External address H'010000 H'010000 space Reserved area Reserved area external address space H'03FFFF...
  • Page 127 Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip with on-chip ROM disabled) with on-chip ROM enabled) mode) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'008000 H'008000 Reserved area Reserved area External address H'010000 H'010000 space...
  • Page 128 Rev. 5.00, 12/03, page 98 of 1088...

  • Page 129: Section 4 Exception Handling

    Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.

  • Page 130: Exception Vector Table

    For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. ·...
  • Page 131 Table 4-2 Exception Vector Table Vector Address * Exception Source Vector Number Advanced Mode Reset H'0000 to H'0003 Reserved H'0004 to H'0007 Reserved for system use H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Reserved for system use H'0018 to H'001B External interrupt H'001C to H'001F...

  • Page 132: Reset

    Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set.

  • Page 133: Interrupts After Reset

    Internal Prefetch of first Vector fetch processing program instruction φ Address bus High HWR, LWR to D (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception vector address) Start address ((5) = (2), (4)) First program instruction Note: * 3 program wait states are inserted.

  • Page 134: Traces

    Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.

  • Page 135: Interrupts

    Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 43 internal sources in the on-chip supporting modules. Figure 4-3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), and A/D converter.

  • Page 136: Trap Instruction

    Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.

  • Page 137: Notes On Use Of The Stack

    Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W (or MOV.W Rn, @-SP)
  • Page 138 Rev. 5.00, 12/03, page 108 of 1088...

  • Page 139: Section 5 Interrupt Controller

    Section 5 Interrupt Controller Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. The available interrupt sources are external interrupts (NMI, IRQ7 to IRQ0) and internal interrupts (43 sources). •...

  • Page 140: Block Diagram

    5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to TEI Interrupt controller Legend:...

  • Page 141: Pin Configuration

    5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ7 to IRQ0 Input External interrupt Maskable external interrupts; rising, falling, or requests 7 to 0 both edges, or level sensing, can be selected 5.1.4...

  • Page 142: Register Descriptions

    Register Descriptions 5.2.1 System Control Register (SYSCR) — — INTM1 INTM0 NMIEG LWROD — RAME Initial value : — SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3, MCU Operating Modes.

  • Page 143: Interrupt Priority Registers A To K (Ipra To Iprk)

    5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : — — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5-3.

  • Page 144: Irq Enable Register (Ier)

    As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.

  • Page 145: Irq Sense Control Registers H And L (Iscrh, Iscrl)

    5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : ISCR (composed of ISCRH and ISCRL) is a 16-bit readable/writable register that selects rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.

  • Page 146: Irq Status Register (Isr)

    5.2.5 IRQ Status Register (ISR) IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests.

  • Page 147: Interrupt Sources

    Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.) NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits.

  • Page 148: Internal Interrupts

    Figure 5-3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
  • Page 149 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Vector Vector Address * IPR Interrupt Source Source Number Priority Activation Power-on reset H'0000 — High — Reserved H'0004 Reserved for system H'0008 H'000C H'0010 Trace H'0014 Reserved for system H'0018 External pin H'001C...
  • Page 150 Origin of Interrupt Vector Vector Address * IPR Interrupt Source Source Number Priority Activation SWDTEND (software- H'0060 IPRC2 to High activated data transfer IPRC0 end) WOVI (interval timer) Watchdog timer 25 H'0064 IPRD6 to — IPRD4 Reserved — H'0068 IPRD2 to —...
  • Page 151 Origin of Interrupt Vector Vector Address * IPR Interrupt Source Source Number Priority Activation TGI1A (TGR1A input H'00A0 IPRF2 to High capture/compare channel 1 IPRF0 match) TGI1B (TGR1B input H'00A4 capture/compare match) TCI1V (overflow 1) H'00A8 — TCI1U (underflow 1) H'00AC —...
  • Page 152 Origin of Interrupt Vector Vector Address * IPR Interrupt Source Source Number Priority Activation TGI4A (TGR4A input H'00E0 IPRH6 to High capture/compare channel 4 IPRH4 match) TGI4B (TGR4B input H'00E4 capture/compare match) TCI4V (overflow 4) H'00E8 — TCI4U (underflow 4) H'00EC —...
  • Page 153 Origin of Interrupt Vector Vector Address * IPR Interrupt Source Source Number Priority Activation Reserved — H'0120 IPRJ6 to High — IPRJ4 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C ERI0 (receive error 0) H'0140 IPRJ2 to — channel 0 IPRJ0 RXI0 (receive-data-full H'0144 TXI0 (transmit-data-...

  • Page 154: Interrupt Operation

    Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
  • Page 155 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
  • Page 156 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level.

  • Page 157: Interrupt Control Mode 0

    5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
  • Page 158 Program execution state Interrupt generated? NMI? I = 0? Hold pending IRQ0? IRQ1? TEI1? Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.

  • Page 159: Interrupt Control Mode 2

    5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
  • Page 160 Program execution state Interrupt generated? NMI? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine...

  • Page 161: Interrupt Exception Handling Sequence

    5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev.
  • Page 162 Figure 5-7 Interrupt Exception Handling Rev. 5.00, 12/03, page 132 of 1088...

  • Page 163: Interrupt Response Times

    5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5-9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.

  • Page 164: Usage Notes

    Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.

  • Page 165: Instructions That Disable Interrupts

    5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.

  • Page 166: Dtc Activation By Interrupt

    DTC Activation by Interrupt 5.6.1 Overview The DTC can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC, see section 7, Data Transfer Controller.

  • Page 167: Operation

    5.6.3 Operation The interrupt controller has three main functions in DTC control. Selection of Interrupt Source: For interrupt sources, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCERA to DTCERE in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
  • Page 168 Rev. 5.00, 12/03, page 138 of 1088...

  • Page 169: Section 6 Bus Controller

    Section 6 Bus Controller Overview The chip has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU and data transfer controller (DTC).

  • Page 170: Block Diagram

    6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Internal control BREQO controller signals Bus mode signal Wait WAIT controller WCRH...

  • Page 171: Pin Configuration

    6.1.3 Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Bus Controller Pins Name Symbol I/O Function Address strobe Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.

  • Page 172: Register Configuration

    6.1.4 Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Initial Value Address * Name Abbreviation Reset H'FF/H'00 * Bus width control register ABWCR H'FED0 Access state control register ASTCR H'FF H'FED1 Wait control register H WCRH H'FF H'FED2...

  • Page 173: Register Descriptions

    Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.

  • Page 174: Access State Control Register (Astcr)

    6.2.2 Access State Control Register (ASTCR) AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.

  • Page 175: Wait Control Registers H And L (Wcrh, Wcrl)

    6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode.
  • Page 176 Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...
  • Page 177 WCRL Initial value : Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.

  • Page 178: Bus Control Register H (Bcrh)

    Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
  • Page 179 Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted...

  • Page 180: Bus Control Register L (Bcrl)

    Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description Max. 4 words in burst access (Initial value) Max. 8 words in burst access Bits 2 to 0—Reserved: Only 0 should be written to these bits.
  • Page 181 Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF * to be internal addresses or external addresses. Description H8S/2319, H8S/2319C, Bit 5 H8S/2318, H8S/2315, H8S/2316, H8S/2313, H8S/2314 H8S/2317 H8S/2311 Reserved area * On-chip ROM Addresses H'010000 to H'01FFFF are on-chip ROM and addresses H'020000 to H'03FFFF are reserved area * Addresses H'010000 to H'03FFFF *...

  • Page 182: Overview Of Bus Control

    Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6-2 shows an outline of the area partitioning.

  • Page 183: Bus Specifications

    6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.

  • Page 184: Memory Interfaces

    Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWCR ASTCR Program Wait ABWn ASTn Bus Width Access States States — — — — 6.3.3 Memory Interfaces The chip’s memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on;...

  • Page 185: Advanced Mode

    6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (sections 6.4, Basic Bus Interface, 6.5, Burst ROM Interface) should be referred to for further details.

  • Page 186: Chip Select Signals

    6.3.5 Chip Select Signals The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6-3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin.

  • Page 187: Basic Bus Interface

    Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
  • Page 188 16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D to D ) and lower data bus (D to D ) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.

  • Page 189: Valid Strobes

    6.4.3 Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.

  • Page 190: Basic Timing

    6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D to D ) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle φ...
  • Page 191 8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D to D ) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle φ...
  • Page 192 16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D to D ) of the data bus is used for the even address, and the lower half (D to D ) for the odd address.
  • Page 193 Bus cycle φ Address bus to D Read Invalid to D Valid High Write High impedance to D to D Valid Note: n = 0 to 7 Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.
  • Page 194 Bus cycle φ Address bus to D Read Valid to D Valid Write to D Valid to D Valid Note: n = 0 to 7 Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev. 5.00, 12/03, page 164 of 1088...
  • Page 195 16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D to D ) of the data bus is used for the even address, and the lower half (D to D ) for the odd address.
  • Page 196 Bus cycle φ Address bus to D Invalid Read to D Valid High Write High impedance to D to D Valid Note: n = 0 to 7 Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.
  • Page 197 Bus cycle φ Address bus to D Valid Read to D Valid Write to D Valid to D Valid Note: n = 0 to 7 Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev. 5.00, 12/03, page 167 of 1088...

  • Page 198: Wait Control

    6.4.5 Wait Control When accessing external space, the H8S/2319 and H8S/2318 Groups can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T state and T state on an individual area basis in 3-state access space, according to the settings of...
  • Page 199 Figure 6-14 shows an example of wait state insertion timing. By WAIT pin By program wait φ WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data indicates the timing of WAIT pin sampling. Note: Figure 6-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled.

  • Page 200: Burst Rom Interface

    Burst ROM Interface 6.5.1 Overview With the chip, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH.
  • Page 201 Full access Burst access φ Only lower address changed Address bus Data bus Read data Read data Read data Figure 6-15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev. 5.00, 12/03, page 171 of 1088...

  • Page 202: Wait Control

    Full access Burst access φ Only lower address changed Address bus Data bus Read data Read data Read data Figure 6-15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.

  • Page 203: Idle Cycle

    Idle Cycle 6.6.1 Operation When the chip accesses external space, it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high- speed memory, I/O interfaces, and so on.
  • Page 204 Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6-17 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
  • Page 205 CS) Signal and Read (RD RD) Signal: Depending on the Relationship between Chip Select (CS system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6-18. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.

  • Page 206: Pin States In Idle Cycle

    6.6.2 Pin States in Idle Cycle Table 6-5 shows the pin states in an idle cycle. Table 6-5 Pin States in Idle Cycle Pins Pin State to A Contents of next bus cycle to D High impedance CSn * High High High High...

  • Page 207: Bus Release

    Bus Release 6.7.1 Overview The chip can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access.

  • Page 208: Pin States In External Bus Released State

    6.7.3 Pin States in External Bus Released State Table 6-6 shows the pin states in the external bus released state. Table 6-6 Pin States in Bus Released State Pins Pin State to A High impedance to D High impedance CSn * High impedance High impedance High impedance...

  • Page 209: Transition Timing

    6.7.4 Transition Timing Figure 6-19 shows the timing for transition to the bus released state. cycle CPU cycle External bus released state φ High impedance Address bus Address High impedance Data bus High impedance High impedance High impedance HWR, LWR BREQ BACK BREQO *...

  • Page 210: Usage Note

    6.7.5 Usage Note Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a transition is made to sleep mode when either of these settings has been made. Bus Arbitration 6.8.1 Overview The chip has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU and DTC, which perform read/write operations when they have possession of the bus.

  • Page 211: Bus Transfer Timing

    6.8.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately.
  • Page 212 Rev. 5.00, 12/03, page 182 of 1088...

  • Page 213: Section 7 Data Transfer Controller

    Section 7 Data Transfer Controller Overview The chip includes a data transfer controller (DTC). The DTC can be activated for data transfer by an interrupt or software. 7.1.1 Features The features of the DTC are: • Transfer possible over any number of channels ...

  • Page 214: Block Diagram

    7.1.2 Block Diagram Figure 7-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM * . A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register information.

  • Page 215: Register Configuration

    7.1.3 Register Configuration Table 7-1 summarizes the DTC registers. Table 7-1 DTC Registers Address * Name Abbreviation Initial Value — * — * DTC mode register A Undefined — * — * DTC mode register B Undefined — * — * DTC source address register Undefined —...

  • Page 216: Register Descriptions

    Register Descriptions 7.2.1 DTC Mode Register A (MRA) Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.

  • Page 217: Dtc Mode Register B (Mrb)

    Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
  • Page 218 Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed.

  • Page 219: Dtc Source Address Register (Sar)

    7.2.3 DTC Source Address Register (SAR) – – – – – – Initial value : – – – Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined — — —...

  • Page 220: Dtc Transfer Count Register B (Crb)

    7.2.6 DTC Transfer Count Register B (CRB) Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined —...

  • Page 221: Dtc Vector Register (Dtvecr)

    For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions such as BSET and BCLR. For the initial setting only, however, when multiple activation sources are set at one time, it is possible to disable interrupts and write after executing a dummy read on the relevant register.

  • Page 222: Module Stop Control Register (Mstpcr)

    7.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, DTC operation stops at the end of the bus cycle and a transition is made to module stop mode.
  • Page 223 Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? CHNS = 0? Transfer counter = 0 or DISEL = 1? Transfer counter = 0? DISEL = 1? Clear activation flag Clear DTCER Interrupt exception handling Figure 7-2 Flowchart of DTC Operation...
  • Page 224 Table 7-2 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CHNE CHNS DISEL DTC Transfer — Not 0 — — — — Ends at 1st transfer — — — — — Ends at 1st transfer — — — —...
  • Page 225 Table 7-3 DTC Functions Address Registers Transfer Transfer Transfer Mode Activation Source Source Destination • • 24 bits 24 bits Normal mode  One transfer request transfers one byte • TPU TGI • or one word 8-bit timer CMI  Memory addresses are incremented •...

  • Page 226: Activation Sources

    7.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.

  • Page 227: Dtc Vector Table

    Source flag clearance Clear control Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Interrupt controller DTVECR Interrupt mask Figure 7-3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect.
  • Page 228 Table 7-5 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector DTCE * Interrupt Source Source Number Address Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0]<<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424...
  • Page 229 Origin of Interrupt Vector Vector DTCE * Interrupt Source Source Number Address Priority TGI3A (GR3A compare match/ TPU channel 3 H'0460 DTCEC5 High input capture) TGI3B (GR3B compare match/ H'0462 DTCEC4 input capture) TGI3C (GR3C compare match/ H'0464 DTCEC3 input capture) TGI3D (GR3D compare match/ H'0466 DTCEC2...

  • Page 230: Location Of Register Information In Address Space

    DTC vector Register information Register information address start address Next transfer Figure 7-4 Correspondence between DTC Vector Address and Register Information 7.3.4 Location of Register Information in Address Space Figure 7-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address).

  • Page 231: Normal Mode

    7.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 7-6 lists the register information in normal mode and figure 7-6 shows the memory map in normal mode.

  • Page 232: Repeat Mode

    7.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.

  • Page 233: Block Transfer Mode

    7.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
  • Page 234 First block SAR or DAR or Block area Transfer Nth block Figure 7-8 Memory Map in Block Transfer Mode Rev. 5.00, 12/03, page 204 of 1088...

  • Page 235: Chain Transfer

    7.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.

  • Page 236: Operation Timing

    7.3.9 Operation Timing Figures 7-10 to 7-12 show examples of DTC operation timing. φ DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 7-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ...

  • Page 237: Number Of Dtc Execution States

    φ DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 7-12 DTC Operation Timing (Example of Chain Transfer) 7.3.10 Number of DTC Execution States Table 7-9 lists execution phases for a single DTC data transfer, and table 7-10 shows the number of states required for each execution phase.
  • Page 238 Table 7-10 Number of States Required for Each Execution Phase Chip Chip Internal I/O Access To: Registers External Devices Bus width Access states Execution Vector read — — — 6+2m 2 phase Register — — — — — — — information read/write Byte data read...

  • Page 239: Procedures For Using Dtc

    7.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1.

  • Page 240: Examples Of Use Of The Dtc

    7.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
  • Page 241 Chain Transfer when Counter = 0: By executing a second data transfer, and performing re- setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000.
  • Page 242 Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data Upper 8 bits transfer register of DAR information Figure 7-13 Chain Transfer when Counter = 0 Rev. 5.00, 12/03, page 212 of 1088...
  • Page 243 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).

  • Page 244: Interrupts

    Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.

  • Page 245: Section 8 I/O Ports

    Section 8 I/O Ports Overview The H8S/2319 and H8S/2318 Groups have 10 I/O ports (ports 1, 2, 3, and A to G), and one input- only port (port 4). Table 8-1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only ports), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
  • Page 246 Table 8-1 Port Functions Mode Mode Mode Mode Port Description Pins Port 1 • 8-bit I/O port P17/TIOCB2/TCLKD 8-bit I/O port also functioning as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, P16/TIOCA2 • Schmitt- TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) P15/TIOCB1/TCLKC triggered input P14/TIOCA1...
  • Page 247 Mode Mode Mode Mode Port Description Pins Port 4 • 8-bit input port P47/AN7/DA1 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs P46/AN6/DA0 (DA1 and DA0) P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Port A •...
  • Page 248 Mode Mode Mode Mode Port Description Pins Port E • 8-bit I/O port PE7/D7 to PE0/D0 In 8-bit bus mode: I/O port I/O port • Built-in MOS In 16-bit bus mode: data bus input/output input pull-up Port F • 8-bit I/O port PF7/φ...
  • Page 249 Mode Mode Mode Mode Port Description Pins When DDR = 0 * Port G • 5-bit I/O port PG4/CS0 : input port I/O port also functions as : CS0 output When DDR = 1 * • Schmitt- interrupt triggered input PG3/CS1/CS7 I/O port input pins...

  • Page 250: Port 1

    Port 1 8.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2) and an address bus output function. Port 1 pin functions change according to the operating mode. The address output or port output function is selected according to the settings of bits A23E to A20E in PFCR1.

  • Page 251: Register Configuration

    8.2.2 Register Configuration Table 8-2 shows the port 1 register configuration. Table 8-2 Port 1 Registers Address * Name Abbreviation Initial Value Port 1 data direction register P1DDR H'00 H'FEB0 Port 1 data register P1DR H'00 H'FF60 Port 1 register PORT1 Undefined H'FF50...
  • Page 252 P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode. Port 1 Register (PORT1) — * — * — * — * — * — * — * —...

  • Page 253: Pin Functions

    Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23). This bit is valid in modes 4 to 6. Bit 3 A23E Description P13DR is output when P13DDR = 1 A23 is output when P13DDR = 1 (Initial value) Bit 2—Address 22 Enable (A22E): Enables or disables address output 22 (A22).
  • Page 254 Table 8-3 Port 1 Pin Functions Selection Method and Pin Functions P17/TIOCB2/ The pin function is switched as shown below according to the combination of TCLKD the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bits TPSC2 to TPSC0 in TCR0 and TCR5, and bit P17DDR.
  • Page 255 Selection Method and Pin Functions P16/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, and bit P16DDR. TPU Channel 2 Setting Table Below (1)
  • Page 256 Selection Method and Pin Functions P15/TIOCB1/ The pin function is switched as shown below according to the combination of TCLKC the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, and bit P15DDR.
  • Page 257 Selection Method and Pin Functions P14/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, and bit P14DDR. TPU Channel 1 Setting Table Below (1)
  • Page 258 Selection Method and Pin Functions P13/TIOCD0/ The pin function is switched as shown below according to the combination of TCLKB/A23 the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit A23E in PFCR1, and bit P13DDR.
  • Page 259 Selection Method and Pin Functions P12/TIOCC0/ The pin function is switched as shown below according to the combination of TCLKA/A22 the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit A22E in PFCR1 and bit P12DDR.
  • Page 260 Selection Method and Pin Functions P11/TIOCB0/ The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit A21E in PFCR1 and bit P11DDR.
  • Page 261 Selection Method and Pin Functions P10/TIOCA0/ The pin function is switched as shown below according to the combination of the operating mode, TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit A20E in PFCR1 and bit P10DDR.

  • Page 262: Port 2

    Port 2 8.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input.
  • Page 263 Port 2 Data Direction Register (P2DDR) P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting P2DDR bits to 1 makes the corresponding port 2 pins output pins, while clearing the bits to 0 makes the pins input pins.

  • Page 264: Pin Functions

    After a reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state after in software standby mode. 8.3.3 Pin Functions Port 2 pins also function as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1).
  • Page 265 Selection Method and Pin Functions P26/TIOCA5/ The pin function is switched as shown below according to the combination of TMO0 the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bits OS3 to OS0 in TCSR0, and bit P26DDR.
  • Page 266 Selection Method and Pin Functions P25/TIOCB4/ This pin is used as the 8-bit timer external clock input pin when external clock TMCI1 is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P25DDR.
  • Page 267 Selection Method and Pin Functions P24/TIOCA4/ This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and TMRI1 CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, and bit P24DDR.
  • Page 268 Selection Method and Pin Functions P23/TIOCD3/ This pin is used as the 8-bit timer external clock input pin when external clock TMCI0 is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P23DDR.
  • Page 269 Selection Method and Pin Functions P22/TIOCC3/ This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and TMRI0 CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, and bit P22DDR.
  • Page 270 Selection Method and Pin Functions P21/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P21DDR. TPU Channel 3 Setting Table Below (1)
  • Page 271 Selection Method and Pin Functions P20/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, and bit P20DDR. TPU Channel 3 Setting Table Below (1)

  • Page 272: Port 3

    Port 3 8.4.1 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are the same in all operating modes.
  • Page 273 Port 3 Data Direction Register (P3DDR) — — P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : Undefined Undefined — — P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read.
  • Page 274 Port 3 Register (PORT3) — — — * — * — * — * — * — * Initial value : Undefined Undefined — — Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states, and cannot be modified. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR.

  • Page 275: Pin Functions

    8.4.3 Pin Functions Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and interrupt input pins (IRQ4, IRQ5). Port 3 pin functions are shown in table 8-7. Table 8-7 Port 3 Pin Functions Selection Method and Pin Functions P35/SCK1/IRQ5 The pin function is switched as shown below according to the combination of...
  • Page 276 Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. P33DDR — P33 output pin * Pin function P33 input pin RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output.

  • Page 277: Port 4

    Port 4 8.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes.

  • Page 278: Pin Functions

    8.5.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port A 8.6.1 Overview Port A is a 4-bit I/O port. Port A pins also function as address bus outputs. The pin functions change according to the operating mode.

  • Page 279: Register Configuration

    8.6.2 Register Configuration Table 8-9 shows the port A register configuration. Table 8-9 Port A Registers Initial Value * Address * Name Abbreviation Port A data direction register PADDR H'FEB9 Port A data register PADR H'FF69 Port A register PORTA Undefined H'FF59 Port A MOS pull-up control register...
  • Page 280 • Mode 7 * Setting PADDR bits to 1 makes the corresponding port A pins output ports, while clearing the bits to 0 makes the pins input ports. Note: * Modes 6 and 7 are not available in the ROMless versions. Port A Data Register (PADR) —...
  • Page 281 Port A MOS Pull-Up Control Register (PAPCR) — — — — PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Undefined Undefined Undefined Undefined — — — — PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. Bits 7 to 4 are reserved;...

  • Page 282: Pin Functions

    8.6.3 Pin Functions Modes 4 and 5: In modes 4 and 5, the lower 4 bits of port A are designated as address outputs automatically. Port A pin functions in modes 4 and 5 are shown in figure 8-6. (output) (output) Port A (output)

  • Page 283: Mos Input Pull-Up Function

    (I/O) (I/O) Port A (I/O) (I/O) Figure 8-8 Port A Pin Functions (Mode 7) Note: * Modes 6 and 7 are not available in the ROMless versions. 8.6.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7 * , and cannot be used in modes 4 and 5.

  • Page 284: Port B

    Port B 8.7.1 Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 8-9 shows the port B pin configuration.

  • Page 285: Register Configuration

    8.7.2 Register Configuration Table 8-11 shows the port B register configuration. Table 8-11 Port B Registers Address * Name Abbreviation Initial Value Port B data direction register PBDDR H'00 H'FEBA Port B data register PBDR H'00 H'FF6A Port B register PORTB Undefined H'FF5A...
  • Page 286 Port B Data Register (PBDR) PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value : PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

  • Page 287: Pin Functions

    Port B MOS Pull-Up Control Register (PBPCR) PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When PBDDR bits are cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PBPCR bits to 1 turns on the MOS input pull-up for the corresponding pins.
  • Page 288 Mode 6 * : In mode 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting PBDDR bits to 1 makes the corresponding port B pins address outputs, while clearing the bits to 0 makes the pins input ports. Port B pin functions in mode 6 are shown in figure 8-11 When PBDDR = 1 When PBDDR = 0...

  • Page 289: Mos Input Pull-Up Function

    8.7.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis.

  • Page 290: Port C

    Port C 8.8.1 Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 8-13 shows the port C pin configuration.

  • Page 291: Register Configuration

    8.8.2 Register Configuration Table 8-13 shows the port C register configuration. Table 8-13 Port C Registers Address * Name Abbreviation Initial Value Port C data direction register PCDDR H'00 H'FEBB Port C data register PCDR H'00 H'FF6B Port C register PORTC Undefined H'FF5B...
  • Page 292 Port C Data Register (PCDR) PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value : PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

  • Page 293: Pin Functions

    Port C MOS Pull-Up Control Register (PCPCR) PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When PCDDR bits are cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PCPCR bits to 1 turns on the MOS input pull-up for the corresponding pins.
  • Page 294 Mode 6 * : In mode 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting PCDDR bits to 1 makes the corresponding port C pins address outputs, while clearing the bits to 0 makes the pins an input ports. Port C pin functions in mode 6 are shown in figure 8-15.

  • Page 295: Mos Input Pull-Up Function

    8.8.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis.

  • Page 296: Port D

    Port D 8.9.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 8-17 shows the port D pin configuration.

  • Page 297: Register Configuration

    8.9.2 Register Configuration Table 8-15 shows the port D register configuration. Table 8-15 Port D Registers Address * Name Abbreviation Initial Value Port D data direction register PDDDR H'00 H'FEBC Port D data register PDDR H'00 H'FF6C Port D register PORTD Undefined H'FF5C...
  • Page 298 Port D Data Register (PDDR) PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value : PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

  • Page 299: Pin Functions

    Port D MOS Pull-Up Control Register (PDPCR) PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When PDDDR bits are cleared to 0 (input port setting) in mode 7, setting the corresponding PDPCR bits to 1 turns on the MOS input pull-up for the corresponding pins.

  • Page 300: Mos Input Pull-Up Function

    Mode 7 * : In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting PDDDR bits to 1 makes the corresponding port D pins output ports, while clearing the bits to 0 makes the pins input ports. Port D pin functions in mode 7 are shown in figure 8-19.
  • Page 301 Table 8-16 MOS Input Pull-Up States (Port D) Hardware Software In Other Modes Reset Standby Mode Standby Mode Operations 4 to 6 ON/OFF ON/OFF Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PDDDR = 0 and PDPCR = 1; otherwise off. Rev.

  • Page 302: Port E

    8.10 Port E 8.10.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 8-20 shows the port E pin configuration.

  • Page 303: Register Configuration

    8.10.2 Register Configuration Table 8-17 shows the port E register configuration. Table 8-17 Port E Registers Address * Name Abbreviation Initial Value Port E data direction register PEDDR H'00 H'FEBD Port E data register PEDR H'00 H'FF6D Port E register PORTE Undefined H'FF5D...
  • Page 304 Port E Data Register (PEDR) PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial value : PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

  • Page 305: Pin Functions

    Port E MOS Pull-Up Control Register (PEPCR) PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. When PEDDR bits are cleared to 0 (input port setting) in mode 4, 5, or 6 with 8-bit bus mode selected, or in mode 7, setting the corresponding PEPCR bits to 1 turns on the MOS input pull-up for the corresponding pins.

  • Page 306: Mos Input Pull-Up Function

    Mode 7 * : In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting PEDDR bits to 1 makes the corresponding port E pins output ports, while clearing the bits to 0 makes the pins input ports. Port E pin functions in mode 7 are shown in figure 8-22.
  • Page 307 Table 8-18 MOS Input Pull-Up States (Port E) Hardware Software In Other Modes Reset Standby Mode Standby Mode Operations ON/OFF ON/OFF 4 to 6 8-bit bus 16-bit bus Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0 and PEPCR = 1; otherwise off. Rev.

  • Page 308: Port F

    8.11 Port F 8.11.1 Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, BACK, BREQO, CS4, and CS5), the system clock (φ) output pin and interrupt input pins (IRQ0 to IRQ3). The interrupt input pins (IRQ0 to IRQ3) are Schmitt-triggered inputs.

  • Page 309: Register Configuration

    8.11.2 Register Configuration Table 8-19 shows the port F register configuration. Table 8-19 Port F Registers Address * Name Abbreviation Initial Value H'80/H'00 * Port F data direction register PFDDR H'FEBE Port F data register PFDR H'00 H'FF6E Port F register PORTF Undefined H'FF5E...
  • Page 310 Port F Data Register (PFDR) PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial value : PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state after in software standby mode.
  • Page 311 Bit 6—CS36 Select (CSS36): Selects whether CS3 or CS6 is output from the PG1 pin. For details, see section 8.12, Port G. Bit 5—Port F1 Chip Select 5 Select (PF1CS5S): Selects enabling or disabling of CS5 output. This bit is valid in modes 4 to 6. Bit 5 PF1CS5S Description...
  • Page 312 Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bit 5—CS167 Enable (CS167E): Enables or disables CS1, CS6, and CS7 output. For details, see section 8.12, Port G. Bit 4—CS25 Enable (CS25E): Enables or disables CS2, CS3, CS4, and CS5 output. Change the CS25E setting only when the DDR bits are cleared to 0.
  • Page 313 Bus Control Register L (BCRL) BRLE BREQOE — — — — WAITE Initial value : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, selection of the area partition unit, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a reset, and in hardware standby mode.

  • Page 314: Pin Functions

    8.11.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, WAIT, BREQ, BACK, BREQO, CS4, and CS5) the system clock (φ) output pin and interrupt input pins (IRQ0 to IRQ3). The pin functions differ between modes 4 to 6 * , and mode 7 * .
  • Page 315 Selection Method and Pin Functions PF3/LWR/IRQ3 The pin function is switched as shown below according to the operating mode, and bit PF3DDR, and bit LWROD in SYSCR. Operating Modes 4 to 6 * Mode 7 * Mode LWROD — PF3DDR —...
  • Page 316 Selection Method and Pin Functions PF1/BACK/IRQ1/ The pin function is switched as shown below according to the operating mode, and the BRLE bit in BCRL, PF1CS5S bit in PFCR1, and CS25E bit in PFCR2 and PF1DDR bit. Operating Modes 4 to 6 * Mode 7 * Mode BRLE...

  • Page 317: Port G

    8.12 Port G 8.12.1 Overview Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, CS6, CS7). The A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The interrupt input pins (IRQ6, IRQ7) are Schmitt-triggered inputs.

  • Page 318: Register Configuration

    8.12.2 Register Configuration Table 8-21 shows the port G register configuration. Table 8-21 Port G Registers Initial Value * Address * Name Abbreviation H'10/H'00 * Port G data direction register PGDDR H'FEBF Port G data register PGDR H'00 H'FF6F Port G register PORTG Undefined H'FF5F...
  • Page 319 Port G Data Register (PGDR) — — — PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined — — — PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved;...
  • Page 320 Port Function Control Register 1 (PFCR1) CSS17 CSS36 PF1CS5S PF0CS4S A23E A22E A21E A20E Initial value : PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bit 7—CS17 Select (CSS17): Selects whether CS1 or CS7 is output from the PG3 pin.
  • Page 321 Bit 1—Address 21 Enable (A21E): Enables or disables address output 21 (A21). For details, see section 8.2, Port 1. Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). For details, see section 8.2, Port 1. Port Function Control Register 2 (PFCR2) —...

  • Page 322: Pin Functions

    8.12.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3, CS6, CS7) the A/D converter input pin (ADTRG), and interrupt input pins (IRQ6, IRQ7). The pin functions are different in mode 7 * , and modes 4 to 6 * .
  • Page 323 Selection Method and Pin Functions PG1/CS3/CS6/ The pin function is switched as shown below according to the combination of IRQ7 operating mode and CSS36 bit in PFCR1, CS167E bit in PFCR2, CS25E bit and bit PG1DDR. Operating Modes 4 to 6 * Mode 7 * Mode PG1DDR...
  • Page 324 Rev. 5.00, 12/03, page 294 of 1088...

  • Page 325: Features

    Section 9 16-Bit Timer Pulse Unit (TPU) Overview The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 9.1.1 Features • Maximum 16-pulse input/output  A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ...
  • Page 326 • Automatic transfer of register data  Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) activation • A/D converter conversion start trigger can be generated  Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger •...
  • Page 327 Table 9-1 lists the functions of the TPU. Table 9-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 φ/1 φ/1 φ/1 φ/1 φ/1 φ/1 Count clock φ/4 φ/4 φ/4 φ/4 φ/4 φ/4 φ/16 φ/16 φ/16 φ/16...
  • Page 328 Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture input capture input capture A/D con-...

  • Page 329: Block Diagram

    9.1.2 Block Diagram Figure 9-1 shows a block diagram of the TPU. Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5...

  • Page 330: Pin Configuration

    9.1.3 Pin Configuration Table 9-2 summarizes the TPU pins. Table 9-2 TPU Pins Channel Name Symbol Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin...
  • Page 331 Channel Name Symbol Function Input capture/out TIOCA3 TGR3A input capture input/output compare compare match A3 output/PWM output pin Input capture/out TIOCB3 TGR3B input capture input/output compare compare match B3 output/PWM output pin Input capture/out TIOCC3 TGR3C input capture input/output compare compare match C3 output/PWM output pin Input capture/out...

  • Page 332: Register Configuration

    9.1.4 Register Configuration Table 9-3 summarizes the TPU registers. Table 9-3 TPU Registers Address * Channel Name Abbreviation Initial Value Timer control register 0 TCR0 H'00 H'FFD0 Timer mode register 0 TMDR0 H'C0 H'FFD1 Timer I/O control register 0H TIOR0H H'00 H'FFD2 Timer I/O control register 0L...
  • Page 333 Address * Channel Name Abbreviation Initial Value Timer control register 3 TCR3 H'00 H'FE80 Timer mode register 3 TMDR3 H'C0 H'FE81 Timer I/O control register 3H TIOR3H H'00 H'FE82 Timer I/O control register 3L TIOR3L H'00 H'FE83 Timer interrupt enable register 3 TIER3 H'40 H'FE84 R/(W) *...

  • Page 334: Register Descriptions

    Register Descriptions 9.2.1 Timer Control Registers (TCR) Channel 0: TCR0 Channel 3: TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1...
  • Page 335 Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
  • Page 336 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
  • Page 337 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 (Initial value) Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
  • Page 338 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on φ/1 (Initial value) Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input Internal clock: counts on φ/1024 Internal clock: counts on φ/256 Internal clock: counts on φ/4096...

  • Page 339: Timer Mode Registers (Tmdr)

    9.2.2 Timer Mode Registers (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 — — Initial value : — — Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 — — — — Initial value : — — — —...
  • Page 340 Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved.

  • Page 341: Timer I/O Control Registers (Tior)

    9.2.3 Timer I/O Control Registers (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : Channel 0: TIOR0L Channel 3: TIOR3L IOD3 IOD2 IOD1...
  • Page 342 Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4...
  • Page 343 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register * Toggle output at compare match Output disabled Initial output is 1...
  • Page 344 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR1B Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match regist er Toggle output at compare match Output disabled Initial output is 1...
  • Page 345 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR3B Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
  • Page 346 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR3D Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register * Toggle output at compare match Output disabled Initial output is 1...
  • Page 347 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR4B Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
  • Page 348 Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel...
  • Page 349 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR0C Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register * Toggle output at compare match Output disabled Initial output is 1...
  • Page 350 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
  • Page 351 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR3A Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
  • Page 352 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR3C Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register * Toggle output at compare match Output disabled Initial output is 1...
  • Page 353 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR4A Output disabled (Initial value) is output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 354: Timer Interrupt Enable Registers (Tier)

    9.2.4 Timer Interrupt Enable Registers (TIER) Channel 0: TIER0 Channel 3: TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : — — Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 TTGE — TCIEU TCIEV —...
  • Page 355 Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU bit when the TCFU bit in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU Description...

  • Page 356: Timer Status Registers (Tsr)

    Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB Description Interrupt requests (TGIB) by TGFB disabled (Initial value) Interrupt requests (TGIB) by TGFB enabled Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
  • Page 357 The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset and in hardware standby mode. Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5.
  • Page 358 Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD Description...
  • Page 359 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description [Clearing conditions] (Initial value) • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 •...

  • Page 360: Timer Counters (Tcnt)

    9.2.6 Timer Counters (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter * ) Channel 2: TCNT2 (up/down-counter * ) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter * ) Channel 5: TCNT5 (up/down-counter * ) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel.

  • Page 361: Timer Start Register (Tstr)

    9.2.8 Timer Start Register (TSTR) — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : — — TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

  • Page 362: Module Stop Control Register (Mstpcr)

    Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels * , and synchronous clearing through counter clearing on another channel * are possible.

  • Page 363: Interface To Bus Master

    Interface to Bus Master 9.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 9-2.
  • Page 364 Examples of 8-bit register access operation are shown in figures 9-3 to 9-5. Internal data bus Module Bus interface master data bus Figure 9-3 8-Bit Register Access Operation [Bus Master ↔ ↔ ↔ ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface...

  • Page 365: Operation

    Operation 9.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.

  • Page 366: Basic Functions

    9.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 9-6 shows an example of the count operation setting procedure.
  • Page 367 • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
  • Page 368 Figure 9-8 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 9-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
  • Page 369 • Examples of waveform output operation Figure 9-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
  • Page 370 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
  • Page 371 • Example of input capture operation Figure 9-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.

  • Page 372: Synchronous Operation

    9.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
  • Page 373 Example of Synchronous Operation: Figure 9-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing sources.

  • Page 374: Buffer Operation

    9.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 9-5 shows the register combinations used in buffer operation.
  • Page 375 • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9-17. Input capture signal Timer general...
  • Page 376 Examples of Buffer Operation • When TGR is an output compare register Figure 9-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
  • Page 377 • When TGR is an input capture register Figure 9-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.

  • Page 378: Cascaded Operation

    9.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
  • Page 379 Examples of Cascaded Operation: Figure 9-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.

  • Page 380: Pwm Modes

    9.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
  • Page 381 Table 9-7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGR0A TIOCA0 TIOCA0 TGR0B TIOCB0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3...
  • Page 382 Example of PWM Mode Setting Procedure: Figure 9-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
  • Page 383 TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 9-25 Example of PWM Mode Operation (1) Figure 9-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.
  • Page 384 Figure 9-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when period register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...

  • Page 385: Phase Counting Mode

    9.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
  • Page 386 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 9-29 shows an example of phase counting mode 1 operation, and table 9-9 summarizes the TCNT up/down-count conditions.
  • Page 387 • Phase counting mode 2 Figure 9-30 shows an example of phase counting mode 2 operation, and table 9-10 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count...
  • Page 388 • Phase counting mode 3 Figure 9-31 shows an example of phase counting mode 3 operation, and table 9-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
  • Page 389 • Phase counting mode 4 Figure 9-32 shows an example of phase counting mode 4 operation, and table 9-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
  • Page 390 Phase Counting Mode Application Example: Figure 9-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
  • Page 391 Channel 1 TCLKA Edge TCNT1 detection circuit TCLKB TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) − TGR0C − (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 9-33 Phase Counting Mode Application Example Rev.

  • Page 392: Interrupts

    Interrupts 9.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
  • Page 393 Table 9-13 TPU Interrupts Interrupt Channel Source Description Activation Priority TGI0A TGR0A input capture/compare match Possible High TGI0B TGR0B input capture/compare match Possible TGI0C TGR0C input capture/compare match Possible TGI0D TGR0D input capture/compare match Possible TCI0V TCNT0 overflow Not possible TGI1A TGR1A input capture/compare match Possible...

  • Page 394: A/D Converter Activation

    Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

  • Page 395: Operation Timing

    Operation Timing 9.6.1 Input/Output Timing TCNT Count Timing: Figure 9-34 shows TCNT count timing in internal clock operation, and figure 9-35 shows TCNT count timing in external clock operation. φ Falling edge Rising edge Internal clock TCNT input clock TCNT N−1 Figure 9-34 Count Timing in Internal Clock Operation φ...
  • Page 396 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.
  • Page 397 Timing for Counter Clearing by Compare Match/Input Capture: Figure 9-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 9-39 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal H'0000...
  • Page 398 Buffer Operation Timing: Figures 9-40 and 9-41 show the timing in buffer operation. φ TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 9-40 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 9-41 Buffer Operation Timing (Input Capture) Rev.

  • Page 399: Interrupt Signal Timing

    9.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 9-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT Compare match signal...
  • Page 400 TGF Flag Setting Timing in Case of Input Capture: Figure 9-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal TCNT TGF flag TGI interrupt Figure 9-43 TGI Interrupt Timing (Input Capture) Rev.
  • Page 401 TCFV Flag/TCFU Flag Setting Timing: Figure 9-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 9-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
  • Page 402 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9-46 shows the timing for status flag clearing by the CPU, and figure 9-47 shows the timing for status flag clearing by the DTC.

  • Page 403: Usage Notes

    Usage Notes Note that the kinds of operation and contention described below can occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
  • Page 404 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 9-49 shows the timing in this case. TCNT write cycle φ...
  • Page 405 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9-50 shows the timing in this case. TCNT write cycle φ...
  • Page 406 Contention between TGR Write and Compare Match: If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 9-51 shows the timing in this case.
  • Page 407 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 9-52 shows the timing in this case. TGR write cycle φ...
  • Page 408 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 9-53 shows the timing in this case. TGR read cycle φ...
  • Page 409 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 9-54 shows the timing in this case. TGR write cycle φ...
  • Page 410 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9-55 shows the timing in this case. Buffer register write cycle φ...
  • Page 411 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
  • Page 412 Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down- count in the T state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 9-57 shows the operation timing when there is contention between TCNT write and overflow.

  • Page 413: Section 10 8-Bit Timers

    Section 10 8-Bit Timers 10.1 Overview The chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle.

  • Page 414: Block Diagram

    10.1.2 Block Diagram Figure 10-1 shows a block diagram of the 8-bit timer module. External clock sources Internal clock sources φ/8 TMCI0 φ/64 TMCI1 φ/8192 Clock 1 Clock select Clock 0 TCORA0 TCORA1 Compare match A1 Comparator A0 Comparator A1 Compare match A0 Overflow 1 TMO0...

  • Page 415: Pin Configuration

    10.1.3 Pin Configuration Table 10-1 summarizes the input and output pins of the 8-bit timer module. Table 10-1 Input and Output Pins of 8-Bit Timer Channel Name Symbol Function Timer output pin 0 TMO0 Output Outputs at compare match Timer clock input pin 0 TMCI0 Input Inputs external clock for counter...

  • Page 416: Register Descriptions

    10.2 Register Descriptions 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 TCNT1 Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source.
  • Page 417 TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 10.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) TCORB0 TCORB1 Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers.
  • Page 418 Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. Bit 7 CMIEB Description CMFB interrupt requests (CMIB) are disabled (Initial value) CMFB interrupt requests (CMIB) are enabled Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1.
  • Page 419 When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1. Bit 2 Bit 1 Bit 0 CKS2 CKS1...
  • Page 420 Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB Description [Clearing conditions] (Initial value) • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 [Setting condition] Set when TCNT matches TCORB...
  • Page 421 Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified. Bit 4 ADTE Description A/D converter start requests by compare match A are disabled (Initial value) A/D converter start requests by compare match A are enabled...

  • Page 422: Module Stop Control Register (Mstpcr)

    10.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode.

  • Page 423: Operation

    10.3 Operation 10.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 10-2 shows the count timing.
  • Page 424 φ External clock input pin Clock input to TCNT TCNT N−1 Figure 10-3 Count Timing for External Clock Input 10.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
  • Page 425 Timer Output Timing: When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 10-5 shows the timing when the output is set to toggle at compare match A.
  • Page 426 10.3.3 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 10-7 shows the timing of this operation.

  • Page 427: Operation With Cascaded Connection

    10.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode).

  • Page 428: Interrupts

    10.4 Interrupts 10.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 10-3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller.

  • Page 429: Sample Application

    10.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 10-9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA.

  • Page 430: Usage Notes

    10.6 Usage Notes Note that the following kinds of contention can occur in the 8-bit timer module. 10.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed.

  • Page 431: Contention Between Tcnt Write And Increment

    10.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 10-11 shows this operation. TCNT write cycle by CPU φ...

  • Page 432: Contention Between Tcor Write And Compare Match

    10.6.3 Contention between TCOR Write and Compare Match During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. Figure 10-12 shows this operation. TCOR write cycle by CPU φ...

  • Page 433: Contention Between Compare Matches A And B

    10.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 10-4.
  • Page 434 Table 10-5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from Clock before low to low * switchover Clock after switchover TCNT clock TCNT CKS bit write Switching from Clock before low to high *...

  • Page 435: Interrupts And Module Stop Mode

    Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high Clock before to high switchover Clock after switchover TCNT clock TCNT CKS bit write Notes: 1. Includes switching from low to stop, and from stop to low. 2.
  • Page 436 Rev. 5.00, 12/03, page 406 of 1088...

  • Page 437: Section 11 Watchdog Timer

    Section 11 Watchdog Timer 11.1 Overview The chip has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) * if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the chip.

  • Page 438: Block Diagram

    11.1.2 Block Diagram Figure 11-1 shows a block diagram of the WDT. Overflow φ/2 φ/64 Interrupt WOVI control φ/128 (interrupt request φ/512 signal) Clock Clock φ/2048 select φ/8192 φ/32768 WDTOVF Reset φ/131072 control Internal reset signal Internal clock sources RSTCSR TCNT TSCR interface...

  • Page 439: Pin Configuration

    11.1.3 Pin Configuration Table 11-1 describes the WDT output pin. Table 11-1 WDT Pin Name Symbol Function WDTOVF * Output Watchdog timer overflow Outputs counter overflow signal in watchdog timer mode Note: * The WDTOVF function is not available in the F-ZTAT versions. 11.1.4 Register Configuration The WDT has three registers, as summarized in table 11-2.

  • Page 440: Notes On Register Access

    11.2 Register Descriptions 11.2.1 Timer Counter (TCNT) Initial value : TCNT is an 8-bit readable/writable * up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) * or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
  • Page 441 Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 Description [Clearing condition] (Initial value) Cleared by reading TCSR when OVF = 1 * , then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode Note: * When OVF is polled and the interval timer interrupt is disabled, OVF = 1 must be read at...
  • Page 442 Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (φ), for input to TCNT. Description Bit 2 Bit 1 Bit 0 Overflow Period (when φ φ φ φ = 20 MHz) * CKS2 CKS1 CKS0...
  • Page 443 Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF Description [Clearing condition] (Initial value) Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer operation...
  • Page 444 TCNT write H'5A Write data Address: H'FFBC TCSR write H'A5 Write data Address: H'FFBC Figure 11-2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written to by a word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 11-3 shows the format of data written to RSTCSR.

  • Page 445: Operation In Watchdog Timer Mode

    11.3 Operation 11.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally.
  • Page 446 TCNT count Overflow H'FF Time H'00 WOVF=1 WT/IT=1 H'00 written WT/IT=1 H'00 written TME=1 to TCNT TME=1 to TCNT WDTOVF internal reset are generated WDTOVF signal 132 states Internal reset signal 518 states Legend: WT/IT : Timer mode select bit : Timer enable bit Notes: 1.

  • Page 447: Operation In Interval Timer Mode

    11.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 11-5.

  • Page 448: Timing Of Watchdog Timer Overflow Flag (Wovf) Setting

    11.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal * goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip.

  • Page 449: Changing Value Of Cks2 To Cks0

    TCNT write cycle φ Address Internal write signal TCNT input clock TCNT Counter write data Figure 11-8 Contention between TCNT Write and Increment 11.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the incrementation.

  • Page 450: Internal Reset In Watchdog Timer Mode

    System Reset by WDTOVF WDTOVF Signal * WDTOVF WDTOVF 11.5.4 If the WDTOVF output signal * is input to the RES pin of the chip, the chip will not be initialized correctly. Make sure that the WDTOVF signal * is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal * , use the circuit shown in figure 11-9.

  • Page 451: Overview

    Section 12 Serial Communication Interface (SCI) 12.1 Overview The chip is equipped with a serial communication interface (SCI) that can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 12.1.1 Features SCI features are listed below.
  • Page 452 • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...

  • Page 453: Block Diagram

    12.1.2 Block Diagram Figure 12-1 shows a block diagram of the SCI. Internal Module data bus data bus SCMR φ φ/4 Baud rate generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check External clock Legend: SCMR : Smart card mode register : Receive shift register : Receive data register : Transmit shift register...

  • Page 454: Pin Configuration

    12.1.3 Pin Configuration Table 12-1 shows the serial pins for each SCI channel. Table 12-1 SCI Pins Channel Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...

  • Page 455: Register Configuration

    12.1.4 Register Configuration The SCI has the internal registers shown in table 12-2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 12-2 SCI Registers Address * Channel Name...
  • Page 456 12.2 Register Descriptions 12.2.1 Receive Shift Register (RSR) — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
  • Page 457 12.2.3 Transmit Shift Register (TSR) — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
  • Page 458 12.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value : SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.
  • Page 459 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
  • Page 460 Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...
  • Page 461 Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 12.2.8, Bit Rate Register (BRR).
  • Page 462 Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled *...
  • Page 463 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
  • Page 464 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
  • Page 465 12.2.7 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value : R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
  • Page 466 Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description (Initial value) * [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 * Notes: 1.
  • Page 467 Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 Description (Initial value) * [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR *...
  • Page 468 Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in synchronous mode.
  • Page 469 Table 12-3 BRR Settings for Various Bit Rates (Asynchronous Mode) φ φ φ φ = 2 MHz φ φ φ φ = 2.097152 MHz φ φ φ φ = 2.4576 MHz φ φ φ φ = 3 MHz Bit Rate Error Error Error...
  • Page 470 φ φ φ φ = 6 MHz φ φ φ φ = 6.144 MHz φ φ φ φ = 7.3728 MHz φ φ φ φ = 8 MHz Bit Rate Error Error Error Error (bits/s) –0.44 2 0.08 –0.07 2 0.03 0.16 0.00...
  • Page 471 φ φ φ φ = 14 MHz φ φ φ φ = 14.7456 MHz φ φ φ φ = 16 MHz φ φ φ φ = 17.2032 MHz Bit Rate Error Error Error Error (bits/s) –0.17 3 0.70 0.03 0.48 0.16 0.00 0.16...
  • Page 472 Table 12-4 BRR Settings for Various Bit Rates (Synchronous Mode) Bit Rate φ φ φ φ = 2 MHz φ φ φ φ = 4 MHz φ φ φ φ = 8 MHz φ φ φ φ = 10 MHz φ...
  • Page 473 The BRR setting is found from the following formulas. Asynchronous mode: φ × 10 – 1 64 × 2 × B 2n–1 Synchronous mode: φ × 10 – 1 8 × 2 × B 2n–1 Where B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 ≤...
  • Page 474 Table 12-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 12-6 and 12-7 show the maximum bit rates with external clock input. Table 12-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ φ φ φ (MHz) Maximum Bit Rate (bits/s) 62500 2.097152...
  • Page 475 Table 12-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500...
  • Page 476 Table 12-7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ φ φ φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333...
  • Page 477 Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR Description TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level.

  • Page 478: Module Stop Control Register (Mstpcr)

    12.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP6 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode.

  • Page 479: Overview

    12.3 Operation 12.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 12-8.
  • Page 480 Table 12-8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Multi- Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Parity Stop Bit processor C/A A A A STOP Mode Length Length Asynchronous 8-bit data 1 bit mode 2 bits...

  • Page 481: Operation In Asynchronous Mode

    12.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis.
  • Page 482 Table 12-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
  • Page 483 Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12-9.
  • Page 484 Figure 12-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Start of initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 When the clock is selected in asynchronous mode, it is output Set CKE1 and CKE0 bits in SCR...
  • Page 485 • Serial data transmission (asynchronous mode) Figure 12-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin.
  • Page 486 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
  • Page 487 Figure 12-6 shows an example of the operation for transmission in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt TEI interrupt request generated TDRE flag cleared to 0 in request generated request generated...
  • Page 488 • Serial data reception (asynchronous mode) Figure 12-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin.
  • Page 489 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 12-7 Sample Serial Reception Flowchart (cont) Rev.
  • Page 490 In serial reception, the SCI operates as described below. [1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
  • Page 491 Table 12-11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 Framing error When the stop bit is 0 Receive data is transferred from RSR to RDR...

  • Page 492: Multiprocessor Communication Function

    12.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a single serial communication line.
  • Page 493 Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB= 1) (MPB= 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to...
  • Page 494 SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled. SCI status check and transmit TDRE = 1? data write:...
  • Page 495 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
  • Page 496 Figure 12-11 shows an example of SCI operation for transmission using the multiprocessor format. Multi- proces- Multi- Start Data Stop Start Data Stop proces- sor bit Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag cleared to...
  • Page 497 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. ID reception cycle: Read MPIE bit in SCR Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR SCI status check, ID reception and comparison: FER ∨...
  • Page 498 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 12-12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.
  • Page 499 Figure 12-13 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) Stop Start Data (Data1) Stop Idle state (mark state) MPIE RDRF value MPIE = 0 RXI interrupt RDR data read If not this station's ID, RXI interrupt request is request and RDRF flag...

  • Page 500: Operation In Synchronous Mode

    12.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
  • Page 501 Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 12-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
  • Page 502 Data Transfer Operations • SCI initialization (synchronous mode) Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
  • Page 503 • Serial data transmission (synchronous mode) Figure 12-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start of transmission pin.
  • Page 504 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
  • Page 505 Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag request generated request generated cleared to 0 in TXI interrupt handling routine 1 frame...
  • Page 506 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. [2] [3] Receive error handling: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to ORER = 1?
  • Page 507 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR.
  • Page 508 SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start of transmission/reception receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR SCI status check and transmit data write: Read SSR and check that the...

  • Page 509: Sci Interrupts

    12.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 12-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently.

  • Page 510: Usage Notes

    A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may be accepted first, with the result that the TDRE and TEND flags are cleared.
  • Page 511 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
  • Page 512 16 clocks 8 clocks 15 0 15 0 Internal base clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 12-21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by formula (1) below. | D –...
  • Page 513 Restrictions on Use of DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur if the transmit clock is input within 4 φ...
  • Page 514 • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception.
  • Page 515 Transition Exit from to software software End of Start of transmission transmission standby standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 12-24 Asynchronous Transmission Using Internal Clock Transition...
  • Page 516 <Reception> Read RDRF flag in SSR [1] Receive data being received RDRF = 1 becomes invalid. Read receive data in RDR RE = 0 Transition to software [2] Includes module stop mode. standby mode, etc. Exit from software standby mode, etc. Change operating mode? Initialization...

  • Page 517: Section 13 Smart Card Interface

    Section 13 Smart Card Interface 13.1 Overview The SCI supports an IC card (smart card) interface conforming to ISO/IEC 7816-3 (identification card) as a serial communication interface extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting.

  • Page 518: Block Diagram

    13.1.2 Block Diagram Figure 13-1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCMR φ φ/4 Baud rate generator φ/16 Transmission/ φ/64 reception control Parity generation Clock Parity check Legend: SCMR : Smart card mode register : Receive shift register : Receive data register : Transmit shift register...

  • Page 519: Pin Configuration

    13.1.3 Pin Configuration Table 13-1 shows the smart card interface pin configuration. Table 13-1 Smart Card Interface Pins Channel Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...

  • Page 520: Register Configuration

    13.1.4 Register Configuration Table 13-2 shows the registers used by the smart card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 12, Serial Communication Interface (SCI). Table 13-2 Smart Card Interface Registers Address * Channel...

  • Page 521: Register Descriptions

    13.2 Register Descriptions Registers added with the smart card interface and bits for which the function changes are described here. 13.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value : — — — —...

  • Page 522: Serial Status Register (Ssr)

    Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0 SMIF Description Smart card interface function is disabled (Initial value) Smart card interface function is enabled 13.2.2 Serial Status Register (SSR) TDRE...

  • Page 523: Serial Mode Register (Smr)

    Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 12.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Description Indicates transfer in progress [Clearing conditions] •...
  • Page 524 and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). Bit 7 Description Normal smart card interface mode operation (Initial value) •...

  • Page 525: Serial Control Register (Scr)

    Bits 5, 4, 1, and 0—Operate in the same way as for the normal SCI. For details, see section 12.2.5, Serial Mode Register (SMR). 13.2.4 Serial Control Register (SCR) MPIE TEIE CKE1 CKE0 Initial value : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1.

  • Page 526: Overview

    13.3 Operation 13.3.1 Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
  • Page 527 Data line Clock line Rx (port) Reset line Chip IC card Connected equipment Figure 13-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.

  • Page 528: Data Format

    13.3.3 Data Format Normal Transfer Mode: Figure 13-3 shows the smart card interface data format in the normal transfer mode. In reception in this mode, a parity check is carried out on each frame. If an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested.
  • Page 529 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).

  • Page 530: Register Settings

    13.3.4 Register Settings Table 13-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 13-3 Smart Card Interface Register Settings Register Bit 7 Bit 6...
  • Page 531 Smart Card Mode Register (SCMR) Settings: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type.

  • Page 532: Clock

    13.3.5 Clock Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1, and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 13-5 shows some sample bit rates.
  • Page 533 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified.

  • Page 534: Data Transfer Operations

    13.3.6 Data Transfer Operations Initialization: Before transmitting or receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
  • Page 535 Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 13-4 shows a flowchart for transmitting, and figure 13-5 shows the relation between a transmit operation and the internal registers.
  • Page 536 Start Initialization Start of transmission ERS = 0? Error handling TEND = 1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 13-4 Sample Transmission Flowchart Rev.
  • Page 537 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output (3) Serial data output Data 1 In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
  • Page 538 Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 13-7 shows an example of the transmission processing flow. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
  • Page 539 With the above processing, interrupt handling or data transfer by the DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated.
  • Page 540 Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.

  • Page 541: Operation In Gsm Mode

    flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. Note: For details of operation in block transfer mode, see section 12.4, SCI Interrupts. 13.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby...

  • Page 542: Operation In Block Transfer Mode

    Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 13-9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential.

  • Page 543: Usage Notes

    13.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 32, 64, 372, or 256 times the transfer rate (determined by bits BCP1 and BCP0).
  • Page 544 Thus the receive margin in asynchronous mode is given by the following formula.  D – 0.5 (1 + F) × 100% M = (0.5 – ) – (L – 0.5) F – Where M: Receive margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation...
  • Page 545 Transfer nth transfer frame Retransferred frame frame n+1 (DE) D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RDRF Figure 13-11 Retransfer Operation in SCI Receive Mode •...
  • Page 546 Rev. 5.00, 12/03, page 516 of 1088...

  • Page 547: Section 14 A/D Converter (8 Analog Input Channel Version)

    Section 14 A/D Converter (8 Analog Input Channel Version) 14.1 Overview The chip incorporates a successive-approximations type 10-bit A/D converter that allows up to eight analog input channels to be selected. 14.1.1 Features A/D converter features are listed below • 10-bit resolution •...

  • Page 548: Block Diagram

    14.1.2 Block Diagram Figure 14-1 shows a block diagram of the A/D converter. Module data bus Internal data bus 10-bit D/A converter − Comparator Control circuit Sample-and- hold circuit ADI interrupt signal ADTRG Conversion start trigger from 8-bit timer or TPU Legend: ADCR : A/D control register...

  • Page 549: Pin Configuration

    14.1.3 Pin Configuration Table 14-1 summarizes the input pins used by the A/D converter. The AV and AV pins are the power supply pins for the analog block in the A/D converter. The pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7).

  • Page 550: Register Configuration

    14.1.4 Register Configuration Table 14-2 summarizes the registers of the A/D converter. Table 14-2 A/D Converter Registers Address * Name Abbreviation Initial Value A/D data register AH ADDRAH H'00 H'FF90 A/D data register AL ADDRAL H'00 H'FF91 A/D data register BH ADDRBH H'00 H'FF92...

  • Page 551: Register Descriptions

    14.2 Register Descriptions 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
  • Page 552 14.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value : R/(W) * Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation.
  • Page 553 Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description...
  • Page 554 Group Selection Channel Selection Description Single Mode (SCAN = 0) Scan Mode (SCAN = 1) AN0 (Initial value) AN0, AN1 AN0 to AN2 AN0 to AN3 AN4, AN5 AN4 to AN6 AN4 to AN7 14.2.3 A/D Control Register (ADCR) TRGS1 TRGS0 —...

  • Page 555: Module Stop Control Register (Mstpcr)

    Bits 5, 4, 1, and 0—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Clock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D conversion time. See the description of the CKS bit for details. Bit 2—Reserved: A value of 1 must be written to this bit.

  • Page 556: Interface To Bus Master

    14.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).

  • Page 557: Operation

    14.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input.
  • Page 558 Set* ADIE Set* Set* conversion starts ADST Clear* Clear* State of channel 0 Idle (AN0) State of channel 1 Idle Idle Idle A/D conversion A/D conversion (AN1) State of channel 2 Idle (AN2) State of Idle channel 3 (AN3) ADDRA Read conversion result Read conversion result A/D conversion result 2...

  • Page 559: Scan Mode (Scan = 1)

    14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0).
  • Page 560 Continuous A/D conversion Clear ADST Clear A/D conversion time State of channel 0 Idle Idle A/D conversion 1 A/D conversion 4 Idle (AN0) State of Idle A/D conversion 2 Idle A/D conversion 5 Idle channel 1 (AN1) State of Idle Idle channel 2 A/D conversion 3...

  • Page 561: Input Sampling And A/D Conversion Time

    14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 14-5 shows the A/D conversion timing.

  • Page 562: External Trigger Input Timing

    Table 14-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS = 0 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion —...

  • Page 563: Interrupts

    φ ADTRG Internal trigger signal ADST A/D conversion Figure 14-6 External Trigger Input Timing 14.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC can be activated by an ADI interrupt.

  • Page 564: Usage Notes

    14.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range ≤...
  • Page 565 ), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. 100 Ω AN0 to AN7 0.1 µF Notes: Values are reference values. 10 µF 0.01 µF 2 . R : Input impedance Figure 14-7 Example of Analog Input Protection Circuit A/D Conversion Precision Definitions: The chip’s A/D conversion precision definitions are...
  • Page 566 • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14-8). • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. •...
  • Page 567 Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 14-9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: The chip’s analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
  • Page 568 Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. Chip A/D converter equivalent circuit Sensor output impedance Max. 5 kΩ 10 kΩ Sensor input = 15 pF 20 pF Low-pass filter...

  • Page 569: Section 15 D/A Converter

    Section 15 D/A Converter 15.1 Overview The chip includes an 8-bit resolution D/A converter with two analog signal output channels. 15.1.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) •...

  • Page 570: Block Diagram

    15.1.2 Block Diagram Figure 15-1 shows a block diagram of the D/A converter. Module data bus Internal data bus 8-bit converter Control circuit Legend: DACR: D/A control register DADR0, DADR1: D/A data registers 0, 1 Figure 15-1 Block Diagram of D/A Converter Rev.

  • Page 571: Pin Configuration

    15.1.3 Pin Configuration Table 15-1 summarizes the input and output pins of the D/A converter. Table 15-1 Pin Configuration Pin Name Symbol Function Analog power pin Input Analog power source Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Channel 0 analog output Analog output pin 1...

  • Page 572: Register Descriptions

    15.2 Register Descriptions 15.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) Initial value : DADR0, DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins.
  • Page 573 Bit 5—D/A Enable (DAE): Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 0 and 1 D/A conversions are controlled together.

  • Page 574: Module Stop Control Register (Mstpcr)

    15.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode.

  • Page 575: Operation

    15.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1.
  • Page 576 DADR0 DACR01 DADR0 DACR01 write cycle write cycle write cycle write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion Conversion result 2 High-impedance state result 1 DCONV DCONV Legend: : D/A conversion time DCONV Figure 15-2 Example of D/A Converter Operation Rev.

  • Page 577: Section 16 Ram

    Section 16 RAM 16.1 Overview The chip has on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.

  • Page 578: Register Configuration

    16.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 16-1 shows the address and initial value of SYSCR. Table 16-1 RAM Register Address * Name Abbreviation Initial Value System control register SYSCR H'01 H'FF39 Note: * Lower 16 bits of the address. 16.2 Register Descriptions 16.2.1...

  • Page 579: Operation

    16.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF * are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units.
  • Page 580 Rev. 5.00, 12/03, page 550 of 1088...

  • Page 581: Section 17 Rom

    Section 17 ROM 17.1 Overview The Group has 512, 384, 256, or 128 kbytes of on-chip flash memory, or 512, 256, 128, or 32 kbytes of on-chip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state.

  • Page 582: Register Configuration

    17.1.2 Register Configuration The operating mode of the chip is controlled by the mode pins and the BCRL register. The ROM- related registers are shown in table 17-1. Table 17-1 ROM Registers Address * Register Name Abbreviation Initial Value Mode control register MDCR Undefined H'FF3B...

  • Page 583: Bus Control Register L (Bcrl)

    17.2.2 Bus Control Register L (BCRL) BRLE BREQOE — — — — WAITE Initial value : Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL).
  • Page 584 Table 17-2 Operating Modes and ROM (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) Mode Pins BCRL Mode Operating Mode On-Chip ROM — — — Advanced expanded mode — Disabled with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode Enabled (256 kbytes) *...
  • Page 585 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled.
  • Page 586 Table 17-3 Operating Modes and ROM (H8S/2319 F-ZTAT, H8S/2319C F-ZTAT, and Mask ROM Versions) Mode Pins BCRL Mode Operating Mode On-Chip ROM — — — Advanced expanded mode — Disabled with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Enabled (256 kbytes) * Advanced expanded mode with on-chip ROM enabled...

  • Page 587: Overview Of Flash Memory (H8S/2318 F-Ztat, H8S/2317 F-Ztat, H8S/2315 F-Ztat, H8S/2314 F-Ztat)

    17.4 Overview of Flash Memory (H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) 17.4.1 Features The H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, and H8S/2314 F-ZTAT have 384, 256, 128 kbytes of on-chip flash memory. The features of the flash memory are summarized below.

  • Page 588: Overview

    • Programmer mode Flash memory can be programmed/erased in programmer mode, using a PROM programmer, as well as in on-board programming mode. Note: * Flash memory emulation by RAM is not supported in the H8S/2314 F-ZTAT. 17.4.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1...

  • Page 589: Flash Memory Operating Modes

    17.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset- start is executed, the chip enters one of the operating modes shown in figure 17-3. In user mode, flash memory can be read but not programmed or erased.

  • Page 590: On-Board Programming Modes

    17.4.4 On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the chip (originally incorporated in the chip) is programming control program and new started and the programming control program in...
  • Page 591 • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The FWE assessment program that confirms When the FWE pin is driven high, user software that the FWE pin has been driven high, and (2) confirms this fact, executes the transfer program the program that will transfer the programming/ in the flash memory, and transfers the erase control program to on-chip RAM should be...

  • Page 592: Flash Memory Emulation In Ram

    17.4.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Flash memory Overlap RAM Emulation block...

  • Page 593: Differences Between Boot Mode And User Program Mode

    Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.

  • Page 594: Block Configuration

    17.4.7 Block Configuration On-chip 128-kbyte flash memory is divided into one 64-kbyte block, one 32-kbyte block, and eight 4-kbyte blocks. On-chip 256-kbyte flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. On-chip 384-kbyte flash memory is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks.

  • Page 595: Pin Configuration

    17.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 17-5. Table 17-5 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets MCU operating mode Mode 1...

  • Page 596: Register Configuration

    17.4.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 17-6. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 17-6 Flash Memory Registers Address * Register Name...

  • Page 597: Register Descriptions

    17.5 Register Descriptions 17.5.1 Flash Memory Control Register 1 (FLMCR1) Initial value : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit.
  • Page 598 Bit 6 Description Writes disabled (Initial value) Writes enabled [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 Description Erase setup cleared...
  • Page 599 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing.

  • Page 600: Flash Memory Control Register 2 (Flmcr2)

    17.5.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value : — — — — — — — FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.

  • Page 601: Erase Block Register 1 (Ebr1)

    17.5.3 Erase Block Register 1 (EBR1) EBR1 Initial value : EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set.

  • Page 602: System Control Register 2 (Syscr2)

    Table 17-7 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF...

  • Page 603: Ram Emulation Register (Ramer)

    Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
  • Page 604 Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS Description Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together...

  • Page 605: On-Board Programming Modes

    17.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 17-9.
  • Page 606 Chip Flash memory Host Write data reception RxD1 SCI1 On-chip RAM Verify data transmission TxD1 Figure 17-9 System Configuration in Boot Mode Rev. 5.00, 12/03, page 576 of 1088...
  • Page 607 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Host transmits number Chip measures low period of programming control program of H'00 data transmitted by host bytes (N), upper byte followed by lower byte Chip calculates bit rate and sets value in bit rate register...
  • Page 608 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, or H8S/2314 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
  • Page 609 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 17-12. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state.
  • Page 610 H'FFDC00 Boot program area (2 kbytes) Reserved area used H'FFE3FF only in boot mode (4 kbytes) H'FFEBFF H'FFEC00 Programming control program area (6 kbytes) H'FFFBFF Notes: 1. This is a reserved area used only in boot mode. It should not be used for any purpose other than flash memory programming/erasing.
  • Page 611 The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program.
  • Page 612 Figure 17-14 shows the procedure for executing the program/erase control program when transferred to on-chip RAM. Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area...

  • Page 613: Programming/Erasing Flash Memory

    17.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for the on-chip ROM area by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.

  • Page 614: Program-Verify Mode

    elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 17.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been...
  • Page 615 Write pulse application subroutine Start of programming Sub-routine write pulse Start Perform programming in the erased state. Do not perform additional programming Enable WDT Set SWE bit in FLMCR1 on previously programmed addresses. Set PSU bit in FLMCR1 Wait (x) µs Wait (y) µs Store 128-byte program data in program data area and reprogram data area...

  • Page 616: Erase Mode

    17.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 17-16. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 20.3.6, Flash Memory Characteristics.
  • Page 617 Start Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) ms n ← n + 1 Clear E bit in FLMCR1 Halt erase Wait (α) µs...

  • Page 618: Flash Memory Protection

    17.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 17-11).

  • Page 619: Error Protection

    Table 17-12 Software Protection Functions Item Description Program Erase • SWE bit protection Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks (Execute in on-chip RAM or external memory.) • Block specification — Erase protection can be set for individual protection blocks by settings in erase block registers 1 and 2 (EBR1, EBR2).
  • Page 620 Error protection is released only by a reset and in hardware standby mode. Figure 17-17 shows the flash memory state transition diagram. Normal operating mode Reset or hardware standby Program mode RES = 0 or STBY = 0 (hardware protection) Erase mode RD VF PR ER RD VF PR ER...

  • Page 621: Flash Memory Emulation In Ram

    17.9 Flash Memory Emulation in RAM 17.9.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.

  • Page 622: Ram Overlap

    17.9.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFDC00 H'FFEBFF Flash memory...

  • Page 623: Interrupt Handling When Programming/Erasing Flash Memory

    state, setting the P or E bit in flash memory control register 1 (FLMCR1) will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2.

  • Page 624: Flash Memory Programmer Mode

    Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer * that supports the Renesas Technology microcomputer device type with 256- kbyte on-chip flash memory (FZTAT256V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.

  • Page 625: Socket Adapters And Memory Map

    17.11.2 Socket Adapters and Memory Map In programmer mode, a socket adapter is connected to the chip as shown in figures 17-21 and 17-23. Figure 17-20 shows the on-chip ROM memory map and figures 17-21 and 17-23 show the socket adapter pin assignments. MCU mode address Programmer mode address H'00000000...
  • Page 626 H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, Socket Adapter HN27C4096HG (40 Pins) H8S/2315 F-ZTAT, H8S/2314 F-ZTAT (40-Pin Conversion) TFP-100B, FP-100A Pin No. Pin Name Pin Name TFP-100G 1, 40 40, 63, 64, 65, 74, 42, 65, 66, 67, 76, 77, 78, 98, 59 79, 80, 100, 61 11, 30 5, 6, 7...

  • Page 627: Programmer Mode Operation

    17.11.3 Programmer Mode Operation Table 17-14 shows how the different operating modes are set when using programmer mode, and table 17-15 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.

  • Page 628: Memory Read Mode

    Table 17-15 Programmer Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write...
  • Page 629 Command write Memory read mode to A Address stable nxtc Data H'00 Data Note: Data is latched at the rising edge of WE. Figure 17-22 Memory Read Mode Timing Waveforms after Command Write Table 17-17 AC Characteristics when Entering Another Mode from Memory Read Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...
  • Page 630 Other mode command write Memory read mode to A Address stable nxtc to I/O Note: Do not enable WE and OE at the same time. Figure 17-23 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 17-18 AC Characteristics in Memory Read Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...

  • Page 631: Auto-Program Mode

    Address stable Address stable to A to I/O Figure 17-25 Timing Waveforms for CE CE/OE OE Clocked Read 17.11.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. •...
  • Page 632 AC Characteristics Table 17-19 AC Characteristics in Auto-Program Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Item Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time —...

  • Page 633: Auto-Erase Mode

    17.11.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O . Alternatively, status read mode can also be used for this purpose (the I/O status polling pin is used to identify the end of an auto-erase operation).

  • Page 634: Status Read Mode

    to A nxtc nxtc ests erase Erase end identifi- cation signal Erase normal end confirmation signal H'00 H'20 H'20 to I/O Figure 17-27 Auto-Erase Mode Timing Waveforms 17.11.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.

  • Page 635: Status Polling

    to A nxtc nxtc nxtc H'71 H'71 to I/O Note: I/O and I/O are undefined. Figure 17-28 Status Read Mode Timing Waveforms Table 17-22 Status Read Mode Return Commands Pin Name I/O Attribute Normal Command Program- Erase — — Program- Effective error ming error...

  • Page 636: Programmer Mode Transition Time

    Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.

  • Page 637: Flash Memory Programming And Erasing Precautions

    Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A) or the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
  • Page 638 Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying or disconnecting FWE. Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory.
  • Page 639 Programming/ erasing Wait time: 100 µs possible Wait time: x φ Min 0 µs OSC1 Min 0 µs MD2 to MD0 SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
  • Page 640 Programming/ erasing Wait time: 100 µs possible Wait time: x φ Min 0 µs OSC1 MD2 to MD0 SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
  • Page 641 φ OSC1 Min 0 µs MD2 to MD0 RESW SWE bit cleared Mode Boot Mode User User program mode User User program change mode change mode mode mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.

  • Page 642: Overview Of Flash Memory (H8S/2319 F-Ztat)

    17.13 Overview of Flash Memory (H8S/2319 F-ZTAT) 17.13.1 Features The H8S/2319 F-ZTAT has 512 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes  Program mode  Erase mode ...

  • Page 643: Overview

    17.13.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating Bus interface/controller Mode pin mode EBR1 EBR2 RAMER SYSCR2 Flash memory (512 kbytes) Legend: FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2:...

  • Page 644: Flash Memory Operating Modes

    17.13.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 17-34. In user mode, flash memory can be read but not programmed or erased.

  • Page 645: On-Board Programming Modes

    17.13.4 On-Board Programming Modes • Boot mode 1. Initial state 2. Programming control program transfer The old program version or data remains written When boot mode is entered, the boot program in in the flash memory. The user should prepare the the chip (originally incorporated in the chip) is programming control program and new started and the programming control program in...
  • Page 646 • User program mode 1. Initial state 2. Programming/erase control program transfer (1) The program that will transfer the Executes the transfer program in the flash programming/erase control program to on-chip memory, and transfers the programming/erase RAM should be written into the flash memory by control program to RAM.

  • Page 647: Flash Memory Emulation In Ram

    17.13.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Flash memory Overlap RAM Emulation block...

  • Page 648: 17.13.6 Differences Between Boot Mode And User Program Mode

    Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.

  • Page 649: 17.13.7 Block Configuration

    17.13.7 Block Configuration The flash memory is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'000000 4 kbytes × 8 32 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'07FFFF Figure 17-39 Flash Memory Block Configuration Rev.

  • Page 650: 17.13.8 Pin Configuration

    17.13.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 17-26. Table 17-26 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Mode 2 Input Sets MCU operating mode Mode 1 Input Sets MCU operating mode Mode 0 Input Sets MCU operating mode...

  • Page 651: 17.13.9 Register Configuration

    17.13.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 17-27. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 17-27 Flash Memory Registers Address * Register Name...

  • Page 652: Register Descriptions

    17.14 Register Descriptions 17.14.1 Flash Memory Control Register 1 (FLMCR1) FWE1 SWE1 ESU1 PSU1 Initial value : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 then setting the EV1 or PV1 bit.
  • Page 653 Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time. Bit 5 ESU1 Description Erase setup cleared (Initial value) Erase setup [Setting condition]...

  • Page 654: Flash Memory Control Register 2 (Flmcr2)

    Bit 1—Erase 1 (E1): Selects erase mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, PV1, or P1 bit at the same time. Bit 1 Description Erase mode cleared (Initial value) Transition to erase mode [Setting condition] When SWE1 = 1, and ESU1 = 1 Bit 0—Program 1 (P1): Selects program mode transition or clearing for addresses H'000000 to...
  • Page 655 Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error- protection state. Bit 7 FLER Description Flash memory is operating normally (Initial value) Flash memory program/erase protection (error protection) is disabled [Clearing condition]...
  • Page 656 Bit 4—Program Setup Bit 2 (PSU2): Prepares for a transition to program mode for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, EV2, PV2, E2, or P2 bit at the same time. Bit 4 PSU2 Description Program setup cleared (Initial value) Program setup [Setting condition]...

  • Page 657: Erase Block Register 1 (Ebr1)

    Bit 0—Program 2 (P2): Selects program mode transition or clearing for H'040000 to H'07FFFF. Do not set the SWE2, PSU2, ESU2, EV2, PV2, or E2 bit at the same time. Bit 0 Description Program mode cleared (Initial value) Transition to program mode [Setting condition] When SWE2 = 1, and PSU2 = 1 17.14.3 Erase Block Register 1 (EBR1)

  • Page 658: Erase Block Register 2 (Ebr2)

    17.14.4 Erase Block Register 2 (EBR2) EBR2 EB15 EB14 EB13 EB12 EB11 EB10 Initial value : EBR2 is an 8-bit register that specifies the flash memory erase area block by block. EBR2 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and when the SWE1 bit in FLMCR1 is not set.

  • Page 659: System Control Register 2 (Syscr2)

    17.14.5 System Control Register 2 (SYSCR2) — — — — FLSHE — — — Initial value : — — — — — — SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized to H'00 by a reset and in hardware standby mode. SYSCR2 can only be used in the F-ZTAT version.
  • Page 660 Flash memory area divisions are shown in table 17-29. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed.

  • Page 661: On-Board Programming Modes

    17.15 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 17-30.
  • Page 662 Chip Flash memory Host Write data reception RxD1 SCI1 On-chip RAM Verify data transmission TxD1 Figure 17-40 System Configuration in Boot Mode Rev. 5.00, 12/03, page 632 of 1088...
  • Page 663 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Host transmits number Chip measures low period of programming control program of H'00 data transmitted by host bytes (N), upper byte followed by lower byte Chip calculates bit rate and sets value in bit rate register...
  • Page 664 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2319 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity.
  • Page 665 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 17-43. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state.

  • Page 666: 17.15.2 User Program Mode

    • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
  • Page 667 or flash memory except for the above address areas. When the program is located in external memory, an instruction for programming the flash memory and the following instruction should be located in on-chip RAM. Figure 17-44 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.

  • Page 668: Program Mode (N = 1 For Addresses H'000000 To H'03Ffff, And N = 2 For Addresses H'040000 To H'07Ffff)

    17.16 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for addresses H'000000 to H'03FFFF by setting the PSU1, ESU1, P1, E1, PV1, and EV1 bits in FLMCR1, and for addresses H'040000 to H'07FFFF by setting the PSU2, ESU2, P2, E2, PV2, and EV2 bits in FLMCR2.

  • Page 669: Program-Verify Mode (N = 1 For Addresses H'000000 To H'03Ffff, And N = 2 For Addresses H'040000 To H'07Ffff)

    in the flash memory. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α...
  • Page 670 Write pulse application subroutine Start of programming Sub-routine write pulse Start Perform programming in the erased state. Do not perform additional programming Enable WDT Set SWE1 (2) bit in FLMCR1 (2) on previously programmed addresses. Set PSU1 (2) bit in FLMCR1 (2) Wait (x) µs Wait (y) µs Store 128-byte program data in program...

  • Page 671: Erase Mode

    17.16.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF, and n = 2 for addresses H'040000 to H'07FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 17-46. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 20.3.6, Flash Memory Characteristics.
  • Page 672 Start Set SWE1 (2) bit in FLMCR1 (2) Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU1 (2) bit in FLMCR1 (2) Wait (y) µs Start of erase Set E1 (2) bit in FLMCR1 (2) Wait (z) ms n ←...

  • Page 673: Flash Memory Protection

    17.17 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.17.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 17-32).

  • Page 674: Software Protection

    Table 17-33 Software Protection Functions Item Description Program Erase • SWE bit protection Clearing the SWE1 bit to 0 in FLMCR1 sets the program/erase-protected state for area H'000000 to H'03FFFF (Execute in on-chip RAM, external memory, or addresses H'040000 to H'07FFFF) •...

  • Page 675: 17.17.3 Error Protection

    17.17.3 Error Protection In error protection, an error is detected when MCU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the MCU malfunctions during flash memory programming/erasing, the FLER bit is set to 1 in FLMCR2 and the error protection state is entered.
  • Page 676 Normal operating mode Reset or hardware standby Program mode RES = 0 or STBY = 0 (hardware protection) Erase mode RD VF PR ER RD VF PR ER FLER = 0 FLER = 0 RES = 0 or Error occurrence STBY = 0 FLMCR1, FLMCR2, (software standby)

  • Page 677: Flash Memory Emulation In Ram

    17.18 Flash Memory Emulation in RAM 17.18.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.

  • Page 678: 17.18.2 Ram Overlap

    17.18.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'000000 H'001000 H'002000 H'030000 H'004000 H'005000 H'006000 H'007000 H'008000 H'FFDC00 H'FFEBFF Flash memory...

  • Page 679: Interrupt Handling When Programming/Erasing Flash Memory

    2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 17.19 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or...

  • Page 680: Flash Memory Programmer Mode

    Programs and data can be written and erased in programmer mode as well as in the on-board programming modes. In programmer mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas Technology microcomputer device type with 512- kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
  • Page 681 H8S/2319 F-ZTAT HN27C4096HG (40 Pins) Socket Adapter (40-Pin Conversion) TFP-100B FP-100A Pin No. Pin Name Pin Name EMLE 1, 40 40, 63, 64, 65, 74, 42, 65, 66, 67, 76, 77, 78, 98, 59 79, 80, 100, 61 11, 30 5, 6, 7 7, 18, 31, 49, 57, 9, 20, 33, 51, 59,...

  • Page 682: 17.20.3 Programmer Mode Operation

    17.20.3 Programmer Mode Operation Table 17-35 shows how the different operating modes are set when using programmer mode, and table 17-36 lists the commands used in programmer mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.

  • Page 683: 17.20.4 Memory Read Mode

    Table 17-36 Programmer Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write...
  • Page 684 Command write Memory read mode to A Address stable nxtc Data H'00 Data Note: Data is latched at the rising edge of WE. Figure 17-52 Memory Read Mode Timing Waveforms after Command Write Table 17-38 AC Characteristics when Entering Another Mode from Memory Read Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...
  • Page 685 Other mode command write Memory read mode to A Address stable nxtc to I/O Note: Do not enable WE and OE at the same time. Figure 17-53 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 17-39 AC Characteristics in Memory Read Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T...

  • Page 686: Auto-Program Mode

    Address stable Address stable to A to I/O Figure 17-55 Timing Waveforms for CE CE/OE OE Clocked Read 17.20.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. •...
  • Page 687 AC Characteristics Table 17-40 AC Characteristics in Auto-Program Mode (Conditions: V = 3.3 V ±0.3 V, V = 0 V, T = 25°C ±5°C) Item Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time —...

  • Page 688: Auto-Erase Mode

    17.20.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O . Alternatively, status read mode can also be used for this purpose (the I/O status polling pin is used to identify the end of an auto-erase operation).

  • Page 689: Status Read Mode

    to A nxtc nxtc ests erase Erase end identifi- cation signal Erase normal end confirmation signal H'00 H'20 H'20 to I/O Figure 17-57 Auto-Erase Mode Timing Waveforms 17.20.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.

  • Page 690: 17.20.8 Status Polling

    to A nxtc nxtc nxtc H'71 H'71 to I/O Note: I/O and I/O are undefined. Figure 17-58 Status Read Mode Timing Waveforms Table 17-43 Status Read Mode Return Commands Pin Name I/O Attribute Normal Command Program- Erase — — Program- Effective error ming error...

  • Page 691: 17.20.9 Programmer Mode Transition Time

    Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level.

  • Page 692: Flash Memory Programming And Erasing Precautions

    Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas Technology microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
  • Page 693 Do not perform additional programming. Erase the memory before reprogramming: In on- board programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased.

  • Page 694: Overview Of Flash Memory (H8S/2319C 0.18Μm F-Ztat)

    17.22 Overview of Flash Memory (H8S/2319C 0.18µm F-ZTAT) 17.22.1 Features This LSI has an on-chip 512-kbyte flash memory. The flash memory has the following features. • Two flash-memory MATs according to LSI initiation mode The on-chip flash memory has two memory spaces in the same address space (hereafter referred to as memory MATs).
  • Page 695 • Programming/erasing time The flash memory programming time is TBD ms (typ) for 128-byte simultaneous programming, which is equivalent to TBD µs per byte. The erasing time is TBD ms (typ) per 64-kbyte block. • Number of programming Flash memory programming can be performed a minimum of 100 times. Rev.

  • Page 696: 17.22.2 Overview

    17.22.2 Overview (1) Block Diagram Internal address bus Internal data bus (16 bits) FCCS FPCS FECS Memory MAT unit FKEY Control unit User MAT: 512 kbytes User boot MAT: 8 kbytes FMATS FTDAR RAMER Flash memory Operating Mode pin mode Legend: FCCS: Flash code control and status register...

  • Page 697: 17.22.3 Operating Mode Of Flash Memory

    17.22.3 Operating Mode of Flash Memory When each mode pin is set in the reset state and reset start is performed, the microcomputer enters each operating mode as shown in figure 17-61. For the setting of each mode pin, see table 17-52. •...

  • Page 698: 17.22.4 Mode Comparison

    17.22.4 Mode Comparison The comparison table of programming and erasing related items about boot mode, user program mode, user boot mode, and PROM mode is shown in table 17-46. Table 17-46 Comparison of Programming Modes User program Boot mode mode User boot mode PROM mode Programming/...

  • Page 699: 17.22.5 Flash Mat Configuration

    17.22.5 Flash MAT Configuration This LSI's flash memory is configured by the 512-kbyte user MAT and 8-kbyte user boot MAT. The start address is allocated to the same address in the user MAT and user boot MAT. Therefore, when the program execution or data access is performed between two MATs, the MAT must be switched by using FMATS.

  • Page 700: 17.22.7 Programming/Erasing Interface

    <User MAT> Erase block Address H'000000 4 kbytes × 8 32 kbytes 64 kbytes 64 kbytes EB10 EB11 64 kbytes 64 kbytes EB12 64 kbytes EB13 64 kbytes EB14 64 kbytes EB15 Address H'07FFFF Note: * The RAM emulation can be performed in the eight blocks of 4 kbytes. Figure 17-63 Block Division of User MAT 17.22.7 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and...
  • Page 701 Start user procedure program for programming/erasing Select on-chip program to be downloaded and set download destination Download on-chip program by setting FKEY and the SCO bits Initialization execution (download program execution) Programming (in 128-byte units) or erasing (in one-block units) (download program execution) Programming/erasing completed?
  • Page 702 3. Initialization of programming/erasing The operating frequency is set before execution of programming/erasing. This setting is performed by using the programming/erasing interface parameters. 4. Programming/erasing execution To program or erase, the FLSHE bit in system control register 2 (SYSCR2) must be set to 1 and the user program mode must be entered.

  • Page 703: Pin Configuration

    17.22.8 Pin Configuration Flash memory is controlled by the pin as shown in table 17-47. Table 17-47 Pin Configuration Pin Name Abbreviation Input/Output Function Reset Input Reset Mode 2 Input Sets operating mode of this LSI Mode 1 Input Sets operating mode of this LSI Mode 0 Input Sets operating mode of this LSI...

  • Page 704: Register Configuration

    Table 17-48 (1) Register Configuration Name Abbreviation Initial Value Address R, W * Flash code control status register FCCS H'00 H'FFC4 H'80 Flash program code select register FPCS H'00 H'FFC5 Flash erase code select register FECS H'00 H'FFC6 Flash key code register FKEY H'00 H'FFC8...

  • Page 705: Register Description Of Flash Memory

    Table 17-49 Register/Parameter and Target Mode Initiali- Program- Download zation ming Erasure Read Emulation Programming/ FCCS — — — — — erasing interface FPCS — — — — — registers PECS — — — — — FKEY — — — FMATS —...
  • Page 706 Bits 6 and 5—Reserved: These bits are always read as 0. The write value should always be 0. Bit 4—Flash Memory Error (FLER): Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. This bit is initialized at a power-on reset or in hardware standby mode.
  • Page 707 Bit 0 Description Download of the on-chip programming/erasing program to the on-chip RAM is not executed (Initial value) [Clear condition] When download is completed Request that the on-chip programming/erasing program is downloaded to the on- chip RAM is occurred [Set conditions] When all of the following conditions are satisfied and 1 is written to this bit •...
  • Page 708 (3) Flash Erase Code Select Register (FECS) FECS selects download of the on-chip erasing program. — — — — — — — EPVB Initial value : Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0. Bit 0—Erase Pulse Verify Block (EPVB): Selects the erasing program.
  • Page 709 Bits 7 to 0 K7 to K0 Description H'A5 Writing to the SCO bit is enabled (The SCO bit cannot be set by the value other than H'A5.) H'5A Programming/erasing is enabled (The value other than H'5A is in software protection state.) H'00 Initial value...
  • Page 710 (6) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFBC00) in on-chip RAM. TDER TDA6 TDA5...

  • Page 711: 17.23.2 Programming/Erasing Interface Parameter

    17.23.2 Programming/Erasing Interface Parameter The programming/erasing interface parameter specifies the operating frequency, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (ER0 and ER1) or the on-chip RAM area.
  • Page 712 Table 17-50 Usable Parameters and Target Modes Name of Abbre- Down- Initializa- Program- Initial Alloca- Parameter viation load tion ming Erasure Value tion Download pass/ DPFR — — — Undefined On-chip RAM * fail result Flash pass/fail FPFR — Undefined R0L of result Flash...
  • Page 713 Initial value : — — — — — — — — — — — — — Bits 7 to 3—Reserved: Return 0. Bit 2—Source Select Error Detect (SS): The on-chip program which can be downloaded can be specified only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, error is occurred.
  • Page 714 (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set.
  • Page 715 Bits 15 to 0—Frequency Set (F15 to F0): Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1. The operating frequency which is shown in MHz units must be rounded in a number to three decimal places and be shown in a number of two decimal places.
  • Page 716 (3) Programming Execution When flash memory is programmed, the programming destination address on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register ER1 of the CPU.
  • Page 717 (a) Flash multipurpose address area parameter (FMPAR: general register ER1 of CPU) This parameter indicates the start address of the programming destination on the user MAT. When an address in an area other than the flash memory space is set, an error occurs. The start address of the programming destination must be at the 128-byte boundary.
  • Page 718 (b) Flash multipurpose data destination parameter (FMPDR: general register ER0 of CPU): This parameter indicates the start address in the area which stores the data to be programmed in the user MAT. When the storage destination of the program data is in flash memory, an error occurs.
  • Page 719 (c) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the programming result is provided here. Initial value : — — — — — — — — — — Bit 7—Reserved: Returns 0. Bit 6—Programming Mode Related Setting Error Detect (MD): Returns the check result of whether the error protection state has been entered.
  • Page 720 Bit 4—Flash Key Register Error Detect (FK): Returns the check result of the value of FKEY before the start of the programming processing. Bit 4 Description FKEY setting is normal (FKEY = H'5A) FKEY setting is error (FKEY = value other than H'5A) Bit 3—Reserved: Returns 0.
  • Page 721 (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded. This is set to the FEBS parameter (general register ER0). One block is specified from the block number 0 to 15. For details on the erasing processing procedure, see section 17.24.2, User Program Mode.
  • Page 722 (b) Flash pass/fail parameter (FPFR: general register R0L of CPU) An explanation of FPFR as the return value indicating the erase result is provided here. Initial value : — — — — — — — — — — — Bit 7—Reserved: Returns 0. Bit 6—Erasure Mode Related Setting Error Detect (MD): Returns the check result of whether the error protection state has been entered.

  • Page 723: System Control Register 2 (Syscr2)

    Bit 4—Flash Key Register Error Detect (FK): Returns the check result of FKEY value before start of the erasing processing. Bit 4 Description FKEY setting is normal (FKEY = H'5A) FKEY setting is error (FKEY = value other than H'5A) Bit 3—Erase Block Select Error Detect (EB): Returns the check result whether the specified erase-block number is in the block range of the user MAT.

  • Page 724: Ram Emulation Register (Ramer)

    Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FCCS, FPCS, FECS, FKEY, FMATS, FTDAR). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
  • Page 725 Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected. Bit 3 RAMS Description Emulation not selected (Initial value) Program/erase-protection of all flash memory blocks is disabled Emulation selected Program/erase-protection of all flash memory blocks is enabled Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together...

  • Page 726: On-Board Programming Mode

    17.24 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has three operating modes: user programming mode, user boot mode, and boot mode.
  • Page 727 This LSI Control command, Flash analysis execution memory software (on-chip) Host Boot Control command, program data programming RxD1 tool and program On-chip SCI1 On-chip RAM data TxD1 Reply response Figure 17-65 System Configuration in Boot Mode SCI Interface Setting by Host: When boot mode is initiated, this LSI measures the low period of asynchronous SCI-communication data (H'00), which is transmitted consecutively by the host.
  • Page 728 State Transition: The overview of the state transition after boot mode is initiated is shown in figure 17-67. For details on boot mode, refer to section 17.29.1, Serial Communications Interface Specification for Boot Mode. [1] Bit rate adjustment After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host. [2] Waiting for inquiry set command For inquiries about user-MAT size and configuration, MAT start address, and support state, the required information is transmitted to the host.

  • Page 729: 17.24.2 User Program Mode

    (Bit rate adjustment) H'00 to H'00 reception H'00 transmission (adjustment completed) Boot mode initiation Bit rate adjustment (reset by boot mode) Inquiry command reception Processing of Wait for inquiry inquiry setting setting command command Inquiry command response All user MAT and user boot MAT erasure Read/check command reception...
  • Page 730 damage or destroy flash memory. If reset is executed accidentally, reset must be released after the reset input period, which is longer than normal 100 µs. For information on the programming procedure refer to "Programming Procedure in User Program Mode", and for information on the erasing procedure refer to "Erasing Procedure in User Program Mode", below.
  • Page 731 <On-chip RAM> Address RAMTOP(H'FFBC00) Area that can be used by user FTDAR setting DPFR (Return value: 1 byte) System use area (15 bytes) Area to be downloaded FTDAR setting+16 Programming/erasing entry (Size: 4 kbytes) FTDAR setting+32 Unusable area in Initialization process entry programming/erasing processing period Initialization + programming...
  • Page 732 Start programming procedure program Select on-chip program Disable interrupts and bus to be downloaded and master operation other set download destination than CPU by FTDAR Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and Set parameter to ER0 and execute download ER1 (FMPAR and FMPDR) Clear FKEY to 0...
  • Page 733 (a) Select the on-chip program to be downloaded and the download destination. When the PPVS bit of FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are set, download is not performed and a download error is returned to the source select error detect (SS) bit in the DPFR parameter.
  • Page 734 When hardware standby mode is entered during download processing, the normal download cannot be guaranteed in the on-chip RAM. Therefore, download must be executed again. Since a stack area of a maximum 128 bytes is used, the area must be saved before setting the SCO bit to 1.
  • Page 735 (g) Initialization When a programming program is downloaded, the initialization program is also downloaded to the on-chip RAM. There is an entry point of the initialization program in the area from (download start address set by FTDAR) + 32 bytes. The subroutine is called and initialization is executed by using the following steps.
  • Page 736 (k) The parameter which is required for programming is set. The start address of the programming destination of the user MAT (FMPAR) is set to general register ER1. The start address of the program data storage area (FMPDR) is set to general register ER0.
  • Page 737 (o) After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a power-on reset immediately after user MAT programming has finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 µs. Erasing Procedure in User Program Mode: The procedures for download, initialization, and erasing are shown in figure 17-71.
  • Page 738 A single divided block is erased by one erasing processing. For block divisions, refer to figure 17- 63, Block Division of User MAT. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (a) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1.
  • Page 739 (4) Erasing and Programming Procedure in User Program Mode By changing the on-chip RAM address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 17-72 shows an example of repetitively executing RAM emulation, erasing, and programming.

  • Page 740: 17.24.3 User Boot Mode

    In this kind of operation, note the following: • Be careful not to damage on-chip RAM with overlapped settings. In addition to the RAM emulation area, erasing program area, and programming program area, areas for the user procedure programs, work area, and stack area are reserved in on-chip RAM. Do not make settings that will overwrite data in these areas.
  • Page 741 Start programming procedure program Select on-chip program Set FMATS to value other than to be downloaded and H'AA to select user MAT switchover set download destination by FTDAR Set FKEY to H'A5 Set FKEY to H'5A Set SCO to 1 and execute download Set parameter to ER0 and ER1 (FMPAR and FMPDR)
  • Page 742 The area that can be executed in the steps of the user procedure program (on-chip RAM, user MAT, and external space) is shown in section 17.29.3, Procedure Program and Storable Area for Programming Data. User MAT Erasing in User Boot Mode: For erasing the user MAT in user boot mode, additional processings made by setting FMATS are required: switching from user-boot-MAT selection state to user-MAT selection state, and switching back to user-boot-MAT selection state after erasing completes.

  • Page 743: Protection

    MAT switching is completed finished, and if an interrupt occurs, from which MAT the interrupt vector is read from is undetermined. Perform MAT switching in accordance with the description in section 17.27, Switching between User MAT and User Boot MAT. Except for MAT switching, the erasing procedure is the same as that in user program mode.

  • Page 744: Hardware Protection

    Table 17-54 Hardware Protection Function to be Protected Item Description Download Program/Erase • Reset/standby A power-on reset (including a power- protection on reset by the WDT) and entry to standby mode reinitialize the program/erase interface register and the device enters a program/erase- protected state.

  • Page 745: Software Protection

    Table 17-55 Software Protection Function to be Protected Item Description Download Program/Erase • Protection by the Clearing the SCO bit in the FCCS SCO bit register makes the device enter a program/erase-protected state, and this disables the downloading of the programming/erasing programs.
  • Page 746 Error protection is cancelled only by a power-on reset or by hardware-standby mode. Note that the reset should only be released after providing a reset input over a period longer than the normal 100 µs period. Since high voltages are applied during programming/erasing of the flash memory, some voltage may remain after the error-protection state has been entered.

  • Page 747: Flash Memory Emulation In Ram

    17.26 Flash Memory Emulation in RAM To provide real-time emulation in RAM of data that is to be written to the flash memory, a part of the RAM can be overlaid on an area of flash memory (user MAT) that has been specified by the RAM emulation register (RAMER).
  • Page 748 This area is accessible as both a RAM area and as a flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'FFBC00 H'05000 H'06000 H'07000 H'FFDC00 H'08000 H'FFEBFF Flash memory On-chip RAM (user MAT) EB8 to EB15 H'7FFFF H'FFFBFF Figure 17-77 Example of a RAM-Overlap Operation Figure 17-77 shows an example of an overlap on block area EB0 of the flash memory.
  • Page 749 [1] Cancel the emulation mode. [2] Transfer the user-created program/ H'00000 erase-procedure program. [3] Download the on-chip programming/erasing H'01000 programs, avoiding the tuning <illegible> data area set in FTDAR. H'02000 [4] Execute programming after erasing, as necessary. H'03000 H'04000 H'05000 H'06000 H'07000 H'FFBC00...

  • Page 750: Switching Between User Mat And User Boot Mat

    17.27 Switching between User MAT and User Boot MAT It is possible to alternate between the user MAT and user boot MAT. However, the following procedure is required because these MATs are allocated to address 0. (Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or PROM mode.) (1) MAT switching by the FMATS register should always be executed from the on-chip RAM.

  • Page 751: 17.27.1 Usage Notes

    < User MAT > < On-chip RAM > < User boot MAT > Procedure for switching to the user boot MAT Procedure for switching to the user MAT Procedure for switching to the user boot MAT [1] Mask interrupts [2] Write H'AA to the FMATS register. [3] Execute 4 NOP instructions before accessing the user boot MAT.
  • Page 752 4. Monitoring runaway by WDT Unlike the conventional F-ZTAT H8S microcomputer, no countermeasures are available for a runaway by WDT during programming/erasing by the downloaded on-chip program. Prepare countermeasures (e.g. use of the user branch routine and periodic timer interrupts) for WDT while taking the programming/erasing time into consideration as required.

  • Page 753: Prom Mode

    ROM. Program/erase is possible on the user MAT and user boot MAT. The PROM programmer must support Renesas Technology microcomputers with 512-kbyte flash memory units as a device type.
  • Page 754 Address in Address in Address in Address in MCU mode PROM mode MCU mode PROM mode H'000000 H'00000 H'000000 H'00000 On-chip ROM space (user boot MAT) 8 kbytes H'001FFF H'01FFF On-chip ROM space (user MAT) 512 kbytes H'07FFFF H'7FFFF Figure 17-80 Mapping of On-Chip Flash Memory Rev.
  • Page 755 H8S/2319 C F-ZTAT HN27C4096HG (40 pins) Socket Adapter TFP-100B FP-100A Pin No. Pin Name Pin Name (40-Pin Conversion) I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 × Capacitor 1, 40 40. 63, 64, 65, 74, 42, 65, 66, 67, 76, 77, 78, 98, 59 79, 80, 100, 61 11, 30...

  • Page 756: 17.28.2 Prom Mode Operation

    17.28.2 PROM Mode Operation Table 17-57 shows the settings for the operating modes of PROM mode, and table 17-58 lists the commands used in PROM mode. The following sections provide detailed information on each mode. • Memory-read mode: This mode supports reading, in units of bytes, from the user MAT or user boot MAT.

  • Page 757: 17.28.3 Memory-Read Mode

    Table 17-58 Commands in PROM Mode Memory 1st Cycle 2nd Cycle Number MAT to be Command of Cycles Accessed Mode Address Data Mode Address Data Memory-read User MAT Write H'00 Read Dout mode User boot Write H'05 Auto-program User MAT Write H'40 Write...

  • Page 758: 17.28.5 Auto-Erase Mode

    (4) The memory address is transferred in the 2nd cycle. Do not transfer addresses in the 3rd or later cycles. (5) Do not issue commands while programming is in progress. (6) When programming, execute automatic programming once for each 128-byte block of addresses.

  • Page 759: 17.28.7 Status Polling

    Table 17-59 Return Codes of Status-Read Mode Pin Name Attribute Normal end Command Programming Erase error — — Programming Invalid indicator error error or erase count address exceeded error Initial value 0 Indication Normal Command Programming Erase — — Count Invalid end: 0 error: 1...
  • Page 760 100 µs. (4) The flash memory is initially in the erased state when the device is shipped by Renesas Technology. For other chips for which the history of erasure is unknown, auto-erasing as a check and supplement for the initialization (erase) level is recommended.

  • Page 761: Further Information

    17.29 Further Information 17.29.1 Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the internal SCI. The serial communication interface specification is shown below. Status The boot program has three states. (1) Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host.
  • Page 762 Reset Bit-Rate-Adjustment State Inquiry Selection Inquiry/Selection wait Operations for Operations for Transition to Inquiry Selection Programming/erasing Operations for Erasing User MATs and User Boot MATs Programming/erasing selection wait Programming Erasing Checking Operations for Operations for Programming Erasing Operations for Checking Figure 17-82 Boot Program States Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the...
  • Page 763 Host Boot Program H'00 (30 times maximum) Measuring the 1-Bit Length H'00 (Completion of Adjustment) H'55 H'E6 (Response to Boot) H'FF (Error) Figure 17-83 Bit-Rate-Adjustment Sequence Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below.
  • Page 764 One-Byte Command Command or Response or One-Byte Response n-Byte Command or Data n-Byte Response Size Checksum Command or Response Error Response Error Code Error Response Address Data (n bytes) 128-Byte Programming Command Checksum Memory Read Size Data Response Response Checksum Figure 17-84 Communication Protocol Format •...
  • Page 765 Inquiry and Selection States The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed below. Table 17-61 Inquiry and Selection Commands Command Command Name...
  • Page 766 the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid after the boot program has received the programming/erasing transition command (H'40). (1) Supported device inquiry The boot program will return the device codes of supported devices and the product code of the F-ZTAT in response to the supported device inquiry.
  • Page 767 Response H'06 • Response, H'06, (1 byte): Response to the device selection command ACK will be returned when the device code matches. Error H'90 ERROR response • Error response, H'90, (1 byte): Error response to the device selection command • Error: (1 byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (3) Clock Mode Inquiry...
  • Page 768 Error H'91 ERROR Response • Error response, H'91, (1 byte): Error response to the clock mode selection command • ERROR, (1 byte) : Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match. Even when the clock mode value is H'00 or H'01 for clock mode inquiry, clock mode selection is performed for each value.
  • Page 769 (6) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values. Command H'23 • Command, H'23, (1 byte): Inquiry regarding operating clock frequencies Response H'33 Size A number of operating clock frequencies The minimum value of The maximum value of operating clock...
  • Page 770 Response H'34 Size A Number of Areas Area-Start Address Area-Last Address ··· • Response, H'34, (1 byte): Response to user boot MAT information inquiry • Size (1 byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address •...
  • Page 771 (9) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses. Command H'26 • Command, H'26, (1 byte): Inquiry regarding erased block information Response H'36 Size A number of blocks Block Start Address Block Last Address ···...
  • Page 772 (11) New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command. Command H'3F Size Bit rate Input frequency Number of Multiplication Multiplication multiplication ratios...
  • Page 773 Response H'06 • Response, H'06, (1 byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error H'BF ERROR Response • Error response, H'BF, (1 byte): Error response to selection of new bit rate •...
  • Page 774 The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated. (4) Bit rate Peripheral operating clock (φ), bit rate (B), clock select (CKS) in the serial mode register (SMR).
  • Page 775 Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clock- mode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state.
  • Page 776 Command Order The order for commands in the inquiry selection state is shown below. (1) A supported device inquiry (H'20) should be made to inquire about the supported devices. (2) The device should be selected from among those described by the returned information and set with a device-selection (H'10) command.
  • Page 777 Table 17-62 Programming/Erasing Command Command Command Name Description H'42 User boot MAT programming Transfers the user boot MAT programming selection program H'43 User MAT programming selection Transfers the user MAT programming program H'50 128-byte programming Programs 128 bytes of data H'48 Erasing selection Transfers the erasing program...
  • Page 778 The sequence for programming-selection and 128-byte programming commands is shown in figure 17-86. Host Boot program Programming selection (H'42, H'43, H'44) Transfer of the programming program 128-byte programming (address, data) Repeat Programming 128-byte programming (H'FFFFFFFF) Figure 17-86 Programming Sequence (2) User Boot MAT Programming Selection The boot program will transfer a programming program.
  • Page 779 (3) User MAT Programming Selection. The boot program will transfer a programming program. The data is programmed to the user MATs by the transferred programming program. Command H'43 • Command, H'43, (1 byte): User-program programming selection Response H'06 • Response, H'06, (1 byte): Response to user-program programming selection When the programming program has been transferred, the boot program will return ACK.
  • Page 780 Error H'D0 ERROR Response • Error response, H'D0, (1 byte): Error response for 128-byte programming • ERROR: (1 byte): Error code H'11: Checksum Error H'28: Address error The address is not within the specified range. H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data.
  • Page 781 Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased.
  • Page 782 Error H'C8 ERROR Response • Error response: H'C8 (1 byte): Error response to erasing selection • ERROR: (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (2) Block Erasure The boot program will erase the contents of the specified block. Command H'58 Size...
  • Page 783 Response H'06 • Response, H'06, (1 byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command. Memory Read The boot program will return the data in the specified address. Command H'52 Size...
  • Page 784 User-Boot Program Sum Check The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program. Command H'4A • Command, H'4A, (1 byte): Sum check for user-boot program Response H'5A Size Checksum of user boot program •...
  • Page 785 Error H'CC H'52 Response • Error Response, H'CC, (1 byte): Response to blank check for user boot MAT • Error Code, H'52, (1 byte): Erasure has not been completed. User MAT Blank Check The boot program will check whether or not all user MATs are blank and return the result. Command H'4D •...
  • Page 786 Table 17-63 Status Code Code Description H'11 Device Selection Wait H'12 Clock Mode Selection Wait H'13 Bit Rate Selection Wait H'IF Programming/Erasing State Transition Wait (Bit rate selection is completed) H'31 Programming State for Erasure H'3F Programming/Erasing Selection Wait (Erasure is completed) H'4F Programming Data Receive Wait (Programming is completed) H'5F...

  • Page 787: 17.29.2 Ac Characteristics And Timing In Prom Mode

    17.29.2 AC Characteristics and Timing in PROM Mode Table 17-65 AC Characteristics in Memory Read Mode Condition: V = 3.3 V ± 0.3 V, V = 0 V, T = 25˚C ± 5˚C Code Symbol Unit µs Command write cycle —...
  • Page 788 Table 17-66 AC Characteristics in Transition from Memory Read Mode to Others Condition: V = 3.3 V ± 0.3 V, V = 0 V, T = 25˚C ± 5˚C Code Symbol Unit µs Command write cycle — nxtc CE hold time —...
  • Page 789 Table 17-67 AC Characteristics Memory Read Mode Condition: V = 3.3 V ± 0.3 V, V = 0 V, T = 25˚C ± 5˚C Code Symbol Unit µs Access time — CE output delay time — OE output delay time —...
  • Page 790 Table 17-68 AC Characteristics Auto-PROM Mode Condition: V = 3.3 V ± 0.3 V, V = 0 V, T = 25˚C ± 5˚C Code Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time — Data hold time —...
  • Page 791 Table 17-69 AC Characteristics Auto-Erase Mode Condition: V = 3.3 V ± 0.3 V, V = 0 V, T = 25˚C ± 5˚C Code Symbol Unit µs Command write cycle — nxtc CE hold time — CE setup time — Data hold time —...
  • Page 792 Table 17-70 AC Characteristics Status Read Mode Condition: V = 3.3 V ± 0.3 V, V = 0 V, T = 25˚C ± 5˚C Code Symbol Unit µs Command write cycle nxtc CE hold time CE setup time Data hold time Data setup time Programming pulse width OE output delay time...

  • Page 793: 17.29.3 Procedure Program And Storable Area For Programming Data

    Command wait state Memory read mode Auto-program mode Normal/abnormal Command wait state Auto-erase mode end identification osc1 Command acceptance Figure 17-95 Oscillation Stabilization Time, PROM Mode Setup Time, and Power-Down Sequence 17.29.3 Procedure Program and Storable Area for Programming Data In the descriptions in the previous section, the programming/erasing procedure programs and storable areas for program data are assumed to be in the on-chip RAM.
  • Page 794 executed from the on-chip RAM. See section 17.27, Switching between User MAT and User Boot MAT. Please make sure you know which MAT is selected when switching between them. (8) When the data storable area indicated by programming parameter FMPDR is within the flash memory area, an error will occur even when the data stored is normal.
  • Page 795 Table 17-73 (1) Useable Area for Programming in User Program Mode Storable/Executable Area Selected MAT External Space Embedded Item On-chip User User (Expanded Program Mode) Storage Area × * Storage Area for Program — — Data Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5...
  • Page 796 Table 17-73 (2) Useable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT External Space Embedded Item On-chip User User (Expanded Program Mode) Storage Area Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5 to Key Register ×...
  • Page 797 Table 17-73 (3) Useable Area for Programming in User Boot Mode Storable/Executable Area Selected MAT User External Space User Embedded Item On-chip User Boot (Expanded Boot Program Mode) Storage Area × * Storage Area for Program — — — Data Operation for Selection of On-chip Program to be Downloaded...
  • Page 798 Table 17-73 (4) Useable Area for Erasure in User Boot Mode Storable/Executable Area Selected MAT User External Space User Embedded Item On-chip User Boot (Expanded Boot Program Mode) Storage Area Operation for Selection of On-chip Program to be Downloaded Operation for Writing H'A5 to Key Register ×...

  • Page 799: Section 18 Clock Pulse Generator

    Section 18 Clock Pulse Generator 18.1 Overview The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium- speed clock divider, and a bus master clock selection circuit.

  • Page 800: Register Configuration

    18.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 18-1 shows the register configuration. Table 18-1 Clock Pulse Generator Register Address * Name Abbreviation Initial Value System clock control register SCKCR H'00 H'FF3A Note: * Lower 16 bits of the address. 18.2 Register Descriptions 18.2.1...
  • Page 801 • The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the guaranteed operation range of clock cycle time tcyc given in the AC timing table in the Electrical Characteristics section. Ensure that φ min = 2 MHz, and the condition φ < 2 MHz does not arise.

  • Page 802: Oscillator

    Description Bit 2 Bit 1 Bit 0 DIV = 0 DIV = 1 SCK2 SCK1 SCK0 Bus master is in high-speed Bus master is in high-speed mode (Initial value) mode (Initial value) Medium-speed clock is φ/2 Clock supplied to entire chip is φ/2 Medium-speed clock is φ/4 Clock supplied to entire chip is φ/4 Medium-speed clock is φ/8...
  • Page 803 XTAL EXTAL AT-cut parallel-resonance type Figure 18-3 Crystal Resonator Equivalent Circuit Table 18-3 Crystal Resonator Characteristics Frequency (MHz) max (Ω Ω Ω Ω ) max (pF) Notes on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation.

  • Page 804: External Clock Input

    18.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18-5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL External clock input XTAL...
  • Page 805 Table 18-4 External Clock Input Conditions = 2.7 V = 3.0 V to 3.3 V to 3.6 V Test Item Symbol Unit Conditions External clock input — — Figure 18-6 low pulse width External clock input — — high pulse width External clock rise time t —...

  • Page 806: Duty Adjustment Circuit

    18.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 18.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. 18.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed...

  • Page 807: Section 19 Power-Down Modes

    Section 19 Power-Down Modes 19.1 Overview In addition to the normal program execution state, the chip has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on.

  • Page 808: Register Configuration

    Table 19-1 Operating Modes Modules Operating Transition Clearing Mode Condition Condition Oscillator Registers Registers I/O Ports High speed Control Functions High Function High Function High speed mode register speed speed Medium- Control Functions Medium Function High/ Function High speed speed mode register speed medium...

  • Page 809: Register Descriptions

    19.2 Register Descriptions 19.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — IRQ37S Initial value : — — SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode.
  • Page 810 Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description Standby time = 8192 states (Initial value) Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states * Note: * Not available in the F-ZTAT versions.

  • Page 811: System Clock Control Register (Sckcr)

    19.2.2 System Clock Control Register (SCKCR) PSTOP — — — SCK2 SCK1 SCK0 Initial value : — — SCKCR is an 8-bit readable/writable register that controls φ clock output, the medium-speed mode in which the bus master runs on a medium-speed clock and the other supporting modules run on the high-speed clock, and a function that allows the medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
  • Page 812 • The division ratio can be changed while the chip is operating. The clock output from the φ pin will also change when the division ratio is changed. The frequency of the clock output from the φ pin in this case will be as follows: φ...

  • Page 813: Module Stop Control Register (Mstpcr)

    19.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode.

  • Page 814: Medium-Speed Mode

    19.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DTC) also operate in medium-speed mode.

  • Page 815: Sleep Mode

    19.4 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state.

  • Page 816: Usage Notes

    Table 19-3 MSTP Bits and Corresponding On-Chip Supporting Modules Register Module MSTPCRH MSTP15 — MSTP14 Data transfer controller (DTC) MSTP13 16-bit timer-pulse unit (TPU) MSTP12 8-bit timer module MSTP11 — MSTP10 D/A converter (channels 0 and 1) MSTP9 A/D converter MSTP8 —...

  • Page 817: Software Standby Mode

    19.6 Software Standby Mode 19.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained.

  • Page 818: Setting Oscillation Stabilization Time After Clearing Software Standby Mode

    19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time).

  • Page 819: Usage Notes

    Oscillator φ NMIEG SSBY NMI exception Software standby mode NMI exception Oscillation handling (power-down mode) handling stabilization NMIEG=1 time t SSBY=1 OSC2 SLEEP instruction Figure 19-2 Software Standby Mode Application Example 19.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained.

  • Page 820: Hardware Standby Mode

    19.7 Hardware Standby Mode 19.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation.

  • Page 821: Φ Clock Output Disabling Function

    Oscillator STBY Oscillation Reset stabilization exception time handling Figure 19-3 Hardware Standby Mode Timing φ φ φ φ Clock Output Disabling Function 19.8 Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port.
  • Page 822 Rev. 5.00, 12/03, page 792 of 1088...

  • Page 823: Section 20 Electrical Characteristics

    Section 20 Electrical Characteristics 20.1 Electrical Characteristics of Mask ROM Versions (H8S/2319, H8S/2318, H8S/2317, H8S/2316, H8S/2313, H8S/2311) and ROMless Versions (H8S/2312S, H8S/2310) 20.1.1 Absolute Maximum Ratings Table 20-1 lists the absolute maximum ratings. Table 20-1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage...

  • Page 824: Dc Characteristics

    20.1.2 DC Characteristics Table 20-2 DC Characteristics Conditions: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V * = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide- range specifications) Test...
  • Page 825 Test Item Symbol Min Unit Conditions µA Input pull-up Ports A to E –I — = 0V MOS current Input — — = 0 V capacitance — — f = 1 MHz All input pins — — = 25°C except RES and Current Normal operation —...

  • Page 826: Ac Characteristics

    Table 20-3 Permissible Output Currents Conditions: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Item Symbol...
  • Page 827 (1) Clock Timing Table 20-4 Clock Timing Condition A: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, φ = 2 MHz to 20 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Condition B: V...
  • Page 828 φ Figure 20-2 System Clock Timing EXTAL DEXT DEXT STBY OSC1 OSC1 φ Figure 20-3 Oscillation Stabilization Timing Rev. 5.00, 12/03, page 798 of 1088...
  • Page 829 (2) Control Signal Timing Table 20-5 Control Signal Timing Condition A: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, φ = 2 MHz to 20 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Condition B: V...
  • Page 830 φ RESS RESS RESW Figure 20-4 Reset Input Timing φ NMIS NMIH NMIW IRQW IRQS IRQH edge input IRQS level input Figure 20-5 Interrupt Input Timing Rev. 5.00, 12/03, page 800 of 1088...
  • Page 831 (3) Bus Timing Table 20-6 Bus Timing Condition A: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, φ = 2 MHz to 20 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Condition B: V...
  • Page 832 Condition A Condition B Item Symbol Unit Test Conditions WR delay time 1 — — Figures 20-6 to 20-10 WRD1 WR delay time 2 — — WRD2 WR pulse width 1 1.0 × 1.0 × — — WSW1 – 20 –...
  • Page 833 φ A23 to A0 CSD1 CS7 to CS0 RSD1 ACC2 RSD2 (read) ACC3 D15 to D0 (read) WRD2 WRD2 HWR, LWR (write) WSW1 D15 to D0 (write) Figure 20-6 Basic Bus Timing (2-State Access) Rev. 5.00, 12/03, page 803 of 1088...
  • Page 834 φ A23 to A0 CSD1 CS7 to CS0 RSD1 RSD2 ACC4 (read) ACC5 D15 to D0 (read) WRD1 WRD2 HWR, LWR (write) WSW2 D15 to D0 (write) Figure 20-7 Basic Bus Timing (3-State Access) Rev. 5.00, 12/03, page 804 of 1088...
  • Page 835 φ A23 to A0 CS7 to CS0 (read) D15 to D0 (read) HWR to LWR (write) D15 to D0 (write) WAIT Figure 20-8 Basic Bus Timing (3-State Access, 1 Wait) Rev. 5.00, 12/03, page 805 of 1088...
  • Page 836 or T φ A23 to A0 RSD2 (read) ACC3 D15 to D0 (read) Figure 20-9 Burst ROM Access Timing (2-State Access) Rev. 5.00, 12/03, page 806 of 1088...
  • Page 837 or T φ A23 to A0 RSD2 (read) ACC1 D15 to D0 (read) Figure 20-10 Burst ROM Access Timing (1-State Access) Rev. 5.00, 12/03, page 807 of 1088...
  • Page 838 φ BRQS BRQS BREQ BACD BACD BACK A23 to A0, CS7 to CS0, AS, RD, HWR, LWR Figure 20-11 External Bus Release Timing φ BRQOD BRQOD BREQO Figure 20-12 External Bus Request Output Timing Rev. 5.00, 12/03, page 808 of 1088...
  • Page 839 (4) Timing of On-Chip Supporting Modules Table 20-7 Timing of On-Chip Supporting Modules Condition A: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, φ = 2 MHz to 20 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Condition B: V...
  • Page 840 Condition A Condition B Test Item Symbol Unit Conditions Input clock Asynchronous t — — Figure 20-20 Scyc cycle Synchronous — — Input clock pulse width SCKW Scyc Input clock rise time — — SCKr Input clock fall time — —...
  • Page 841 φ TOCD Output compare output * TICS Input capture input * Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 20-14 TPU Input/Output Timing φ TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 20-15 TPU Clock Input Timing φ...
  • Page 842 φ TMCS TMCS TMCI0, TMCI1 TMCWL TMCWH Figure 20-17 8-Bit Timer Clock Input Timing φ TMRS TMRI0, TMRI1 Figure 20-18 8-Bit Timer Reset Input Timing φ WOVD WOVD WDTOVF Figure 20-19 WDT Output Timing SCKW SCKr SCKf SCK0, SCK1 Scyc Figure 20-20 SCK Clock Input Timing Rev.
  • Page 843 SCK0, SCK1 TxD0, TxD1 (transmit data) RxD0, RxD1 (receive data) Figure 20-21 SCI Input/Output Timing (Synchronous Mode) φ TRGS ADTRG Figure 20-22 A/D Converter External Trigger Input Timing Rev. 5.00, 12/03, page 813 of 1088...

  • Page 844: A/D Conversion Characteristics

    20.1.4 A/D Conversion Characteristics Table 20-8 A/D Conversion Characteristics Condition A: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, φ = 2 MHz to 20 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Condition B: V...

  • Page 845: D/A Conversion Characteristics

    20.1.5 D/A Conversion Characteristics Table 20-9 D/A Conversion Characteristics Condition A: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, φ = 2 MHz to 20 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Condition B: V...

  • Page 846: Electrical Characteristics Of Mask Rom Versions H8S/2318, H8S/2317, H8S/2316, H8S/2313) In Low-Voltage Operation

    20.2 Electrical Characteristics of Mask ROM Versions (H8S/2318, H8S/2317, H8S/2316, H8S/2313) in Low-Voltage Operation 20.2.1 Absolute Maximum Ratings Table 20-10 lists the absolute maximum ratings. Table 20-10 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.3 Input voltage (except port 4) –0.3 to V +0.3...

  • Page 847: Dc Characteristics

    20.2.2 DC Characteristics Table 20-11 DC Characteristics Condition C: V = 2.4 V to 3.6 V, AV = 2.4 V to 3.6 V, V = 2.4 V to AV = AV 0 V * = –20°C to +75°C (regular specifications) Test Item Symbol...
  • Page 848 Test Item Symbol Min Unit Conditions µA Input pull-up Ports A to E –I — = 0V MOS current Input — — = 0 V capacitance NMI — — f = 1 MHz All input pins — — = 25°C except RES and Current Normal operation...

  • Page 849: Ac Characteristics

    Table 20-12 Permissible Output Currents Condition C: V = 2.4 V to 3.6 V, AV = 2.4 V to 3.6 V, V = 2.4 V to AV = AV 0 V, T = –20°C to +75°C (regular specifications) Item Symbol Unit Permissible output All output pins...
  • Page 850 (1) Clock Timing Table 20-13 Clock Timing Condition C: V = 2.4 V to 3.6 V, AV = 2.4 V to 3.6 V, V = 2.4 V to AV = AV 0 V, φ = 2 MHz to 14 MHz, T = –20°C to 75°C (regular specifications) Condition C Item...
  • Page 851 (3) Bus Timing Table 20-15 Bus Timing Condition C: V = 2.4 V to 3.6 V, AV = 2.4 V to 3.6 V, V = 2.4 V to AV = AV 0 V, φ = 2 MHz to 14 MHz, T = –20°C to 75°C (regular specifications) Condition C Item...
  • Page 852 (4) Timing of On-Chip Supporting Modules Table 20-16 Timing of On-Chip Supporting Modules Condition C: V = 2.4 V to 3.6 V, AV = 2.4 V to 3.6 V, V = 2.4 V to AV = AV 0 V, φ = 2 MHz to 14 MHz, T = –20°C to 75°C (regular specifications) Condition C Item...

  • Page 853: A/D Conversion Characteristics

    20.2.4 A/D Conversion Characteristics Table 20-17 A/D Conversion Characteristics Condition C: V = 2.4 V to 3.6 V, AV = 2.4 V to 3.6 V, V = 2.4 V to AV = AV 0 V, φ = 2 MHz to 14 MHz, T = –20°C to 75°C (regular specifications) Condition C Item...

  • Page 854: Absolute Maximum Ratings

    20.3 Electrical Characteristics of F-ZTAT Versions (H8S/2319 F-ZTAT, H8S/2319E F-ZTAT, H8S/2318 F-ZTAT, H8S/2317 F-ZTAT, H8S/2315 F-ZTAT, H8S/2314 F-ZTAT) 20.3.1 Absolute Maximum Ratings Table 20-19 Absolute Maximum Ratings Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, T...

  • Page 855: Dc Characteristics

    20.3.2 DC Characteristics Table 20-20 DC Characteristics Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item...
  • Page 856 Test Item Symbol Unit Conditions µA Input pull-up Ports A to E –I — = 3.0 V MOS current to 3.6 V, = 0 V Input — — = 0 V capacitance — — f = 1 MHz All input pins —...
  • Page 857 Table 20-21 Permissible Output Currents Condition B: V = 3.0 V to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 V to AV = AV = 0 V, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Item Symbol Unit...

  • Page 858: Ac Characteristics

    20.3.3 AC Characteristics (1) Clock Timing Table 20-22 Clock Timing Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...
  • Page 859 (2) Control Signal Timing Table 20-23 Control Signal Timing Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...
  • Page 860 (3) Bus Timing Table 20-24 Bus Timing Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...
  • Page 861 (4) Timing of On-Chip Supporting Modules Table 20-25 Timing of On-Chip Supporting Modules Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...

  • Page 862: A/D Conversion Characteristics

    20.3.4 A/D Conversion Characteristics Table 20-26 A/D Conversion Characteristics Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...

  • Page 863: Flash Memory Characteristics

    20.3.6 Flash Memory Characteristics Table 20-28 Flash Memory Characteristics — Preliminary — Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, T = 0°C to +75°C (program/erase operating temperature range: regular specifications), T = 0°C to +85°C (program/erase operating temperature range: wide-range specifications)
  • Page 864 register 1 (FLMCR1) is set. In the H8S/2319, indicates the total time during which the P1 bit and P2 bit in the flash memory control registers (FLMCR1, FLMCR2) are set. Does not include the program-verify time.) 3. Time to erase one block. (In the H8S/2318, H8S/2317, H8S/2315, and H8S/2314, indicates the total time during which during which the E1 bit in FLMCR1 and the E2 bit in FLMCR2 are set.

  • Page 865: Electrical Characteristics Of F-Ztat Version (H8S/2319C F-Ztat) (In Planning)

    20.4 Electrical Characteristics of F-ZTAT Version (H8S/2319C F-ZTAT) (In planning) 20.4.1 Absolute Maximum Ratings Table 20-29 Absolute Maximum Ratings — Preliminary— Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, T = –20°C to 75°C (regular specifications), T...

  • Page 866: Dc Characteristics

    20.4.2 DC Characteristics Table 20-30 DC Characteristics — Preliminary— Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = 0 V * = AV = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item...
  • Page 867 Test Item Symbol Unit Conditions µA Input pull-up Ports A to E –I — = 3.0 V MOS current to 3.6 V, = 0 V Input — — = 0 V capacitance — — f = 1 MHz All input pins —...
  • Page 868 Table 20-31 Permissible Output Currents — Preliminary— Condition B: V = 3.0 V to 3.6 V, AV = 3.0 to 3.6 V, V = 3.0 V to AV = AV = 0 V, T = –20 to +75°C (regular specifications), = –40 to +85°C (wide-range specifications) Item Symbol...

  • Page 869: Ac Characteristics

    20.4.3 AC Characteristics (1) Clock Timing Table 20-32 Clock Timing — Preliminary— Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...
  • Page 870 (2) Control Signal Timing Table 20-33 Control Signal Timing — Preliminary — Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...
  • Page 871 (3) Bus Timing Table 20-34 Bus Timing — Preliminary — Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...
  • Page 872 (4) Timing of On-Chip Supporting Modules Table 20-35 Timing of On-Chip Supporting Modules — Preliminary — Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ...

  • Page 873: A/D Conversion Characteristics

    20.4.4 A/D Conversion Characteristics Table 20-36 A/D Conversion Characteristics — Preliminary — Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, φ = 2 MHz to 25 MHz, T = –20°C to 75°C (regular specifications), = –40°C to 85°C (wide-range specifications) Item...

  • Page 874: Flash Memory Characteristics

    20.4.6 Flash Memory Characteristics Table 20-38 Flash Memory Characteristics — Preliminary — Condition B: V = 3.0 V to 3.6 V, AV = 3.0 V to 3.6 V, V = 3.0 V to AV = AV 0 V, T = 0°C to +75°C (program/erase operating temperature range: regular specifications), T = 0°C to +85°C (program/erase operating temperature range: wide-range specifications)

  • Page 875: Usage Note

    External capacitor to stabilize the power supply 0.1 µF Do not connect the V power-supply to the V pin. Doing so could permanently damage the LSI. (Connect the V power-supply to the V pin, in the usual way.) Use a multilayer ceramic capacitor (0.1 µF), and place it near the pins.
  • Page 876 Rev. 5.00, 12/03, page 846 of 1088...

  • Page 877: Appendix A Instruction Set

    Appendix A Instruction Set Instruction List Operand Notation General register (destination) * General register (source) * General register * General register (32-bit register) Multiply-and-accumulate register (32-bit register) * (EAd) Destination operand (EAs) Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR...
  • Page 878 Condition Code Notation Symbol Changes according to the result of the instruction Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 — Not affected by execution of the instruction Rev. 5.00, 12/03, page 848 of 1088...
  • Page 879 Table A-1 Instruction Set Rev. 5.00, 12/03, page 849 of 1088...
  • Page 880 Rev. 5.00, 12/03, page 850 of 1088...
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  • Page 899 Rev. 5.00, 12/03, page 869 of 1088...
  • Page 900 Rev. 5.00, 12/03, page 870 of 1088...

  • Page 901: Instruction Codes

    Instruction Codes Table A-2 shows the instruction codes. Rev. 5.00, 12/03, page 871 of 1088...
  • Page 902 Table A-2 Instruction Codes Rev. 5.00, 12/03, page 872 of 1088...
  • Page 903 Rev. 5.00, 12/03, page 873 of 1088...
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  • Page 911 Rev. 5.00, 12/03, page 881 of 1088...
  • Page 912 Rev. 5.00, 12/03, page 882 of 1088...
  • Page 913 Rev. 5.00, 12/03, page 883 of 1088...
  • Page 914 Rev. 5.00, 12/03, page 884 of 1088...
  • Page 915 Rev. 5.00, 12/03, page 885 of 1088...

  • Page 916: Operation Code Map

    Operation Code Map Table A-3 shows the operation code map. Table A-3 Operation Code Map (1) Rev. 5.00, 12/03, page 886 of 1088...
  • Page 917 Table A-3 Operation Code Map (2) Rev. 5.00, 12/03, page 887 of 1088...
  • Page 918 Table A-3 Operation Code Map (3) Rev. 5.00, 12/03, page 888 of 1088...
  • Page 919 Table A-3 Operation Code Map (4) Rev. 5.00, 12/03, page 889 of 1088...

  • Page 920: Number Of States Required For Instruction Execution

    Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle.
  • Page 921 Table A-4 Number of States per Cycle Access Conditions External Device On-Chip Supporting 8-Bit Bus 16-Bit Bus Module On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation Byte data access 3 + m...
  • Page 922 Table A-5 Number of Cycles in Instruction Execution Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd...
  • Page 923 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16...
  • Page 924 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8...
  • Page 925 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16...
  • Page 926 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16...
  • Page 927 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic 2n+2 * EEPMOV EEPMOV.B 2n+2 * EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 JMP @@aa:8...
  • Page 928 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH Cannot be used in the chip LDMAC ERs,MACL MAC @ERn+,@ERm+ Cannot be used in the chip MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd...
  • Page 929 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd)
  • Page 930 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd...
  • Page 931 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd 2/3 * SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR...
  • Page 932 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) 3 STC.W EXR,@(d:16,ERd) 3 STC.W CCR,@(d:32,ERd) 5 STC.W EXR,@(d:32,ERd) 5 STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32...
  • Page 933 Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. The number of state cycles is 2 when EXR is invalid, and 3 when EXR is valid. 2.

  • Page 934: Bus States During Instruction Execution

    Bus States during Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction Internal operation, JMP@aa:24 R:W 2nd R:W EA...
  • Page 935 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus HWR, LWR High Internal R:W 2nd R:W EA operation...
  • Page 936 Table A-6 Instruction Execution Cycles Rev. 5.00, 12/03, page 906 of 1088...
  • Page 937 Rev. 5.00, 12/03, page 907 of 1088...
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  • Page 944 Rev. 5.00, 12/03, page 914 of 1088...
  • Page 945 Rev. 5.00, 12/03, page 915 of 1088...
  • Page 946 Rev. 5.00, 12/03, page 916 of 1088...
  • Page 947 Rev. 5.00, 12/03, page 917 of 1088...

  • Page 948: Condition Code Modification

    Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand...
  • Page 949 Table A-7 Condition Code Modification Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
  • Page 950 Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
  • Page 951 Instruction Definition — — N = Rm Z = Rm · Rm–1 · ..· R0 MOVFPE Cannot be used in the chip MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ..· R0 MULXU —...
  • Page 952 Instruction Definition ROTXL — N = Rm Z = Rm · Rm–1 · ..· R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — N = Rm Z = Rm · Rm–1 · ..· R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) Stores the corresponding bits of the result.
  • Page 953 Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...

  • Page 954: Appendix B Internal I/O Registers

    Appendix B Internal I/O Registers List of Registers (Address Order) Data Register Module Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width 16/32 * H'F800 bits H'FBFF CHNE DISEL CHNS —...
  • Page 955 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FE90 TCR4 — CCLR1 CCLR0 CKEG CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16 bits H'FE91 TMDR4 — — —...
  • Page 956 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FEC4 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Interrupt 8 bits controller H'FEC5 IPRB — IPR6 IPR5 IPR4...
  • Page 957 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYSCR2 * H'FF42 — — — — FLSHE — — — Flash 8 bits memory H'FF44 Reserved — —...
  • Page 958 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FF78 SMR0 C/A/ CHR/ STOP/ CKS1 CKS0 SCI0, 8 bits GM * BLK * BCP1 * BCP0 * smart card interface 0 H'FF79...
  • Page 959 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFA4 DADR0 8 bits converter H'FFA5 DADR1 H'FFA6 DACR01 DAOE1 DAOE0 — — — — — H'FFAC PFCR2 —...
  • Page 960 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFC8 * FLMCR1 Flash 8 bits memory H'FFC9 * FLMCR2 FLER — — — — — — —...
  • Page 961 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU0 16 bits H'FFD1 TMDR0 — — H'FFD2 TIOR0H IOB3...
  • Page 962 Data Register Module Name Name Width Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FFF0 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 bits H'FFF1 TMDR2 — — —...

  • Page 963: List Of Registers (By Module)

    List of Registers (By Module) Initial Value Address * Module Register Abbreviation R/W Interrupt System control register SYSCR H'01 H'FF39 controller IRQ sense control register H ISCRH H'00 H'FF2C IRQ sense control register L ISCRL H'00 H'FF2D IRQ enable register H'00 H'FF2E R/(W) *...
  • Page 964 Initial Value Address * Module Register Abbreviation R/W H'FF/H'00 * Bus width control register ABWCR H'FED0 controller Access state control register ASTCR H'FF H'FED1 Wait control register H WCRH H'FF H'FED2 Wait control register L WCRL H'FF H'FED3 Bus control register H BCRH H'D0 H'FED4...
  • Page 965 Initial Value Address * Module Register Abbreviation R/W SCI0 Serial mode register 0 SMR0 H'00 H'FF78 Bit rate register 0 BRR0 H'FF H'FF79 Serial control register 0 SCR0 H'00 H'FF7A Transmit data register 0 TDR0 H'FF H'FF7B R/(W) * Serial status register 0 SSR0 H'84 H'FF7C...
  • Page 966 Initial Value Address * Module Register Abbreviation R/W All SMCI Module stop control register MSTPCR H'3FFF H'FF3C channels A/D data register AH ADDRAH H'00 H'FF90 A/D data register AL ADDRAL H'00 H'FF91 A/D data register BH ADDRBH H'00 H'FF92 A/D data register BL ADDRBL H'00 H'FF93...
  • Page 967 Initial Value Address * Module Register Abbreviation R/W TPU1 Timer I/O control register 1 TIOR1 H'00 H'FFE2 Timer interrupt enable register 1 TIER1 H'40 H'FFE4 R/(W) * Timer status register 1 TSR1 H'C0 H'FFE5 Timer counter 1 TCNT1 H'0000 H'FFE6 Timer general register 1A TGR1A H'FFFF...
  • Page 968 Initial Value Address * Module Register Abbreviation R/W TPU5 Timer control register 5 TCR5 H'00 H'FEA0 Timer mode register 5 TMDR5 H'C0 H'FEA1 Timer I/O control register 5 TIOR5 H'00 H'FEA2 Timer interrupt enable register 5 TIER5 H'40 H'FEA4 R/(W) * Timer status register 5 TSR5 H'C0...
  • Page 969 Initial Value Address * Module Register Abbreviation R/W Power- Standby control register SBYCR H'08 H'FF38 down state Module stop control register H MSTPCRH H'3F H'FF3C Module stop control register L MSTPCRL H'FF H'FF3D Port 1 Port 1 data direction register P1DDR H'00 H'FEB0...
  • Page 970 Initial Value Address * Module Register Abbreviation R/W Port E Port E data direction register PEDDR H'00 H'FEBD Port E data register PEDR H'00 H'FF6D Port E register PORTE Undefined H'FF5D Port E MOS pull-up control register PEPCR H'00 H'FF74 H'80/H'00 * Port F Port F data direction register...
  • Page 971 14. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte access can be used on these registers, with the access requiring two states (Applies to the F-ZTAT versions but the H8S/2319C F-ZTAT). 15. The SYSCR2 register can only be used in the F-ZTAT versions. In the mask ROM versions this register will return an undefined value if read, and cannot be written to.

  • Page 972: Functions

    Functions MRA—DTC Mode Register A H'F800—H'FBFF Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined         Read/Write DTC Data Transfer Size Byte-size transfer Word-size transfer DTC Transfer Mode Select Destination side is repeat area or block area Source side is repeat area or block area...
  • Page 973 MRB—DTC Mode Register B H'F800—H'FBFF      CHNE DISEL CHNS Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined         Read/Write Reserved Only 0 should be written to these bits DTC Interrupt Select After DTC data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0...
  • Page 974 DAR—DTC Destination Address Register H'F800—H'FBFF - - - - - - Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Initial value - - - fined fined fined fined fined fined fined fined fined fined     ...
  • Page 975 TCR3—Timer Control Register 3 H'FE80 TPU3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Timer Prescaler Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input Internal clock: counts on φ/1024 Internal clock: counts on φ/256 Internal clock: counts on φ/4096...
  • Page 976 TMDR3—Timer Mode Register 3 H'FE81 TPU3   Initial value   Read/Write Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 × ×...
  • Page 977 TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 Initial value IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Read/Write TGR3A I/O Control TGR3A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match Output disabled Initial output is...
  • Page 978 TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TGR3C I/O Control TGR3C Output disabled is output Initial output is 0 output at compare match compare 0 output register * 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
  • Page 979 TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3   TTGE TCIEV TGIED TGIEC TGIEB TGIEA Initial value   Read/Write TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
  • Page 980 TSR3—Timer Status Register 3 H'FE85 TPU3    TCFV TGFD TGFC TGFB TGFA Initial value    Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
  • Page 981 TCNT3—Timer Counter 3 H'FE86 TPU3 Initial value Read/Write Up-counter TGR3A—Timer General Register 3A H'FE88 TPU3 TGR3B—Timer General Register 3B H'FE8A TPU3 TGR3C—Timer General Register 3C H'FE8C TPU3 TGR3D—Timer General Register 3D H'FE8E TPU3 Initial value Read/Write Rev. 5.00, 12/03, page 951 of 1088...
  • Page 982 TCR4—Timer Control Register 4 H'FE90 TPU4  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value  Read/Write Timer Prescaler Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/1024...
  • Page 983 TMDR4—Timer Mode Register 4 H'FE91 TPU4     Initial value     Read/Write Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
  • Page 984 TIOR4—Timer I/O Control Register 4 H'FE92 TPU4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR4A I/O Control TGR4A Output disabled is output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
  • Page 985 TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4    TTGE TCIEU TCIEV TGIEB TGIEA Initial value    Read/Write TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB) by...
  • Page 986 TSR4—Timer Status Register 4 H'FE95 TPU4    TCFD TCFU TCFV TGFB TGFA Initial value    Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
  • Page 987 TCNT4—Timer Counter 4 H'FE96 TPU4 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A—Timer General Register 4A H'FE98 TPU4...
  • Page 988 TCR5—Timer Control Register 5 H'FEA0 TPU5  CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value  Read/Write Time Prescaler Internal clock: counts on φ/1 Internal clock: counts on φ/4 Internal clock: counts on φ/16 Internal clock: counts on φ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on φ/256...
  • Page 989 TMDR5—Timer Mode Register 5 H'FEA1 TPU5     Initial value     Read/Write Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 ×...
  • Page 990 TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR5A I/O Control TGR5A Output disabled is output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...
  • Page 991 TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5    TTGE TCIEU TCIEV TGIEB TGIEA Initial value    Read/Write TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
  • Page 992 TSR5—Timer Status Register 5 H'FEA5 TPU5    TCFD TCFU TCFV TGFB TGFA Initial value    Read/Write R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 •...
  • Page 993 TCNT5—Timer Counter 5 H'FEA6 TPU5 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A—Timer General Register 5A H'FEA8 TPU5...
  • Page 994 P2DDR—Port 2 Data Direction Register H'FEB1 Port 2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register H'FEB2 Port 3   P35DDR P34DDR P33DDR P32DDR P31DDR...
  • Page 995 PBDDR—Port B Data Direction Register H'FEBA Port B PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value Read/Write Specify input or output for individual port B pins PCDDR—Port C Data Direction Register H'FEBB Port C PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR...
  • Page 996 PFDDR—Port F Data Direction Register H'FEBE Port F PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 * Initial value Read/Write Mode 7 * Initial value Read/Write Specify input or output for individual port F pins Note: * Modes 6 and 7 cannot be used in the ROMless versions. PGDDR—Port G Data Direction Register H'FEBF Port G...
  • Page 997 IPRA—Interrupt Priority Register A H'FEC4 Interrupt Controller IPRB—Interrupt Priority Register B H'FEC5 Interrupt Controller IPRC—Interrupt Priority Register C H'FEC6 Interrupt Controller IPRD—Interrupt Priority Register D H'FEC7 Interrupt Controller IPRE—Interrupt Priority Register E H'FEC8 Interrupt Controller IPRF—Interrupt Priority Register F H'FEC9 Interrupt Controller IPRG—Interrupt Priority Register G H'FECA...
  • Page 998 ABWCR—Bus Width Control Register H'FED0 Bus Controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7* Initial value Mode 4 Initial value Read/Write Area 7 to 0 Bus Width Control Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) Note: * Modes 6 and 7 cannot be used in the ROMless versions.

  • Page 999: Bus Controller

    WCRH—Wait Control Register H H'FED2 Bus Controller Initial value Read/Write Area 4 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 5 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted...
  • Page 1000 WCRL—Wait Control Register L H'FED3 Bus Controller Initial value Read/Write Area 0 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Area 1 Wait Control Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted...
  • Page 1001 BCRH—Bus Control Register H H'FED4 Bus Controller    ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 Initial value Read/Write Reserved Only 0 should be written to these bits Burst Cycle Select 0 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 Burst cycle comprises 1 state Burst cycle comprises 2 states...

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H8s/2318 series

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